Author: claimsbot

1. A method for beneficially treating human skin aging comprised of the following steps:
a producing a composition of a non-acidic formulation of copper and zinc chemically bound to a botanical pigment possessing antioxidant qualities; said composition containing a botanical copper-antioxidant-pigment complex and a botanical zinc-antioxidant-pigment complex;
b locating areas on the skin that show signs of photodamage, environmental damage, or aging;
c applying topically to said skin areas said composition of copper-botanical antioxidant complex and zinc-botanical antioxidant complex, the composition resulting in enhanced penetration of the complexes;
d simultaneously delivering pH-activated copper and zinc ions and plant-based antioxidant pigment to said skin damaged areas to treat said areas and to protect against further skin damage.
2. The method of claim 1 wherein said composition is a topical pharmaceutical, cosmeceutical or cosmetic formulation.
3. The method of claim 1 wherein the skin aging, photodamage or environmental damage is manifested by one or more of the following visible signs or symptoms of the skin: skin laxity or sagging, lentigenes or age spots, skin blotchiness, skin sallowness, fine lines and wrinkles, coarse wrinkles, uneven pigmentation or dyschromia, enlarged pores, dryness, and roughness.
4. The method of claim 1, wherein the skin penetration of the copper-antioxidant pigment complex and zinc-antioxidant pigment complex is enhanced by encapsulating the copper-antioxidant pigment complex and zinc-antioxidant pigment complex within a liposome shell.
5. The method of claim 1, wherein the skin penetration of the copper-antioxidant pigment complex and zinc-antioxidant pigment complex are enhanced by one or more of the skin penetrating ingredients that include pentylene glycol, isopentyl glycol, 1, 3-butylene glycol, 1,4-butylene glycol, and ethoxydiglycol, or mixtures of these diglycols.
6. The method of claim 1, wherein the copper-antioxidant pigment complex is sodium-copper-chlorophyllin.
7. The method of claim 1, wherein the zinc-antioxidant pigment complex is sodium-zinc-chlorophyllin.
8. The method of claim 1, wherein the composition is applied to any skin area of the human body showing signs of aging, photodamage, environmental damage or the like.
9. A composition for the topical treatment of human skin aging, due to photodamage or other environmentally-induced damage containing a non-acidic, aqueous, liposomal dispersion of sodium-copper-chlorophyllin and sodium-zinc-chlorophyllin in a pharmaceutical, cosmeceutical or cosmetic vehicle.
10. The composition of claim 9 wherein the sodium-copper-chlorophyllin is used at a concentration in the range of 0.005% to 0.5% by weight of the total composition.
11. The composition of claim 9 wherein the sodium-zinc-chlorophyllin is used at a concentration in the range of 0.005% to 0.5% by weight of the total composition.
12. The composition of claim 9, wherein the composition is enhanced through the addition of other topical anti-aging treatment materials that can include one or more of peptides, sunscreens, isoflavones, flavenoids, isoprenoids, quinones, carotenoids, retinoids, metalloprotease enzyme inhibitors, or other recognized anti-aging actives.
13. The method of claim 1, wherein the composition is in the form of a liquid, gel, spray, lotion, cream, or solid.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A power supply control device comprising:
a boost type power supply controller boosting an input voltage;
a step down power supply controller reducing an output of the boost type power supply controller to output an output voltage;
a first control loop including the boost type power supply controller; and
a second control loop including the step down power supply controller,
wherein the output voltage is controlled by the second control loop during a predetermined period beginning after the power supply control device enters a power-on state, and
wherein the output voltage is controlled by the first control loop after the predetermined period passes.
2. The power supply control device according to claim 1,
wherein the second control loop controls the output voltage with soft-start control during the predetermined period, and stops the control of the output voltage after the predetermined period passes.
3. The power supply control device according to claim 1,
wherein the step down power supply controller is a circuit controlling the output voltage by controlling an on-resistance value of a transistor that receives the output of the boost type power supply controller, and
wherein a value of a voltage output from the boost type power supply controller is obtained by adding a value of a voltage drop at the transistor to a value equal to or greater than the output voltage.
4. The power supply control device according to claim 1,
wherein the second control loop measures a period of time it takes for the output voltage to reach a predetermined voltage, and wherein the predetermined period is the measured period of time.
5. The power supply control device according to claim 1,
wherein the second control loop measures a period of time from the power-on state, and wherein the predetermined period is the measured period of time.
6. A power supply control device comprising:
a boost type power supply controller boosting an input voltage;
a step down power supply controller reducing an output of the boost type power supply controller to output an output voltage; and
a controller controlling a voltage drop amount at the step down power supply controller, and maintaining the voltage drop amount, wherein the boost type power supply controller boosts the input voltage based on the output voltage after a predetermined time from a time the power supply control device enters a power-on state.
7. The power supply control device according to claim 6,
wherein the controller reduces the voltage drop amount during the predetermined period, and maintains the voltage drop amount at a minimum value of the reduced voltage drop amount after the predetermined period passes.
8. The power supply control device according to claim 6,
wherein the step down power supply controller is a circuit controlling the output voltage by controlling an on-resistance of a transistor that receives the output of the boost type power supply controller, and
wherein a value of a voltage output from the boost type power supply controller is obtained by adding a value of a voltage drop at the transistor to a value equal to or greater than the output voltage.
9. The power supply control device according to claim 6,
wherein the controller measures a period of time it takes for the output voltage to reach a predetermined voltage, and wherein the predetermined period is the measured period of time.
10. The power supply control device according to claim 6,
wherein the controller measures a period of time from the power-on state, and wherein the predetermined period is the measured period of time.
11. A power supply control method comprising:
controlling an output voltage with a second control loop having a step down power supply controller;
reducing an output of a boost type power supply controller via the step down power supply controller;
boosting an input voltage via the boost type power supply controller;
outputting the output voltage during a predetermined period beginning at a time a power-on state is entered; and
controlling the output voltage with a first control loop having the boost type power supply controller after the predetermined period passes.

1. A magnetoresistive element comprising a substrate and a multi-layer film formed on the substrate, the multi-layer film comprising a tunnel layer and a pair of magnetic layers that sandwich the tunnel layer,
wherein a resistance value changes with a relative angle formed by magnetization directions of the pair of magnetic layers,
wherein a conductive layer is arranged between the substrate and the tunnel layer, and
wherein the conductive layer is at least one selected from:
a) a conductor composed of at least one selected from Pt, Pd, Ag, Au, C, Si, Ge, Sn and Pb;
b) an amorphous film;
c) a microcrystalline film having an average crystal diameter of 5 nm or less; and
d) a laminate including a Cu film and a non-Cu metal film.
2. The magnetoresistive element as claimed in claim 1, wherein the conductive layer is a non-magnetic film.
3. The magnetoresistive element as claimed in claim 1, wherein the conductive layer is a magnetic film.
4. The magnetoresistive element as claimed in claim 1, wherein the conductive layer is at least one selected from a), b) and c), and wherein the conductive layer has an average thickness of 10 nm or less.
5. The magnetoresistive element as claimed in claim 1, wherein the substrate is polycrystalline.
6. A magnetoresistive element comprising a substrate and a multi-layer film formed on the substrate, the multi-layer film comprising a tunnel layer and a pair of magnetic layers that sandwich the tunnel layer,
wherein a resistance value changes with a relative angle formed by magnetization directions of the pair of magnetic layers,
wherein at least one layer selected from the pair of magnetic layers comprises at least one selected from:
e) a lattice strain expressed by a lattice constant difference in a range of 0.1% to 5% with respect to a lattice constant that is calculated from the crystal structure of said at least one layer;
f) a crystal structure that is different from a preferential crystal structure at the ordinary temperature and the atmospheric pressure; and
g) a polycrystalline structure having an oriented crystal plane controlled to be other than the closest packed plane of the crystal structure of said at least one layer.
7. The magnetoresistive element as claimed in claim 6, wherein the multi-layer film further comprises a crystal-structure controlling layer, wherein the crystal-structure controlling layer is in contact with said at least one layer, and wherein at least one selected from e), f) and g) is introduced into the at least one layer by the crystal-structure controlling layer.
8. The magnetoresistive element as claimed in claim 7, wherein said at least one layer comprises at least e) and at least one element selected from Fe, Co and Ni, and wherein the crystal-structure controlling layer comprises said at least one element and an element other than Fe, Co and Ni.
9. The magnetoresistive element as claimed in claim 6, wherein the multi-layer film comprises a magnetic layer that comprises at least f) and g).
10. The magnetoresistive element as claimed in claim 9, wherein the multi-layer film comprises a magnetic layer that comprises e), f) and g).
11. A magnetoresistive element comprising a substrate and a multi-layer film formed on the substrate, the multi-layer film comprising a tunnel layer and a pair of magnetic layers that sandwich the tunnel layer,
wherein a resistance value changes with a relative angle formed by magnetization directions of the pair of magnetic layers,
wherein at least one layer selected from the pair of magnetic layers comprises at least one element selected from Fe, Co and Ni, and an element other than Fe, Co and Ni, and
wherein an average electron number of said at least one layer is in a range of 23.5 to 25.5 or 26.5 to 36, where the average electron number is a per-atom electron number calculated on the basis of the composition ratio of said at least one layer.
12. The magnetoresistive element as claimed in claim 11, wherein said element other than the magnetic element is at least one selected from Si, Al, Ti, V, Cr, Mn, Ru, Rh, Pd, Os, Ir, Pt, B, C, N and O.
13. The magnetoresistive element as claimed in claim 11, wherein the average electron number is in a range of 24.5 to 25.5.
14. The magnetoresistive element as claimed in claim 11, wherein the average electron number is in a range of 27.5 to 32.5.
15. A magnetoresistive element comprising a substrate and a multi-layer film formed on the substrate, the multi-layer film comprising a tunnel layer and a pair of magnetic layers that sandwich the tunnel layer,
wherein a resistance value changes with a relative angle formed by magnetization directions of the pair of magnetic layers,
wherein at least one layer selected from the layers in the multi-layer film that is other than the pair of magnetic layers comprises an excess element, and the excess element decreases spin polarization in at least one magnetic layer selected from the magnetic layers when the concentration of the excess element in said at least one magnetic layer increases, and
wherein the multi-layer film further comprises an excess-element capturing layer including an alloy or a compound that contains the excess element, and the content of the excess element in the excess-element capturing layer is higher than those in the magnetic layers.
16. The magnetoresistive element as claimed in claim 15, wherein the multi-layer film comprises an excess-element supplying layer, and the content of the excess-element is not lower than that in the excess-element capturing layer.
17. The magnetoresistive element as claimed in claim 16, wherein the excess-element supplying layer is the tunnel layer, and wherein the excess-element is at least one selected from B, C, N and O.
18. The magnetoresistive element as claimed in claim 17, wherein the excess-element capturing layer comprises a compound containing a metal, and the metal has a formation free-energy for a compound selected from an oxide, a nitride, a carbide and a boride that is lower than that of Fe.
19. The magnetoresistive element as claimed in claim 16, wherein the excess-element supplying layer is at least one selected from an antiferromagnetic layer and a laminated ferrimagnetic layer.
20. The magnetoresistive element as claimed in claim 19, wherein the excess-element is at least one selected from Mn and Ru.
21. The magnetoresistive element as claimed in claim 15, wherein the distance between the excess-element capturing layer and at least one selected from the pair of magnetic layers with respect to the thickness direction of the multi-layer film is 10 nm or less.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for fabricating a thin film silicon-on-insulator semiconductor device which comprises:
providing a structure having a layer of semiconductor material, a buried insulation layer located above the layer of semiconductor material, a semiconductor SOI layer of a first conductivity type above the buried insulating layer, gate insulating layer located above selected portions of the semiconductor SOI layer, a gate conductor located above the gate insulating layer, shallow source and drain extensions of a second conductivity type opposite from the conductivity type of the semiconductor SOI layer;
implanting indium ions at a dosage of about 5E13 to about 1.5E14 at an energy level of about 60 to about 125 Kev and an angle \u03b1 of about 0\xb0 to about 45\xb0,
and then annealing the structure at a temperature of about 900\xb0 C. to about 1025\xb0 C. for about 6 to about 25 seconds to provide a pocket halo implant of indium beneath the gate and in a channel region of the semiconductor SOI layer;
and providing source and drain regions of the second conductivity type.
2. The method of claim 1 wherein the dosage is about 1E14.
3. The method of claim 1 wherein the angle \u03b1 is about 0\xb0.
4. The method of claim 1 which provides a peak active indium dopant concentration of about 8\xd71018 atomscm3 and 2\xd71019 atomscm3.
5. The method of claim 1 wherein the layer of semiconductor material comprises silicon.
6. The method of claim 1 wherein the buried insulation layer comprises silicon dioxide.
7. The method of claim 1 wherein the semiconductor SOI layer comprises silicon.
8. The method of claim 1 wherein the semiconductor device is a SOI NMOSFET device.
9. The method of claim 1 wherein the gate insulating layer comprises silicon dioxide.
10. The method of claim 1 wherein the gate conductor comprises polycrystalline silicon.
11. The method of claim 1 wherein the semiconductor device further comprises side wall spacers on the gate conductor prior to providing the source and drain regions.
12. The method of claim 11 wherein the side wall spacers comprise silicon dioxide, silicon nitride or combinations thereof.
13. The method of claim 1 wherein the shallow source and drain extensions are provided by ion implantation at a dosage of about 6E14 to about 9E14 and an energy level of about 10 to about 15 Kev, and the source and drain regions are provided by ion implantation at a dosage of about 3E15 to about 7E15 and an energy level of about 10 to about 15 Kev.
14. The method of claim 1 wherein the shallow source and drain extensions are provided by ion implantation at a dosage of about 7E14 to about 8E14 and an energy level of about 12 to about 13 Kev; and the source and drain regions are provided by ion implantation at a dosage of about 5E15 to about 6E15 and an energy level of about 12 to about 13 Kev.
15. The method of claim 1 which further comprises after providing dopants for the source and drain regions thermally annealing the structure at a temperature of about 950\xb0 C. to about 1050\xb0 C. for about 6 to about 20 seconds.
16. The method of claim 1 wherein the pocket halo implant contacts the gate insulating layer, wherein a portion of the semiconductor SOI layer is disposed between the pocket halo implant and the buried insulation layer, and wherein the shallow source and drain extensions extend above the pocket halo implant and only partly through a thickness of the semiconductor SOI layer in the channel region of the semiconductor SOI layer.