Author: claimsbot

1. A cooling system comprising:
one or more nodes, each node having at least one temperature sensor to monitor a temperature of internal node components;
an air-to-liquid heat exchanger configured to accept a liquid coolant input and to provide cooled air to the one or more nodes;
a temperature sensor to monitor a temperature of the air provided by the air-to-liquid heat exchanger;
a liquid cooling system configured to provide liquid coolant to components of the one or more nodes;
a valve configured to control coolant flow to the air-to-liquid heat exchanger and the liquid cooling system based on the temperature of internal node components and the temperature of the air provided by the air-to-liquid heat exchanger; and
a pump configured to provide liquid coolant to the liquid cooling system and the air-to-liquid heat exchanger, having a pump strength that is based on the temperature of internal node components and the temperature of the air provided by the air-to-liquid heat exchanger.
2. The cooling system of claim 1, further comprising control logic configured to compare a maximum internal node component temperature to a first and second component threshold and to compare the air temperature to a first and second air threshold.
3. The cooling system of claim 2, wherein the control logic is further configured to control the valve and the pump according to said comparisons.
4. The cooling system of claim 1, further comprising a flow rate valve configured to limit a coolant flow to the air-to-liquid heat exchanger based on the temperature of internal node components and the temperature of the air provided by the air-to-liquid heat exchanger.
5. The cooling system of claim 1, further comprising a flow rate valve configured to limit a coolant flow to the liquid cooling system based on the temperature of internal node components and the temperature of the air provided by the air-to-liquid heat exchanger.
6. The cooling system of claim 1, wherein the valve is a three-way valve that connects the air-to-liquid heat exchanger and the liquid cooling system to the pump in parallel.
7. The cooling system of claim 1, wherein the air-to-liquid heat exchanger and the liquid cooling system are connected serially and the valve is a two-way bypass valve.
8. The cooling system of claim 7, wherein the two-way bypass valve provides a bypass for the air-to-liquid heat exchanger, such that opening the two-way bypass valve allows coolant to flow directly to the liquid cooling system.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus comprising:
a printed circuit board;
a first antenna element etched onto the printed circuit board, the first antenna element working within a first frequency band;
a second antenna element etched onto the printed circuit board, the second antenna element working with a second frequency band;
a first RF choke etched onto the printed circuit board near a first end of the printed circuit board, the first RF choke working within the first frequency band; and
a second RF choke etched onto the printed circuit board near the first end of the printed circuit board, the second RF choke working within the second frequency band.
2. The apparatus as in claim 1 further comprising an upper domed body housing the printed circuit board, the first antenna element, the second antenna element, the first RF choke, and the second RF choke.
3. The apparatus as in claim 1 wherein the first frequency band includes a relatively higher frequency band.
4. The apparatus as in claim 3 wherein the first frequency band includes a 5.8 GHz frequency band.
5. The apparatus as in claim 1 wherein the second frequency band includes a relatively lower frequency band.
6. The apparatus as in claim 5 wherein the second frequency band includes a 2.4 GHz frequency band.
7. The apparatus as in claim 1 further comprising a third RF choke embedded in a connector body below the first and second antenna elements.
8. The apparatus as in claim 1 wherein the first antenna element includes a radiator.
9. The apparatus as in claim 8 wherein the first antenna element includes a loop-shaped radiator.
10. The apparatus as in claim 9 wherein a length of the first antenna element is approximately \xbc wavelength.
11. The apparatus as in claim 9 wherein the loop-shaped radiator is symmetrical.
12. The apparatus as in claim 1 wherein the second antenna element includes a radiator.
13. The apparatus as in claim 12 wherein the second antenna element includes a folded radiator.
14. The apparatus as in claim 13 wherein a length of the second antenna element is approximately \xbc wavelength.
15. The apparatus as in claim 13 wherein the second antenna element is integrated into the first antenna element.
16. The apparatus as in claim 13 wherein the folded radiator is bent into two equal parts.
17. The apparatus as in claim 1 wherein the second antenna element acts as an open circuit to the first antenna element.
18. The apparatus as in claim 1 further comprising a connector body for mounting on a plurality of different WiFi access point metal platforms.
19. The apparatus as in claim 18 wherein the connector body includes a connector pin for connecting with the printed circuit board.
20. The apparatus as in claim 1 wherein each of the first and second RF chokes includes a high impedance section.

1. At least one computer-readable medium, having computer-executable instructions which when executed perform steps, comprising:
receiving a request via a process thread having a first memory map associated therewith;
changing a privilege level to a level that allows a map change;
performing the map change to associate a second memory map with the process thread, the second memory map providing different memory access with respect to the first memory map; and
restoring the privilege level to a level that does not allow a map change.
2. At least one computer-readable medium, having computer-executable instructions which when executed perform steps, comprising:
associating first and second address maps with a process, wherein at least the second address map includes a mapping that maps a virtual address to a physical address that is larger than the largest possible virtual memory address;
receiving a request from a thread of the process to change from the first address map to the second address map;
changing the first address map to the second address map; and
using the mapping to access data at a physical memory location having a physical address that is larger than the largest possible virtual memory address.
3. At least one computer-readable medium, having computer-executable instructions which when executed perform steps, comprising:
associating first and second address maps with a process, wherein the second address map provides different memory access with respect to the first memory map;
running trusted code with the first map;
switching to the second map prior to running a first set of untrusted code without switching the process; and
returning to the first map after completion of the untrusted code.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming a gate electrode, comprising the steps of;
forming a lower amorphous silicon layer using silane (SiH4) gas and nitrous oxide (N2O) gas;
forming an upper amorphous silicon layer on the lower amorphous silicon layer; and
crystallizing the lower and upper amorphous silicon layers through a thermal process.
2. The method of forming the gate electrode of claim 1, wherein the lower polysilicon layer, which is crystallized after performing the thermal process, has the grain size which is more uniform and denser than that of the upper polysilicon layer due to a partial oxidation of the lower amorphous silicon layer caused by nitrous oxide (N2O) gas.
3. The method of forming the gate electrode of claim 1, wherein the lower amorphous silicon layer is formed through a lower pressure chemical vapor deposition process.
4. The method of forming the gate electrode of claim 3, wherein the lower pressure chemical vapor deposition process is performed at a temperature of 700 to 900\xb0 C. and a pressure of 0.5 to 2.0 Torr.
5. The method of forming the gate electrode of claim 1, wherein the upper amorphous silicon layer is formed through a lower pressure chemical vapor deposition process.
6. The method of forming the gate electrode of claim 5, wherein the lower pressure chemical vapor deposition process is performed at a temperature of 500 to 650\xb0 C. and a pressure of 0.5 to 2.0 Torr.
7. The method of forming the gate electrode of claim 5, wherein the lower pressure chemical vapor deposition process is performed under an atmosphere of silane (SiH4) gas and phosphine (PH3) gas.