What is claimed is:
1. A semiconductor device comprising:
(a) a semiconductor substrate;
(b) an insulating film formed at a surface of said semiconductor substrate for defining device regions in each of which a semiconductor device is to be fabricated;
(c) a gate electrode formed on said semiconductor substrate;
(d) a sidewall covering said gate electrode therewith; and
(e) drain and source diffusion layers formed at a surface of said semiconductor substrate around said gate electrode,
said sidewall having a sidewall offset extending outwardly of said gate electrode along a surface of said semiconductor substrate in at least one of regions below which said drain and source diffusion layers are to be formed,
at least one of said drain and source diffusion layers extending towards said gate electrode beyond an edge of said sidewall offset.
2. The semiconductor device as set forth in claim 1, wherein said sidewall offset is formed along a surface of said semiconductor substrate in both regions below which said drain and source diffusion layers are to be formed.
3. The semiconductor device as set forth in claim 1, further comprising second diffusion layers formed below said drain and source diffusion layers and surrounding said drain and source diffusion layers.
4. The semiconductor device as set forth in claim 3, wherein said second diffusion layers have a lower impurity-concentration than that of said drain and source diffusion layers.
5. The semiconductor device as set forth in claim 1, further comprising a memory cell formed on said semiconductor substrate.
6. A semiconductor device comprising:
(a) a semiconductor substrate;
(b) an insulating film formed at a surface of said semiconductor substrate for defining device regions in each of which a semiconductor device is to be fabricated;
(c) a gate electrode formed on said semiconductor substrate;
(d) a sidewall covering said gate electrode therewith;
(e) drain and source diffusion layers formed at a surface of said semiconductor substrate around said gate electrode; and
(f) low-resistive wiring layers formed at surfaces of said drain and source diffusion layers, said low-resistive wiring layers being located outwardly beyond a peripheral edge of said sidewall offset,
said sidewall having a sidewall offset extending outwardly of said gate electrode along a surface of said semiconductor substrate in at least one of regions below which said drain and source diffusion layers are to be formed,
at least one of said drain and source diffusion layers extending towards said gate electrode beyond an edge of said sidewall offset.
7. The semiconductor device as set forth in claim 6, wherein said low-resistive wiring layers are composed of TiSi.
8. The semiconductor device as set forth in claim 6, wherein said sidewall offset is formed along a surface of said semiconductor substrate in both regions below which said drain and source diffusion layers are to be formed.
9. The semiconductor device as set forth in claim 6, further comprising second diffusion layers formed below said drain and source diffusion layers and surrounding said drain and source diffusion layers.
10. The semiconductor device as set forth in claim 9, wherein said second diffusion layers have a lower impurity-concentration than that of said drain and source diffusion layers.
11. The semiconductor device as set forth in claim 6, further comprising a memory cell formed on said semiconductor substrate.
12. A method of fabricating a semiconductor device, comprising the steps of:
(a) forming an insulating film at a surface of a semiconductor substrate to thereby define device regions in which a semiconductor device is to be formed;
(b) forming a first well having a first electrical conductivity and a second well having a second electrical conductivity in a first region in which a first transistor is to be fabricated, and further forming a first well having a first electrical conductivity and a second well having a second electrical conductivity in a second region in which a second transistor is to be fabricated;
(c) forming a gate electrode of said first transistor in said first region and a gate electrode of said second transistor in said second region;
(d) forming first drain and source diffusion layers of said first and second transistors in both said first and second regions;
(e) forming a sidewall around said gate electrode of said first transistor, said sidewall having a sidewall offset having an edge remoter from said gate electrode than an edge of said first drain and source diffusion layers on at least one of said first drain and source diffusion layers, and forming a sidewall around said gate electrode of said second transistor; and
(f) forming second drain and source diffusion layers of said first transistor in both said first and second regions.
13. The method as sot forth in claim 12, further comprising the step of lowering a resistance of at least a portion of said second drain and source diffusion layers of said first transistor.
14. The method as set forth in claim 13, wherein said portion is turned into silicide.
15. The method as set forth in claim 12, wherein said sidewall offset is formed in both said first drain and source diffusion layers in said step (e).
16. A method of fabricating a semiconductor device, comprising the steps of:
(a) forming an insulating film at a surface of a semiconductor substrate to thereby define device regions in which a semiconductor device is to be formed;
(b) forming a first well having a first electrical conductivity and a second well having a second electrical conductivity in a first region in which a first transistor is to be fabricated, forming a first well having a first electrical conductivity and a second well having a second electrical conductivity in a second region in which a second transistor is to be fabricated, and forming a well in a third region in which a memory cell is to be fabricated;
(c) forming a gate electrode of said memory cell in said third region;
(d) forming a diffusion layer of said memory cell in said third region;
(e) forming a gate electrode of said first transistor in said first region and a gate electrode of said second transistor in said second region;
(f) forming first drain and source diffusion layers of said first and second transistors in both said first and second regions;
(g) forming a sidewall around said gate electrode of said first transistor, said sidewall having a sidewall offset having an edge remoter from said gate electrode than an edge of said first drain and source diffusion layers on at least one of said first drain and source diffusion layers, and forming a sidewall around said gate electrode of said second transistor; and
(h) forming second drain and source diffusion layers of said first transistor in both said first and second regions.
17. The method as set forth in claim 16, further comprising the step of lowering a resistance of at least a portion of said second drain and source diffusion layers of said first transistor.
18. The method as set forth in claim 17, wherein said portion is turned into suicide.
19. The method as set forth in claim 16, wherein said sidewall offset is formed in both said first drain and source diffusion layers in said step (g).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A wireless transmitter product, comprising:
a charger plug including a distal end that is configured to interface with a power outlet and a proximal end that includes a first magnetic element adjacent therewith; and
a component for housing a functional element of the wireless transmitter product that includes a second magnetic element, the first magnetic element and second element being oriented respectively within the proximal end and the component housing to product magnetic attraction between the component housing and the charger plug.
2. The wireless transmitter product of claim 1 in which the functional element comprises a user interface.
3. The wireless transmitter product of claim 2 in which the user interface includes a display or controls.
4. The wireless transmitter product of claim 1 in which the functional element comprises an FM transmitter.
5. The wireless transmitter product of claim 1 in which the functional element comprises an FM transceiver.
6. The wireless transmitter product of claim 1 in which the charger plug is configured with a circumferential groove that is arranged for receiving a connector cap.
7. The wireless transmitter product of claim 6 in which the connector cap is configured as an elastically deformable body having a through passage that has a inside diameter that is substantially equal to the outside diameter of the circumferential groove so that the connector cap is removably installable in a close fitting manner in the circumferential groove.
8. The wireless transmitter product of claim 6 in which the connector cap includes a device connector slot that is sized to receive a device connector in a close fitting matter so that the device connector is removably insertable into the connector cap.
9. The wireless transmitter product of claim 1 in which the first and second magnetic elements comprise rare earth magnets.
10. The wireless transmitter product of claim 1 in which one of the first or second magnetic elements is a permanent magnet and the other is a ferromagnetic material.
11. An apparatus for coupling a component of a wireless transmitter to a charger plug in the wireless transmitter, comprising:
an elastically deformable body;
a first interface disposed within the body for removably receiving the component, the first interface being configured so that, when received, the component causes the body to elastically deform and impart a clamping force on a portion of the component; and
a second interface disposed within the body for slidably engaging with the charger plug, the second interface being configured so that, when slidably engaged on the charger, the body is elastically deformed.
12. The apparatus of claim 11 in which the elastically deformable body is formed from a polymer.
13. The apparatus of claim 11 in which the second interface comprises a circular through passage that is sized to interface with a circumferentially disposed groove in the charger plug.
14. The apparatus of claim 13 in which the body returns to a substantially un-deformed state when located within the circumferentially disposed groove.
15. The apparatus of claim 11 in which the component includes a device connector that is adapted to interface with an electronic device.
16. The apparatus of claim 15 in which the electronic device is selected from a group consisting of media player, MP3 player, mobile phone, personal digital assistant, smart phone, pocket PC, handheld game device, CD player, DVD player, and combinations thereof.
17. An FM transmitter for use in a vehicle environment comprising:
a charger plug adapted for interfacing with a DC power outlet in the vehicle and including a first magnetic element at its proximal end;
a controller coupled to the charger plug with a first wire and including a user interface on a first face and second magnetic element disposed adjacent to a second face of the controller opposite the first face, the first magnetic and second magnetic elements being oriented to generate magnetic attraction between the controller and the charger plug when the second face and the proximal end are in contact; and
a device connector coupled to the controller with a second wire, the device connector being adapted to interface with a personal media player so that media content stored on the personal media player may be modulated onto a FM signal generated by the FM transmitter that is receivable by an FM radio in the vehicle.
18. The FM transmitter of claim 17 further including an elastically deformable connector cap that includes a first interface for removably receiving a portion of the device connector and retaining the received portion through application of a normal clamping force, and a second interface that is adapted for slideable removable engagement with the charger plug.
19. The FM transmitter of claim 17 in which the first and second magnetic elements are ones of permanent magnets, rare earth magnets, or electromagnets.
20. The FM transmitter of claim 17 in which portions of circuitry used to implement FM transmitter functionality is housed within the controller.