Author: claimsbot

What is claimed is:

1. A vinylpyrrolidone polymer, which contains at least one antioxidant in a ratio of 0.0000130 weight % to the vinylpyrrolidone polymer.
2. A vinylpyrrolidone polymer according to claim 1, wherein the antioxidant is a compound having a phenolic hydroxyl group.
3. A vinylpyrrolidone polymer according to claim 1, wherein the antioxidant is a compound of general formula (1) andor (2) below:
4
wherein each of R1, R2, R3, R4, and R5 is, independently of each other, at least one member selected from the group consisting of a hydrogen atom, alkyl groups, substituted alkyl groups, aryl groups, and substituted aryl groups, wherein R1 and R2, or R3 and R4, may be bonded to each other to form a cyclic structure.
4. A vinylpyrrolidone polymer according to claim 1, wherein the antioxidant includes the joint use of a radical scavenger with a peroxide decomposer.
5. A vinylpyrrolidone polymer according to claim 1, which further contains a radical formation inhibitor.
6. A vinylpyrrolidone polymer, which is adjusted such that the reduction ratio of the K value defined by Fikentscher’s equation will be within 5% when the vinylpyrrolidone polymer is subjected to a forcible test in which the vinylpyrrolidone polymer is kept heated at 120 C. under normal pressure in air for 2 hours.
7. A vinylpyrrolidone polymer, which is adjusted such that the reduction ratio of the K value defined by Fikentscher’s equation will be within 5% when the vinylpyrrolidone polymer is subjected to a promotion test in which the vinylpyrrolidone polymer is kept heated at 50 C. in a solution state for 14 days.
8. A vinylpyrrolidone polymer according to claim 1, pH of the aqueous solution of which with a concentration of 5 weight % is in the range of 4 to 12.
9. A vinylpyrrolidone polymer according to claim 3, pH of the aqueous solution of which with a concentration of 5 weight % is in the range of 4 to 12.
10. A resin composition, which comprises a vinylpyrrolidone polymer as a resin component, and further comprises at least one antioxidant in a ratio of 0.0000130 weight % to the vinylpyrrolidone polymer.
11. A stabilization process for a vinylpyrrolidone polymer, which comprises the step of mixing the vinylpyrrolidone polymer with at least one antioxidant in a ratio of 0.0000130 weight % to the vinylpyrrolidone polymer.
12. A preservation process for a vinylpyrrolidone polymer, which comprises the step of suppressing the oxygen concentration to not higher than 50,000 ppm in a gas phase that contacts with the vinylpyrrolidone polymer.
13. A preservation process for a vinylpyrrolidone polymer according to claim 12, which further comprises the steps of putting the vinylpyrrolidone polymer into an airtight container and evacuating the container.
14. A preservation process for a vinylpyrrolidone polymer according to claim 12, which further comprises the steps of putting the vinylpyrrolidone polymer into an airtight container and displacing air in the container with an inert gas andor carbonic acid gas.
15. A preservation process for a vinylpyrrolidone polymer according to claim 13, which further comprises the steps of putting the vinylpyrrolidone polymer into an airtight container and displacing air in the container with an inert gas andor carbonic acid gas.
16. A preservation process for a vinylpyrrolidone polymer according to claim 12, which further comprises the steps of putting the vinylpyrrolidone polymer into an airtight container and enclosing at least one deoxidizing agent together with the vinylpyrrolidone polymer in the container.
17. A preservation process for a vinylpyrrolidone polymer according to claim 15, which further comprises the steps of putting the vinylpyrrolidone polymer into an airtight container and enclosing at least one deoxidizing agent together with the vinylpyrrolidone polymer in the container.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method of manufacture of ferroelectric memory comprising a ferroelectric film, said method comprising:
assembling a chip of said ferroelectric memory;
writing data to said ferroelectric memory, after the chip assembly process; and,
subjecting said ferroelectric memory, after the data writing process, to heat treatment at a heat treatment temperature T1 ( C.) below the phase transition temperature Tc ( C.) of the ferroelectric film, causing imprinting in said ferroelectric film.
2. The method of manufacture of ferroelectric memory according to claim 1, wherein subjecting said ferroelectric memory to heat treatment is performed at said heat treatment temperature T1 ( C.) such that (Tc150) ( C.)T1 ( C.)(Tc50) ( C.) is satisfied.
3. The method of manufacture of ferroelectric memory according to claim 1, wherein said ferroelectric film is an SrBi2Ta2O9 film and subjecting said ferroelectric memory to heat treatment is performed substantially for one hour, and said heat treatment temperature T1 ( C.) is substantially 220 C.
4. The method of manufacture of ferroelectric memory according to claim 1, wherein read-only memory is manufactured as said ferroelectric memory.
5. The method of manufacture of ferroelectric memory according to claim 1, wherein heat treatment of said ferroelectric memory is performed in said chip assembly process.
6. The method of manufacture of ferroelectric memory according to claim 1, wherein subjecting said ferroelectric film to heat treatment is performed at a heat treatment temperature t1 ( C.) for stabilizing the polarization state of said ferroelectric film in the polarization direction corresponding to said data.
7. A method of manufacture of ferroelectric memory comprising:
assembling a chip of said ferroelectric memory which has a ferroelectric film;
writing data to said ferroelectric memory, after the chip assembly process;
providing a read-only memory through subjecting said ferroelectric memory, after the data writing process, to a first heat treatment at a heat treatment temperature T1 ( C.) below the phase transition temperature Tc ( C.) of the ferroelectric film; and
selecting said ferroelectric film comprised by said read-only memory, after the first treatment process, to a second heat treatment at a heat treatment temperature T2 ( C.) equal to or higher than the phase transition temperature Tc ( C.) of the ferroelectric film.
8. The method of manufacture of ferroelectric memory according to claim 7, wherein subjecting said ferroelectric memory to heat treatment is performed at said heat treatment temperature T1 ( C.) such that (Tc150) ( C.)T1 ( C.)(Tc50)( C.) is satisfied.
9. The method of manufacture of ferroelectric memory according to claim 7, wherein said ferroelectric film is an SrBi2Ta2O9 film, said first heat treatment process is performed substantially for one hour and said heat treatment temperature T1 ( C.) is substantially 220 C., and said second heat treatment process is performed at said heat treatment temperature T2 ( C.) of substantially 350 C. or higher.
10. The method of manufacture of ferroelectric memory according to claim 7, wherein random-access memory is manufactured as said ferroelectric memory after said second heat treatment process.
11. The method of manufacture of ferroelectric memory according to claim 7, wherein said ferroelectric memory is subjected to heat treatment in said chip assembly process.
12. The method of manufacture of ferroelectric memory according to claim 7, wherein said second heat treatment temperature T2 ( C.) is approximately the phase transition temperature Tc ( C.) of said ferroelectric film.
13. The method of manufacture of ferroelectric memory according to claim 7, wherein said second heat treatment process causes the remanent polarization of said ferroelectric film to be zero.

1. A system, comprising:
a processor coupled to an address bus;
a cache memory that couples to the address bus and comprises cache data, the cache memory divided into a plurality of ways; and
a store buffer that couples to the address bus, and comprises store buffer data, a store buffer way and a store buffer index;
wherein the processor selects the store buffer data for use by a data load operation if a selected way of the plurality of ways matches the store buffer way, and if at least part of the bus address matches the store buffer index.
2. The system of claim 1, wherein the store buffer data, the store buffer way and the store buffer index are saved into the store buffer by the processor during a data store operation.
3. The system of claim 1, wherein the store buffer data is valid if a branch of a program executed by the processor is identified as an actual program branch taken.
4. The system of claim 1, wherein the store buffer data is not valid if a branch of a program executed by the processor is identified as a mispredicted program branch.
5. The system of claim 1, wherein the processor deselects the store buffer data if a branch of a program executed by the processor is identified as a mispredicted program branch.
6. The system of claim 1, further comprising
a hashed address generator that couples to the address bus and converts a bus address present on the address bus into a current hashed address; and
a hash memory that couples to the address bus and comprises a saved hashed address associated with the cache data;
wherein the current hashed address is compared to the saved hashed address; and
wherein the result of the comparison of the hashed addresses is a current way value indicative of the selected way.
7. The system of claim 6,
wherein the hash memory is organized as a plurality of hash ways;
wherein the plurality of hash ways are enabled when the current hashed address is compared against the saved hashed address; and
wherein a hash way of the plurality of hash ways comprises the saved hashed address.
8. The system of claim 1, wherein the system is a communication system.
9. The system of claim 1, where the system is a memory cache controller.
10. A processor, comprising:
an address bus;
a processor core coupled to the address bus;
a cache memory system that couples to the address bus, is divided into a plurality of sub-arrays, and comprises cache data; and
a store buffer that couples to the address bus, and comprises store buffer data, a store buffer way and a store buffer index;
wherein the processor core uses the store buffer data in a data load operation if a value representing a selected sub-array of the plurality of sub-arrays matches the store buffer way, and if at least a portion of the bus address matches the store buffer index.
11. The processor of claim 10, wherein the processor core performs a data store operation that saves the store buffer data, the store buffer way and the store buffer index to the store buffer.
12. The processor of claim 10, wherein the store buffer data is marked as valid if a branch of a program executed by the processor core is identified as an actual program branch taken.
13. The processor of claim 10, wherein the store buffer data is marked not valid and is not used by the data load operation if a branch of a program executed by the processor core is identified as a mispredicted program branch.
14. The processor of claim 10, further comprising
a hashed address generator that couples to the address bus and converts a bus address present on the address bus into a current hashed address; and
a hash memory that couples to the address bus and comprises a saved hashed address associated with the cache data;
wherein the current hashed address is compared to the saved hashed address; and
wherein the result of the comparison of the hashed addresses is a current way value indicative of the selected way.
15. The processor of claim 14,
wherein the hash memory is organized as a plurality of hash arrays;
wherein the plurality of hash arrays are enabled when the current hash code is compared against the saved hash code; and
wherein a hash array of the plurality of hash arrays comprises the saved hash code.
16. A method, comprising:
generating a current hash code by logically combining a plurality of address bits of a current address;
identifying a selected way if the current hash code matches one of a plurality of stored hash codes; and
selecting saved cache data held in a store buffer if the selected way matches a saved way held in the store buffer, and if at least part of the current address matches a saved cache address held in the store buffer.
17. The method of claim 16, further comprising storing the saved cache address, the saved way and the saved cache data to the store buffer.
18. The method of claim 16, further comprising identifying the cache data in the store buffer as valid after classifying a branch of an executing program as an actual program branch.
19. The method of claim 16, further comprising ending the selecting of the saved cache data after classifying a branch of an executing program as a mispredicted program branch.
20. The method of claim 16, further comprising identifying the cache data in the store buffer as invalid after classifying a branch of an executing program as a mispredicted program branch.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A bicycle fork having a cylindrical steerer tube, a crown and a pair of fork arms for mounting of a front wheel therebetween
the crown having the steerer tube extending upwardly therefrom to an upper distal end of the steerer tube,
the crown having the fork arms extending downwardly therefrom to lower distal ends of the fork arms,
the steerer tube adapted to extend through a bicycle frame to rotatably couple the fork to the bicycle frame,
characterized by:
the steerer tube having an inner tube of fibre composite material and
a plated layer of metal circumferentially about a section of the inner tube forming an exterior surface of the steerer tube over the section of the inner tube,
wherein the plated layer of metal on the steerer tube has a thickness between 0.001 inches and 0.04 inches.
2. The bicycle fork as claimed in claim 1 wherein the steerer tube has proximate the upper distal end an upper clamp portion adapted for engagement by a clamp mechanism of a bicycle handlebar and the steerer tube has proximate the crown a lower journal portion adapted and to extend through the bicycle frame and be journalled therein, the plated layer of metal circumferentially about at least one of the upper clamp portion and the lower journal portion.
3. The bicycle fork as claimed in claim 2 wherein the plated layer of metal is circumferentially about the upper clamp portion.
4. The bicycle fork as claimed in claim 2 wherein the plated layer of metal is circumferentially about the lower journal portion.
5. The bicycle fork as claimed in claim 3 wherein the plated layer of metal on the steerer tube has a thickness between 0.001 inches and 0.01 inches.
6. The bicycle fork as claimed in claim 4 wherein the plated layer of metal on the steerer tube has a thickness between 0.001 inches and 0.01 inches.
7. The bicycle fork as claimed in claim 1 wherein the fibre composite is selected from a group consisting of one or more of glass, Kevlar and carbon.
8. The bicycle fork as claimed claims 7 wherein the plated layer of metal is selected from a group consisting of one or more of Ag, Au, Cd, Co, Cr, Cu, Fe, Ir, Ni, Pb, Pd, Pt, Rh, Sn, and Zn.
9. The bicycle fork as claimed in claim 8 wherein the plated layer of metal has the alloying component selected from a group consisting of B, C, Mn, Mo, P, S, Si, and W.
10. The bicycle fork as claimed in claim 3 wherein the fibre composite is selected from a group consisting of one or more of glass, Kevlar and carbon.
11. The bicycle fork as claimed claims 10 wherein the plated layer of metal is selected from a group consisting of one or more of Ag, Au, Cd, Co, Cr, Cu, Fe, Ir, Ni, Pb, Pd, Pt, Rh, Sn, and Zn.
12. The bicycle fork as claimed in claim 11 wherein the layer of metal has the alloying component selected from a group consisting of B, C, Mn, Mo, P, S, Si, and W.
13. The bicycle fork as claimed in claim 2 wherein the inner tube has an internal surface and a second layer of metal circumferentially about a section of the internal surface of the inner tube.
14. The bicycle fork as claimed in claim 13 wherein the second layer of metal on the steerer tube has a thickness between 0.001 inches and 0.04 inches.
15. The bicycle fork as claimed in claim 13 wherein at least one of the layer of metal and the second layer of metal on the steerer tube has a thickness between 0.001 inches and 0.01 inches.
16. The bicycle fork as claimed in claim 4 wherein the crown is fibre composite material and a plated layer of metal extends over the section of the crown forming an exterior surface of the steerer tube over the section of the crown.
17. A bicycle fork having a cylindrical steerer tube, a crown and a pair of fork arms for mounting of a front wheel therebetween
the crown having the steerer tube extending upwardly therefrom to an upper distal end of the steerer tube,
the crown having the fork arms extending downwardly therefrom to lower distal ends of the fork arms;
the steerer tube having proximate the upper distal end an upper clamp portion adapted for engagement by a clamp mechanism of a bicycle handlebar,
characterized by:
the steerer tube having an inner tube (37) of fibre composite material;
the inner tube is plated with a layer of metal circumferentially about a section of the upper clamp portion of the inner tube (37) forming an exterior surface the steerer tube over the upper clamp portion,
wherein the plated layer of metal on the steerer tube has a thickness between 0.001 inches and 0.04 inches.
18. A bicycle comprising a bicycle frame, a front fork and a handlebar;
the fork having a cylindrical steerer tube, a crown and a pair of fork arms for mounting of a front wheel therebetween,
the crown having the steerer tube extending upwardly therefrom to an upper distal end of the steerer tube,
the crown having the fork arms extending downwardly therefrom to lower distal ends of the fork arms;
the steerer tube extending through the bicycle frame to rotatably couple the fork to the bicycle frame,
the steerer tube above the crown having a lower journal portion and an upper clamp portion;
the steerer tube extending through a bicycle frame with the lower journal portion of the steerer tube journalled in the bicycle frame to rotatably couple the fork to the bicycle frame,
the upper clamp portion extending upwardly past the bicycle frame;
the handlebar having a clamp mechanism for engagement circumferentially about the upper clamp portion of steerer tube;
the clamp mechanism removably securing the handlebar to the steerer tube against relative rotation and against removal by applying forces to the exterior surface of the steerer tube about the upper clamp portion,
the steerer tube having an inner tube of fibre composite material and
a plated layer of metal circumferentially about a section of at least one of the upper clamp portion and the lower journal portion of the inner tube forming an exterior surface of the steerer tube over the section of the inner tube;
wherein the plated layer of metal on the steerer tube has a thickness between 0.001 inches and 0.04 inches.
19. The bicycle fork as claimed in claim 17 wherein the plated layer of metal on the steerer tube has a thickness between 0.001 inches and 0.01 inches.
20. The bicycle as claimed in claim 18 wherein the plated layer of metal on the steerer tube has a thickness between 0.001 inches and 0.01 inches.