1460741088-f33cf208-aaed-458a-8f12-556339788898

1. Card holder for a mobile electronic device for receiving accessory cards, said card holder comprising:
a substantially cuboidal housing having an open front face for inserting accessory cards, said housing being constituted by a back face, a left and a right lateral face, and a top and a bottom face;
at least two guiding elements protruding from the interior side of said left and right lateral faces, respectively, and extending parallel to and between said top and said bottom face;
wherein:
said guiding elements define an upper slot of a first height h1 between said top face and said guiding elements and a lower slot of a second height h2 between said bottom face and said guiding elements, for receiving accessory cards of first height h1 and second height h2, respectively;
said upper and said lower slots together define a combined slot for receiving an accessory card of a third height h3;
said guiding elements are split into upper and lower guiding element sections associated to said upper and lower slots, respectively; and
said upper and lower guiding element sections are resiliently arranged on said left and right lateral faces, such that the guiding element section associated to a respective slot is pushed aside by an accessory card of first height h1 being inserted into that slot, such that said accessory card of first height can be received in that slot unobstructed by the associated guiding element section.
2. Card holder according to claim 1, wherein said guiding elements are resiliently arranged on said left and right lateral faces, in order to be pushed aside by an accessory card of a third height h3 being inserted into said combined slot, such that said accessory card of third height can be received in said card holder unobstructed by said guiding elements.
3. Card holder according to claim 1, further comprising at least one resilient element arranged on the inner side of said top or said bottom face for spring-biasing accessory cards received in said card holder towards said bottom or said top face, respectively.
4. Card holder according to claim 1, further comprising an electrical interface adapted for electrically contacting an accessory card of the third height.
5. Card holder according to claim 1, wherein:
said guiding elements are constituted by spring-biased guiding rails; and
said guiding rails are formed tapering towards the open front face of said housing.
6. Card holder according to claim 1, wherein said guiding elements are constituted by resilient curved strips.
7. Card holder according to claim 1, wherein said guiding elements are constituted by resilient tongues.
8. Electronic device, comprising a card holder according to claim 1.
9. Device according to claim 8, wherein said electronic device is a mobile phone.
10. A mobile phone comprising a card holder for receiving an accessory card, wherein the card holder comprises:
a substantially cuboidal housing having an open front face for inserting accessory cards, the housing including a back face, a left and a right lateral face, and a top and a bottom face;
at least two guiding elements protruding from the interior side of said left and right lateral faces, respectively, and extending parallel to and between said top and said bottom face;
wherein:
said guiding elements define an upper slot of a first height between said top face and said guiding elements and a lower slot of a second height between said bottom face and said guiding elements, for receiving accessory cards of first height and second height respectively;
said upper and said lower slots together define a combined slot for receiving an accessory card of a third height;
said guiding elements are split into upper and lower guiding element sections associated to said upper and lower slots, respectively; and
said upper and lower guiding element sections are resiliently arranged on said left and right lateral faces, such that the guiding element section associated to a respective slot is pushed aside by an accessory card of first height being inserted into that slot, such that said accessory card of first height can be received in that slot unobstructed by the associated guiding element section.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A static random access memory (SRAM) cell, comprising:
a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array, the wordline landing pad in the first conductive layer being electrically isolated from all gate contacts of the neighboring memory cell;
a second conductive layer including a wordline coupled to the wordline landing pad in the first conductive layer;
a first via coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer; and
a second via coupling the wordline landing pad and the wordline of the second conductive layer.
2. The SRAM cell of claim 1, in which the first conductive layer including the wordline landing pad is fabricated with a self-aligned dual patterning process.
3. The SRAM cell of claim 1, in which the first via and the second via are manufactured in a multiple patterning process.
4. The SRAM cell of claim 1, in which the via in a location corresponding to a first via location is omitted in the neighboring memory cell.
5. The SRAM cell of claim 1, comprising a six-transistor memory cell.
6. The SRAM cell of claim 1 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.
7. A method of fabricating a semiconductor device comprising:
fabricating a pass transistor and a neighbor transistor that is adjacent to the pass transistor on a substrate, the pass transistor and the neighbor transistor both containing a gate contact;
fabricating a first via on the gate contact that is on a pass transistor gate;
forming a first conductive layer on the first via that overlaps both the pass transistor and the neighbor transistor;
fabricating a second via on the first conductive layer; and
fabricating a first wordline on the second via and a second wordline aligned with the neighbor transistor.
8. The method of claim 7, in which fabricating the pass transistor and the neighbor transistor on the substrate comprises:
forming at least two material wells in the substrate;
fabricating an insulating layer over the at least two material wells; and
fabricating a conductive gate on the insulating layer.
9. The method of claim 7, in which a layer of interlayer dielectric material separates the gate contact on the neighbor transistor and the first conductive layer.
10. The method of claim 7, in which a layer of interlayer dielectric material separates the first conductive layer and the second wordline.
11. The method of claim 7, in which the first wordline and the second wordline are fabricated from a second conductive layer.
12. The method of claim 7, further comprising incorporating the semiconductor device into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.
13. A static random access memory (SRAM) cell, comprising:
a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array, the wordline landing pad in the first conductive layer being electrically isolated from all gate contacts of the neighboring memory cell;
a second conductive layer including a wordline coupled to the wordline landing pad in the first conductive layer;
a first means for coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer; and
a second means for coupling the wordline landing pad and the wordline of the second conductive layer.
14. The SRAM cell of claim 13, in which the first conducting layer including the wordline landing pad is fabricated with a self-aligned dual patterning process.
15. The SRAM cell of claim 13, in which the first coupling means and the second coupling means are manufactured in a multiple patterning process.
16. The SRAM cell of claim 13, in which a via in a location corresponding to a location of the first means is omitted in the neighboring memory cell.
17. The SRAM cell of claim 13, comprising a six-transistor memory cell.
18. The SRAM cell of claim 13 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.
19. A method of fabricating a semiconductor device comprising the steps of:
fabricating a pass transistor and a neighbor transistor that is adjacent to the pass transistor on a substrate, the pass transistor and the neighbor transistor both containing a gate contact;
fabricating a first via on the gate contact that is on a pass transistor gate;
forming a first conductive layer on the first via that overlaps both the pass transistor and the neighbor transistor;
fabricating a second via on the first conductive layer; and
fabricating a first wordline on the second via and a second wordline aligned with the neighbor transistor.
20. The method of claim 19, further comprising the step of incorporating the semiconductor device into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

1460741080-6e9b4192-e6e8-4f94-8ed1-e14c5957239f

1. An improved trocar of the type including a fixed-radius tubular element having a trocar valve at a proximal end thereof, wherein the improvement comprises: a plurality of tubular elements each having a different fixed diameter and means for detachably securing the trocar valve thereto; and means defining a radially expandable axial lumen for selectively receiving and conforming to any of said plurality of tubular elements, whereby said defining means is percutaneously introducible to provide an access lumen for selectively introducing and interchanging said tubular elements into said access lumen of said defining means, wherein the trocar valve is selectively attached to said tubular element after said tubular element has been introduced into said access lumen.
2. An improved trocar as in claim 1, wherein the defining means comprises an elongate radially expandable tubular braid and means at a distal end of the braid for puncturing tissue as the braid is percutaneously advanced.
3. An improved trocar as in claim 2, wherein the puncturing means comprises an elongate penetrating element having a sharpened distal tip and being removably received within an axial lumen of the elongate radially expandable tubular braid.
4. An improved trocar as in claim 3, wherein each tubular element includes a rod received in an axial lumen thereof, wherein the rod has tapered distal end which extends distally from a distal end of the tubular element to facilitate insertion into the axial lumen of the elongate radially expandable tubular braid.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A microcontroller-implemented method, comprising:
determining a mode of a microcontroller; and
if the mode is a compatibility mode, modifying a clock source of the microcontroller to increase instruction execution time.
2. The method of claim 1, where modifying further comprises:
selecting one or more scaling factors or wait state factors; and
applying the one or more scaling factors or wait state factors to the clock source.
3. The method of claim 1, where the one or more scale factors or wait state factors are functions of a current instruction.
4. The method of claim 1, where the one or more scale factors or wait state factors are a constant value.
5. The method of claim 1, where the one or more scale factors or wait state factors are based on an architecture of the microcontroller.
6. The method of claim 1, where the instruction execution time is increased based on the formula T2(I)=T1(I)*S(I)+W(I), where T1 is an instruction execution time for a first microcontroller mode and T2 is an instruction execution time for a second microcontroller mode, I is a current instruction, and S(I) is a scale factor and W(I) is a wait cycle associated with the instruction I.
7. The method of claim 1, where the instruction execution time is increased based on the formula T2(I)=((T1(I)+A(I))*B(I)+C(I))*D, where T1 is an instruction execution time for a first microcontroller mode and T2 is an instruction execution time for a second microcontroller mode, I is a current instruction, D is a divider adjustment representing a quantity adjustment provided by a clock divider, A(I) represents a number of wait states, each wait state scaled by a wait scaling factor B(I) or the divider adjustment D, and C(I) is a further adjustment.
8. The method of claim 7, further comprising:
prescaling the clock source by the factor D prior to modifying the clock source.
9. The method of claim 1, where modifying instruction execution time includes gating or dividing the clock source.
10. A microcontroller-implemented method, comprising:
obtaining a first instruction;
executing the instruction in accordance with a first mode, including executing the first instruction over a first instruction execution time;
obtaining a second instruction; and
executing the second instruction in accordance with a second mode, including executing the second instruction over a second instruction execution time, where the first instruction and the second instruction are the same, and the second instruction execution time is longer than the first instruction execution time.
11. The method of claim 10, where executing the second instruction in accordance with a second mode includes gating or dividing a clock source.
12. The method of claim 10, where executing the second instruction in accordance with a second mode comprises:
selecting one or more scaling factors or wait state factors; and
applying the one or more scaling factors or wait state factors to a clock source of the microcontroller.
13. The method of claim 10, where the one or more scale factors or wait state factors are functions of a current instruction.
14. The method of claim 10, where the one or more scale factors or wait state factors are a constant value.
15. The method of claim 10, where the one or more scale factors or wait state factors are based on an architecture of the microcontroller.
16. The method of claim 10, where the second instruction execution time is increased from the first instruction execution time based on the formula T2(I)=T1(I)*S(I)+W(I), where T1 is the first instruction execution time for the first mode and T2 is a second instruction execution time for the second mode, I is a current instruction, and S(I) is a scale factor and W(I) is a wait cycle associated with the instruction I.
17. The method of claim 10, where the second instruction execution time is increased based on the formula T2(I)=((T1(I)+A(I))*B(I)+C(I))*D, where T1 is the first instruction execution time for the first mode and T2 is the second instruction execution time for the second mode, I is a current instruction, D is a divider adjustment representing a quantity adjustment provided by a clock source divider, A(I) represents a number of wait states, each wait state scaled by a wait scaling factor B(I) or the divider adjustment D, and C(I) is a further adjustment.
18. A microcontroller with compatibility mode, comprising:
an instruction register operable for storing an instruction;
a clock control operable for modifying a clock source if the microcontroller is in compatibility mode; and
a processor operable for executing the instruction using the modified clock source.
19. The microcontroller of claim 18, if the microcontroller is not in compatibility mode, the processor is operable for executing the instruction using an unmodified clock source.
20. The microcontroller of claim 18, further comprising:
a clock divider operable for dividing the clock source prior to the clock control modifying the clock source.
21. The microcontroller of claim 18, further comprising:
a mode selector operable for selecting compatibility mode.
22. The microcontroller of claim 18, where the clock control includes a finite state machine that is operable to modify the clock source using clock division or clock gating to increase execution time of the instruction.
23. The microcontroller of claim 18, further comprising:
a decoder operable for providing values of instruction dependent factors used to modify the execution time of the instruction.
24. The microcontroller of claim 23, where the execution time of the instruction is increased based on the formula T2(I)=T1(I)*S(I)+W(I), where T1 is a first instruction execution time for standard mode and T2 is a second instruction execution time for compatibility mode, I is a current instruction, and S(I) and W(I) are the instruction dependent factors.
25. The microcontroller of claim 23, where the execution time of the instruction is increased based on the formula T2(I)=((T1(I)+A(I))*B(I)+C(I))*D, where T1 is a first instruction execution time for standard mode and T2 is the second instruction execution time for compatibility mode, I is a current instruction, D is a divider adjustment representing a quantity adjustment provided by a clock source divider, A(I) represents a number of wait states, each wait state scaled by a wait scaling factor B(I) or the divider adjustment D, and C(I) is a further adjustment.