Author: claimsbot

1. An X-ray tube comprising:
a cathode emitting electrons;
an anode accelerating emitted electrons;
a target with which accelerated electrons collide and thereby generate X-rays; and
an X-ray shielding member disposed so as to surround a surface of the target facing the cathode, and allowing the electrons to pass through an electron passing hole toward the target,
wherein separately from an opening of the electron passing hole facing the cathode, the X-ray tube has a gas exhaust path allowing communication between the inside and outside of the electron passing hole.
2. The X-ray tube according to claim 1, wherein as the gas exhaust path, a through-hole is formed in the X-ray shielding member.
3. The X-ray tube according to claim 2, wherein the through-hole is formed such that all straight lines imaginarily passing through the through-hole from the position of collision of electrons with the target intersect with the inner wall surface of the through-hole.
4. The X-ray tube according to claim 1, wherein as the gas exhaust path, a gap is formed around an end of the X-ray shielding member facing the anode.
5. The X-ray tube according to claim 4, wherein an auxiliary X-ray shielding member is provided on part of the anode around the X-ray shielding member.
6. The X-ray tube according to claim 1, wherein at least the inner wall surface of the electron passing hole is formed of a conductive material, and the inner wall surface can be controlled at the same potential as the anode.
7. The X-ray tube according to claim 6, wherein the inner wall surface of the X-ray shielding member and the anode are grounded.
8. The X-ray tube according to claim 1, wherein the X-ray tube is a transmission type X-ray tube in which the X-rays are emitted outward from a surface of the target opposite the electron collision surface.
9. The X-ray tube according to claim 1, wherein the cathode is a cold cathode.
10. An X-ray photographing apparatus comprising:
an X-ray tube comprising:
a cathode emitting electrons;
an anode accelerating emitted electrons;
a target with which accelerated electrons collide and thereby generate X-rays; and
an X-ray shielding member disposed so as to surround a surface of the target facing the cathode, and allowing the electrons to pass through an electron passing hole toward the target,
wherein separately from an opening of the electron passing hole facing the cathode, the X-ray tube has a gas exhaust path allowing communication between the inside and outside of the electron passing hole;

an X-ray detecting unit that detects X-rays emitted from the X-ray tube and passing through a subject; and
a control unit that controls the X-ray tube and the X-ray detecting unit in a coordinated manner.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated circuit comprising:
a memory that stores a first task list and a second task list, wherein the first task list includes task instructions, and wherein the second task list includes task instructions;
a first bus coupled to the memory;
a processor adapted to write task instructions into the memory across the first bus;
a first buffer;
a second buffer;
a third buffer;
a second bus coupled to the memory;
a first sub-circuit comprising:
a first processing circuit adapted to read first data from the first buffer, to process the first data thereby generating second data, and to write the second data into the second buffer; and
a first task manager adapted to read a first task instruction of the first task list from the memory across the second bus, to interpret the first task instruction, and to configure the first processing circuit based on a result of the interpreting; and

a second sub-circuit comprising:
a second processing circuit adapted to read the second data from the second buffer, to process the second data thereby generating third data, and to write the third data into the third buffer; and
a second task manager adapted to read a second task instruction of the second task list from the memory across the second bus, to interpret the second task instruction, and to configure the second processing circuit based on a result of the interpreting.
2. The integrated circuit of claim 1, wherein the first task manager is adapted to interpret a plurality of different task instructions, and wherein each of the different task instructions can be executed by the first sub-circuit such that the first processing circuit performs a different processing operation.
3. The integrated circuit of claim 1, further comprising:
a wall clock timer that outputs a sequence of timer count values, wherein the first task instruction read by the first task manager includes a first timer count field, wherein the first processing circuit begins the processing of the first data when a value of the first timer count field substantially equals a first timer count value of the sequence.
4. The integrated circuit of claim 1, further comprising:
a wall clock timer, wherein the first task instruction includes a first timer count value that causes the first task instruction to be executed by the first sub-circuit at a first particular time as indicated by the wall clock timer.
5. The integrated circuit of claim 4, wherein the wall clock timer comprises a task manager, and wherein the task manager of the wall clock timer is adapted to read task instructions across the second bus from a timer task list stored in the memory.
6. The integrated circuit of claim 1, wherein the first task manager includes a first pointer register, wherein the processor is adapted to write a first pointer value into the first pointer register of the first task manager across the second bus, wherein the first pointer value points to location in a circular buffer portion of the memory that contains the first task list.
7. The integrated circuit of claim 6, wherein the first task manager responds to a writing of the first pointer register by reading a task instruction out of the first task list.
8. The integrated circuit of claim 1, wherein the second task list includes a third task instruction, wherein the second task manager reads the third task instruction from the memory across the second bus, interprets the third task instruction, and executes the third task instruction by starting the second processing circuit upon assertion of a signal received from the first processing circuit.
9. The integrated circuit of claim 1, further comprising:
a third sub-circuit comprising:
a third processing circuit adapted to output a signal from the integrated circuit; and
a third task manager adapted to read a third task instruction of a third task list from the memory across the second bus, to interpret the third task instruction, and to configure the third processing circuit based on a result of the interpreting.
10. The integrated circuit of claim 1, further comprising:
a third sub-circuit comprising:
a data mover engine; and
a third task manager adapted to read a third task instruction of a third task list from the memory across the second bus, to interpret the third task instruction, and to configure the data mover engine based on a result of the interpreting.
11. The integrated circuit of claim 1, wherein the second bus comprises:
a first sub-bus that couples the processor to pointer registers in the first task manager and the second task manager, wherein the processor writes pointer values across the first sub-bus into the pointer registers; and
a second sub-bus that couples the memory to the first task manager and to the second task manager, wherein the first and second task mangers read task instructions from the memory across the second sub-bus.
12. The integrated circuit of claim 1, wherein the memory, the first bus, and the processor together form a tightly coupled memory (TCM) system.
13. The integrated circuit of claim 1, wherein the memory is accessible by the processor via the first bus with a smaller memory access latency than the memory is accessible via the second bus by the first and second task managers.
14. The integrated circuit of claim 1, wherein the first and second processing circuits are dedicated hardware circuits that do not fetch instructions.
15. The integrated circuit of claim 1, wherein the first task instruction includes a source address field, and a destination address field, wherein a source address value in the source address field indicates a source location in the first buffer, and wherein a destination address value in the destination address field indicates a destination location in the second buffer.
16. The integrated circuit of claim 1, wherein the processor writes a third task instruction into the first task list while the first sub-circuit is executing the first task instruction.
17. The integrated circuit of claim 1, wherein the first sub-circuit reads a push task instruction from the first task list and executes the push task instruction, wherein execution of the push task instruction by the first sub-circuit causes the first sub-circuit to write information into the memory across the second bus.
18. An integrated circuit comprising:
a Tightly Coupled Memory (TCM) system comprising a processor that is tightly coupled to a memory via a first bus, wherein the memory stores a plurality of task lists;
a timer; and
a plurality of sub-circuits, wherein each sub-circuit reads task instructions via a second bus from a task list that corresponds to the sub-circuit and executes the task instructions, wherein the task lists include a push task instruction that when executed by a sub-circuit causes information to be written by the sub-circuit into the memory, wherein the task lists include a configuration task instruction that when executed by a sub-circuit causes the sub-circuit to be configured in a particular way determined by the configuration task instruction, wherein the task lists include a timestamp task instruction that contains a timer count field, wherein execution of the timestamp task instruction is started by a sub-circuit at a time indicated by a timer count value in the timer count field, and wherein the task lists include a hardware signal event task instruction, wherein execution of the hardware signal event task instruction is started by a sub-circuit upon assertion of a signal generated by another sub-circuit.
19. A method comprising:
storing a first task list and a second task list in a memory, wherein a processor, a first bus, and the memory form a Tightly Coupled Memory (TCM) system;
a first sub-circuit reading a first task instruction of the first task list from the memory across a second bus;
the first sub-circuit performing a first operation indicated by the first task instruction;
a second sub-circuit reading a second task instruction of the second task list from the memory across the second bus; and
the second sub-circuit performing a second operation indicated by the second task instruction, wherein the processor, the first bus, the second bus, the memory, the first sub-circuit and the second sub-circuit are parts of an integrated circuit.
20. The method of claim 19, wherein the first operation involves the first sub-circuit writing data into a buffer, and wherein the second operation involves the second sub-circuit reading the data out of the buffer.
21. The method of claim 20, wherein the first task instruction includes a destination address field, wherein a destination address value in the destination address field indicates a location in the buffer where the first sub-circuit writes the data.
22. The method of claim 20, wherein the second task instruction includes a source address field, wherein a source address value in the source address field indicates a location in the buffer from which the second sub-circuit reads the data.
23. The method of claim 19, further comprising:
storing a timestamp task instruction in the memory in the first task list, wherein the timestamp task instruction has a timer count field, wherein execution of the timestamp task instruction by the first sub-circuit is started at a time indicated by a value in the timer count field.
24. The method of claim 19, further comprising:
storing a push task instruction in the first task list, wherein an execution of the push task instruction by the first sub-circuit results in the first sub-circuit writing information across the second bus into the memory.
25. An apparatus comprising:
a memory that stores a first task list and a second task list;
a processor that is tightly coupled to the memory via a first bus;
a second bus;
first means for reading task instructions of the first task list out of the memory across the second bus and for performing first operations indicated by task instructions of the first task list, wherein the first means performs the first operations without fetching any instruction other than task instructions of the first task list; and
second means for reading task instructions of the second task list out of the memory across the second bus and for performing second operations indicated by task instructions of the second task list, wherein the second means performs the second operations without fetching any instruction other than task instructions of the second task list.
26. The apparatus of claim 25, further comprising:
a buffer, wherein the first means writes data into the buffer at locations indicated by a field in a task instruction of the first task list, and wherein the second means reads the data out of the buffer from locations indicated by a field in a task instruction of the second task list.
27. The apparatus of claim 25, wherein the processor is a processor taken from the group consisting of: a multi-core processor, and a multi-threaded processor.
28. A computer program product, comprising:
computer-readable medium comprising:
a first task list for causing a first sub-circuit to perform a first set of operations indicated by task instructions in the first task list, wherein the first sub-circuit reads the task instructions from the computer-readable medium across a second bus;
a second task list for causing a second sub-circuit to perform a second set of operations indicated by task instructions in the second task list, wherein the second sub-circuit reads the task instructions from the computer-readable medium across the second bus; and
code for causing a processor to maintain the first and second task lists in the computer-readable medium across a first bus.
29. The computer program product of claim 28, wherein the first and second task lists include timestamp task instructions that include timer count fields, wherein the first and second task lists also include push task instructions that cause information to be written by sub-circuits into the computer-readable medium, and wherein the first and second task lists include task instructions that include source address fields and destination address fields.
30. The computer program product of claim 28, wherein the computer-readable medium includes an amount of program memory that stores program code executed by the processor and further includes a cache memory coupled to the processor, wherein the first and second task lists are stored in the cache memory.

1. An integrally woven preform with stiffeners in two or more directions constructed from a woven base fabric, said base fabric comprising:
a first woven fabric;
a second woven fabric; and
a plurality of yarns interwoven between said first woven fabric and said second woven fabric, wherein said plurality of yarns are interwoven over a region between said first fabric and said second fabric, and said first fabric is folded relative to said second fabric such that a first off-axis stiffener is formed in said preform.
2. The woven preform of claim 1, wherein said first woven fabric is slit from a top surface of said second woven fabric in one or more regions.
3. The woven preform of claim 2, wherein a first portion on a first side of an interwoven region of said first woven fabric is folded together with a first portion on a second side of the interwoven region of said first woven fabric to form an off-axis stiffener rib in a first direction.
4. The woven preform of claim 1, further comprising:
a third woven fabric; and
a plurality of yarns interwoven between said second woven fabric and said third woven fabric, wherein said plurality of yarns are interwoven over a region between said second fabric and said third fabric, and said third fabric is folded relative to said second fabric such that a second off-axis stiffener is formed in said preform.
5. The woven preform of claim 4, wherein said third woven fabric is slit from a bottom surface of said second woven fabric in one or more regions.
6. The woven preform of claim 5, wherein a first portion on a first side of an interwoven region of said third woven fabric is folded together with a first portion on a second side of the interwoven region of said third woven fabric to form an off-axis stiffener rib in a second direction.
7. The woven preform of claim 1, wherein said base fabric is woven from warp and weft yarns or fibers.
8. The woven preform of claim 7, wherein the warp fiber pattern is a pattern selected from the group consisting of ply-to-ply, orthogonal, and angle interlock.
9. The woven preform of claim 7, wherein the interwoven yarns are warp yarns.
10. The woven preform of claim 7, wherein the interwoven yarns are weft yarns.
11. The woven preform of claim 7, wherein said warp and weft yarns or fibers are selected from the group of consisting of carbon, nylon, rayon, fiberglass, cotton, ceramic, aramid, and polyethylene.
12. The woven preform of claim 4, wherein said first and second off-axis stiffeners are formed at \xb160 degrees or \xb145 degrees orientation.
13. A fiber reinforced composite comprising an integrally woven preform with stiffeners in two or more directions constructed from a woven base fabric, said base fabric comprising:
a first woven fabric;
a second woven fabric; and
a plurality of yarns interwoven between said first woven fabric and said second woven fabric, wherein said plurality of yarns are interwoven over a region between said first fabric and said second fabric, and said first fabric is folded relative to said second fabric such that a first off-axis stiffener is formed in said preform.
14. The composite of claim 13, further comprising a matrix material.
15. The composite of claim 14, wherein said matrix material is a resin, and said composite is formed from a process selected from the group consisting of resin transfer molding and chemical vapor filtration.
16. The composite of claim 14, wherein said matrix material is selected from the group consisting of epoxy, polyester, bismaleimide, vinyl-ester, ceramic, and carbon.
17. The composite of claim 13, wherein said first off-axis stiffener is formed at \xb160 degrees or \xb145 degrees orientation.
18. An integrally woven preform with stiffeners in two or more directions constructed from a woven base fabric, said base fabric comprising:
a first woven fabric;
a second woven fabric; and
a plurality of yarns interwoven between said first woven fabric and said second woven fabric in a plurality of independent regions,
wherein said first fabric is folded relative to said second fabric such that a first stiffener is formed in a first direction in said preform, and a portion of said first stiffener is folded to form a second stiffener in a second direction in said preform, said second stiffener being an off-axis stiffener.
19. The woven preform of claim 18, wherein said first woven fabric is slit from a top surface of said second woven fabric in one or more regions.
20. The woven preform of claim 18, further comprising:
a third woven fabric; and
a plurality of yarns interwoven between said second woven fabric and said third woven fabric in a plurality of independent regions,
wherein said third fabric is folded relative to said second fabric such that a third stiffener is formed in a third direction in said preform, and a portion of said third stiffener is folded to form a fourth stiffener in a fourth direction in said preform, said fourth stiffener being an off-axis stiffener.
21. The woven preform of claim 20, wherein said third woven fabric is slit from a bottom surface of said second woven fabric in one or more regions.
22. The woven preform of claim 18, wherein said base fabric is woven from warp and weft yarns or fibers.
23. The woven preform of claim 22, wherein the warp fiber pattern is a pattern selected from the group consisting of ply-to-ply, orthogonal, and angle interlock.
24. The woven preform of claim 22, wherein the interwoven yarns are warp yarns.
25. The woven preform of claim 22, wherein the interwoven yarns are weft yarns.
26. The woven preform of claim 22, wherein said warp and weft yarns or fibers are selected from the group of consisting of carbon, nylon, rayon, fiberglass, cotton, ceramic, aramid, and polyethylene.
27. The woven preform of claim 20, wherein said second stiffener and fourth stiffener are formed at \xb160 degrees or \xb145 degrees orientation.
28. A fiber reinforced composite comprising an integrally woven preform with stiffeners in two or more directions constructed from a woven base fabric, said base fabric comprising:
a first woven fabric;
a second woven fabric; and
a plurality of yarns interwoven between said first woven fabric and said second woven fabric in a plurality of independent regions,
wherein said first fabric is folded relative to said second fabric such that a first stiffener is formed in a first direction in said preform, and a portion of said first stiffener is folded to form a second stiffener in a second direction in said preform, said second stiffener being an off-axis stiffener.
29. The composite of claim 28, further comprising a matrix material.
30. The composite of claim 29, wherein said matrix material is a resin, and said composite is formed from a process selected from the group consisting of resin transfer molding and chemical vapor filtration.
31. The composite of claim 29, wherein said matrix material is selected from the group consisting of epoxy, polyester, bismaleimide, vinyl-ester, ceramic, and carbon.
32. The composite of claim 28, wherein said second stiffener is formed at \xb160 degrees or \xb145 degrees orientation.
33. A method of forming an integrally woven preform comprising the steps of:
providing two or more woven fabrics;
interweaving a plurality of yarns from a first woven fabric with a plurality of yarns from a second woven fabric, said first woven fabric being foldable in relation to said second woven fabric;
slitting a portion of said first woven fabric from a top surface of said second woven fabric; and
folding said portion of said first fabric relative to said second woven fabric to form a first off-axis stiffener in said preform.
34. The method of claim 33, further comprising the step of:
folding a first portion on a first side of an interwoven region of said first woven fabric together with a first portion on a second side of the interwoven region of said first woven fabric to form an off-axis stiffener rib in a first direction.
35. The method of claim 33, further comprising the step of:
interweaving a plurality of yarns from a third woven fabric with a plurality of yarns from a second woven fabric, said third woven fabric being foldable in relation to said second woven fabric;
slitting a portion of said third woven fabric from a bottom surface of said second woven fabric; and
folding said portion of said third fabric relative to said second woven fabric to form a second off-axis stiffener in said preform.
36. The method of claim 35, further comprising the step of
folding a first portion on a first side of an interwoven region of said third woven fabric together with a first portion on a second side of the interwoven region of said third woven fabric to form an off-axis stiffener rib in a second direction.
37. The method of claim 33, wherein said two or more fabrics are woven from warp and weft yarns or fibers.
38. The method of claim 37, wherein the warp fiber pattern is a pattern selected from the group consisting of ply-to-ply, orthogonal, and angle interlock.
39. The method of claim 37, wherein the interwoven yarns are warp yarns.
40. The method of claim 37, wherein the interwoven yarns are weft yarns.
41. The method of claim 37, wherein said warp and weft yarns or fibers are selected from the group of consisting of carbon, nylon, rayon, fiberglass, cotton, ceramic, aramid, and polyethylene.
42. The method of claim 35, wherein said first and second off-axis stiffeners are formed at \xb160 degrees or \xb145 degrees orientation.
43. A method of forming a fiber reinforced composite comprising the steps of:
forming an integrally woven preform by providing two or more woven fabrics;
interweaving a plurality of yarns from a first woven fabric with a plurality of yarns from a second woven fabric, said first woven fabric being foldable in relation to said second woven fabric;
slitting a portion of said first woven fabric from a top surface of said second woven fabric; and
folding said portion of said first fabric relative to said second woven fabric to form a first off-axis stiffener in said preform.
44. The method of claim 43, further comprising the step of:
impregnating said preform in a matrix material.
45. The method of claim 44, wherein said matrix material is a resin, and said composite is formed from a process selected from the group consisting of resin transfer molding and chemical vapor filtration.
46. The method of claim 44, wherein said matrix material is selected from the group consisting of epoxy, polyester, bismaleimide, vinyl-ester, ceramic, and carbon.
47. The method of claim 43, wherein said first off-axis stiffener is formed at \xb160 degrees or \xb145 degrees orientation.
48. A method of forming an integrally woven preform comprising the steps of:
providing two or more woven fabrics;
interweaving a plurality of yarns from a first woven fabric with a plurality of yarns from a second woven fabric in a plurality of independent regions, said first woven fabric being foldable in relation to said second woven fabric;
slitting a portion of said first woven fabric from a top surface of said second woven fabric; and
folding said portion of said first fabric relative to said second woven fabric such that a first stiffener is formed in a first direction in said preform, and a portion of said first stiffener is folded to form a second stiffener in a second direction in said preform, said second stiffener being an off-axis stiffener.
49. The method of claim 48, further comprising:
interweaving a plurality of yarns from a third woven fabric with a plurality of yarns from a second woven fabric in a plurality of independent regions, said third woven fabric being foldable in relation to said second woven fabric;
slitting a portion of said third woven fabric from a top surface of said second woven fabric; and
folding said portion of said third fabric relative to said second woven fabric such that a third stiffener is formed in a third direction in said preform, and a portion of said third stiffener is folded to form a fourth stiffener in a fourth direction in said preform, said fourth stiffener being an off-axis stiffener.
50. The method of claim 48, wherein said two or more fabrics are woven from warp and weft yarns or fibers.
51. The method of claim 50, wherein the warp fiber pattern is a pattern selected from the group consisting of ply-to-ply, orthogonal, and angle interlock.
52. The method of claim 50, wherein the interwoven yarns are warp yarns.
53. The method of claim 50, wherein the interwoven yarns are weft yarns.
54. The method of claim 50, wherein said warp and weft yarns or fibers are selected from the group of consisting of carbon, nylon, rayon, fiberglass, cotton, ceramic, aramid, and polyethylene.
55. The method of claim 49, wherein said second stiffener and fourth stiffener are formed at \xb160 degrees or \xb145 degrees orientation.
56. A method of forming a fiber reinforced composite comprising the steps of:
forming an integrally woven preform by providing two or more woven fabrics;
interweaving a plurality of yarns from a first woven fabric with a plurality of yarns from a second woven fabric in a plurality of independent regions, said first woven fabric being foldable in relation to said second woven fabric;
slitting a portion of said first woven fabric from a top surface of said second woven fabric; and
folding said portion of said first fabric relative to said second woven fabric such that a first stiffener is formed in a first direction in said preform, and a portion of said first stiffener is folded to form a second stiffener in a second direction in said preform, said second stiffener being an off-axis stiffener.
57. The method of claim 56, further comprising the step of:
impregnating said preform in a matrix material.
58. The method of claim 57, wherein said matrix material is a resin, and said composite is formed from a process selected from the group consisting of resin transfer molding and chemical vapor filtration.
59. The method of claim 57, wherein said matrix material is selected from the group consisting of epoxy, polyester, bismaleimide, vinyl-ester, ceramic, and carbon.
60. The method of claim 56, wherein said first off-axis stiffener is formed at +\u221260 degrees or \xb145 degrees orientation.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A scan type exposure apparatus for exposing a substrate, placed on an exposure plane, to a pattern of a mask with light from a light source, said apparatus comprising:
a stop member for restricting an exposure range on the exposure plane;
measuring means for measuring an illuminance distribution which is produced on a predetermined plane displaced from the exposure plane in an optical axis direction and by a predetermined amount and which is provided by light passed through an opening of said stop member and projected or to be projected at a predetermined position on the exposure plane; and
calculating means for calculating an angular characteristic of light projected or to be projected on the exposure plane, on the basis of integrating illuminance distributions which are defined by lights incident at plural positions along a scan direction upon the exposure plane and which are measured by said measuring means.
2. An apparatus according to claim 1, wherein said measuring means is adapted to measure the illuminance distributions, defined by the lights incident on the plural positions, independently of each other.
3. An apparatus according to claim 1, wherein the opening of said stop member has a variable shape, and wherein, for the measurement with said measuring means, the shape of the opening is made into a hole-like shape.
4. An apparatus according to claim 1, wherein the opening of said stop member has a slit-like shape being elongated in the scan direction.
5. An apparatus according to claim 1, wherein the opening of said stop member has a variable shape, and wherein, for the measurement with said measuring means, the shape of the opening is made into a slit-like shape being elongated in the scan direction.
6. An apparatus according to claim 1, wherein said measuring means includes a detector for detecting intensity of light, and wherein said detector is movable in a direction perpendicular to an optical axis to measure the illuminance distribution.
7. An apparatus according to claim 1, wherein said measuring means includes a sensor array which is movable in a direction perpendicular to an optical axis to measure the illuminance distribution.
8. An apparatus according to claim 1, wherein said measuring means includes a two-dimensional sensor array.
9. A scan type exposure apparatus for exposing a substrate, placed on an exposure plane, to a pattern of a mask with light from a light source, said apparatus comprising:
a stop member having a slit-like opening elongated in a scan direction, for restricting an exposure range on the exposure plane;
a two-dimensional sensor array disposed at a position corresponding to a Fourier transform plane with respect to the exposure plane; and
a detector for detecting an intensity distribution, on the Fourier transform plane, of light passed through the slit-like opening of said stop member.
10. A device manufacturing method, comprising the steps of: exposing a substrate by use of an exposure apparatus as recited in claim 1; and developing the exposed substrate.
11. A device manufacturing method, comprising the steps of: exposing a substrate by use of an exposure apparatus as recited in claim 9; and developing the exposed substrate.
12. An apparatus according to claim 9, wherein the opening of said stop member has a variable shape, and wherein, for the detection with said detector, the shape of the opening is made into the slit-like shape.