Author: claimsbot

1. A PLI n-bit correction circuit which compares a core header, included in a GFP frame with a fixed payload length, with a predetermined expectation value for each bit so as to calculates the number of inconsistent bits therebetween and which outputs the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number).
2. The PLI n-bit correction circuit according to claim 1, wherein the core header is directly output when the number of inconsistent bits is greater than n.
3. The PLI n-bit correction circuit according to claim 1, wherein a PLI included in the core header is compared with a PLI expectation value, thus calculating the number of inconsistent bits therebetween.
4. The PLI n-bit correction circuit according to claim 1, wherein the core header and the predetermined expectation value are subjected to exclusive-OR operation for each bit and then added together, thus calculating the number of inconsistent bits therebetween.
5. The PLI n-bit correction circuit according to claim 1, wherein a first expectation value and a second expectation value are used as the predetermined expectation value, wherein a first number of inconsistent bits is calculated based on the first expectation value whilst a second number of inconsistent bits is calculated based on the second expectation value, and wherein the minimum number of inconsistent bits, which is either the first or second number of inconsistent bits, is defined as m, which satisfies a condition of n<m2.
6. A GFP Layer 2 synchronization circuit comprising:
a core header drop circuit which extracts a core header from a GFP frame with a fixed payload length;
a PLI n-bit correction circuit which compares the core header with a predetermined expectation value per each bit so as to calculate the number of inconsistent bits therebetween, which outputs the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number), or which directly outputs the core header when the number of inconsistent bits is greater than n;
a Layer 2 synchronization monitor circuit which generates a Layer 2 synchronization signal indicating establishment of Layer 2 synchronization when the PLI n-bit correction circuit consecutively outputs errorless core headers two times or an event of Layer 2 desynchronization when the number of inconsistent bits exceeds n so that the PLI n-bit correction circuit directly outputs the core header without error correction; and
a selector which supplies the Layer 2 synchronization monitor circuit with the output of the PLI n-bit correction circuit when the Layer 2 synchronization signal indicates establishment of Layer 2 synchronization or which supplies the Layer 2 synchronization monitor circuit with the core header output from the core header drop circuit when the Layer 2 synchronization signal indicates the event of Layer 2 desynchronization.
7. A GFP frame transfer device comprising:
a receiver which receives a GFP frame with a fixed payload length;
a core header drop circuit which extracts a core header from the GFP frame;
a PLI n-bit correction circuit which compares the core header with a predetermined expectation value per each bit so as to calculate the number of inconsistent bits therebetween, which outputs the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number), or which directly outputs the core header when the number of inconsistent bits is greater than n;
a Layer 2 synchronization monitor circuit which generates a Layer 2 synchronization signal indicating establishment of Layer 2 synchronization when the PLI n-bit correction circuit consecutively outputs errorless core headers two times or an event of Layer 2 desynchronization when the PLI n-bit correction circuit directly outputs the core header without error correction;
a selector which supplies the Layer 2 synchronization monitor circuit with the output of the PLI n-bit correction circuit when the Layer 2 synchronization signal indicates establishment of Layer 2 synchronization or which supplies the Layer 2 synchronization monitor circuit with the core header output from the core header drop circuit when the Layer 2 synchronization signal indicates the event of Layer 2 desynchronization; and
a GFP frame processing circuit which executes predetermined processing on a payload of the GFP frame dropping the core header when the Layer 2 synchronization signal indicates establishment of Layer 2 synchronization or which discards the GPF frame without performing the predetermined processing on the payload when the Layer 2 synchronization signal indicates the event of Layer 2 desynchronization.
8. A PLI n-bit correction method comprising:
comparing a core header, included in a GFP frame with a fixed payload length, with a predetermined expectation value per each bit;
calculating the number of inconsistent bits therebetween; and
outputting the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number).
9. The PLI n-bit correction method according to claim 8, wherein the core header is directly output when the number of inconsistent bits is greater than n.
10. The PLI n-bit correction method according to claim 8, wherein a PLI included in the core header is compared with a PLI expectation value, thus calculating the number of inconsistent bits therebetween.
11. The PLI n-bit correction method according to claim 8, wherein the core header and the predetermined expectation value are subjected to exclusive-OR operation per each bit and then added together, thus calculating the number of inconsistent bits therebetween.
12. The PLI n-bit correction method according to claim 8, wherein a first expectation value and a second expectation value are used as the predetermined expectation value, wherein a first number of inconsistent bits is calculated based on the first expectation value whilst a second number of inconsistent bits is calculated based on the second expectation value, and wherein the minimum number of inconsistent bits, which is either the first or second number of inconsistent bits, is defined as m, which satisfies a condition of n<m2.
13. A GFP frame transfer method comprising:
extracting a core header from a GFP frame with a fixed payload length;
comparing the core header with a predetermined expectation value for each bit;
calculating the number of inconsistent bits therebetween;
outputting the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number) or directly outputting the core header when the number of inconsistent bits is greater than n;
generating a Layer 2 synchronization signal indicating establishment of Layer 2 synchronization when errorless core headers are consecutively output two times or an event of Layer 2 desynchronization when the number of inconsistent bits exceeds n so that the core header is directly output without error correction; and
performing predetermined processing on a payload of the GFP frame dropping the core header when the Layer 2 synchronization signal indicates establishment of Layer 2 synchronization or discarding the GPF frame without performing predetermined processing on the payload when the Layer 2 synchronization signal indicates the event of Layer 2 desynchronization.
14. The PLI n-bit correction circuit according to claim 2, wherein a PLI included in the core header is compared with a PLI expectation value, thus calculating the number of inconsistent bits therebetween.
15. The PLI n-bit correction circuit according to claim 2, wherein the core header and the predetermined expectation value are subjected to exclusive-OR operation for each bit and then added together, thus calculating the number of inconsistent bits therebetween.
16. The PLI n-bit correction circuit according to claim 2, wherein a first expectation value and a second expectation value are used as the predetermined expectation value, wherein a first number of inconsistent bits is calculated based on the first expectation value whilst a second number of inconsistent bits is calculated based on the second expectation value, and wherein the minimum number of inconsistent bits, which is either the first or second number of inconsistent bits, is defined as m, which satisfies a condition of n<m2.
17. The PLI n-bit correction method according to claim 9, wherein a PLI included in the core header is compared with a PLI expectation value, thus calculating the number of inconsistent bits therebetween.
18. The PLI n-bit correction method according to claim 9, wherein the core header and the predetermined expectation value are subjected to exclusive-OR operation per each bit and then added together, thus calculating the number of inconsistent bits therebetween.
19. The PLI n-bit correction method according to claim 9, wherein a first expectation value and a second expectation value are used as the predetermined expectation value, wherein a first number of inconsistent bits is calculated based on the first expectation value whilst a second number of inconsistent bits is calculated based on the second expectation value, and wherein the minimum number of inconsistent bits, which is either the first or second number of inconsistent bits, is defined as m, which satisfies a condition of n<m2.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of entering an Initialization State in a wireless communication system, characterized in that:
selecting a serving access network;
obtaining synchronization from access network; and
determining if a Redirect Message with a Channel Record is received.
2. The method as claimed in claim 1, characterized in that issuing an InitializationState.Activate command upon entering Initialization State.
3. The method as claimed in claim 1, characterized in that issuing the Channel Record with InitializationState.Activate command if the Redirect Message with Channel Record is received.
4. A computer-readable medium including instructions stored thereon, characterized in that:
a set of instructions for selecting a serving access network;
a set of instructions for obtaining synchronization from access network;
a set of instructions for determining if a Redirect Message with Channel Record is received.
5. An apparatus operable in a wireless communication system, the apparatus characterized in that:
means for selecting a serving access network;
means for obtaining synchronization from an access network;
means for determining if a Redirect Message with a Channel Record is received.
6. The apparatus as claimed in claim 5, characterized in that means for issuing an InitializationState.Activate command upon entering an Initialization State.
7. The apparatus as claimed in claim 5, characterized in that means for issuing the Channel Record with InitializationState.Activate command if the Redirect Message with Channel Record is received.
8. A method of transition to an Idle State, characterized in that:
determining if protocol received an InitializationState.NetworkAcquired indication;
issuing an Initialization State.Deactivate command if the initializationState.NetworkAcquired indication has been received; and
transitioning to the Idle state.
9. A computer-readable medium including instructions stored thereon, characterized in that:
a set of instructions to determine if protocol received an InitializationState.NetworkAcquired indication;
a set of instructions for issuance of an Initialization State.Deactivate command if the InitializationState.NetworkAcquired indication has been received; and
a set of instructions for transitioning to an Idle state.
10. An apparatus operable in a wireless communication system, the apparatus characterized in that:
means to determine if protocol received an InitializationState.NetworkAcquired indication;
means to issue an Initialization State.Deactivate command if InitializationState.NetworkAcquired indication has been received; and
means for transition to Idle state.

1. A method of fabricating an array substrate for a display device, the method comprising:
forming a gate line, and a gate electrode connected to the gate line, on a substrate;
forming a gate insulating layer on the gate line and the gate electrode;
forming an active layer, an ohmic contact layer, and source and drain electrodes on the gate insulating layer using a photo mask including a transmissive portion, a semi-transmissive portion and a blocking portion;
forming a passivation layer on the source and drain electrodes; and
forming a pixel electrode connected to the drain electrode on the passivation layer,
wherein the source and drain electrodes are separated from each other to define a separate region, wherein the separate region is defined between opposing sides of the source and drain electrodes,
wherein the separate region includes first to third regions in different directions, and
wherein the active layer is removed in at least one of the first to third regions to expose the gate insulating layer.
2. The method according to claim 1, wherein the active layer remained in other regions of the first to third regions is exposed through the other regions of the first to third regions and functions as a channel of the thin film transistor.
3. The method according to claim 2, wherein the active layer removed in at least one of the first to third regions corresponds to the transmissive portion and the active layer remained in the other regions of the first to third regions corresponds to the semi-transmissive portion during the photo mask process.
4. The method according to claim 1, wherein the channel of the thin film transistor is formed in one direction.
5. The method according to claim 1, wherein the separate region has a U shape, the first region corresponds to straight portions of the U-shaped separation region, the third region corresponds to bottom portion of the U-shaped separation region, and the second region corresponds to corner portions between the straight portions and the bottom portion of the U-shaped separation region.
6. The method according to claim 5, wherein the active layer is removed in the third region of the separation region.
7. The method according to claim 5, wherein the active layer is removed in the second and third regions of the separation region.
8. The method according to claim 5, wherein the first region of the separate region parallels with the gates lines, the second region of the separation region is tilted at an angle of 45 degrees or \u221245 degrees with respect to the gate lines, and the third region is perpendicular to the gate line.
9. The method according to claim 5, wherein the first region of the separate region is tilted at an angle of 45 degrees with respect to the gate lines, the second region of the separation region is in parallel with or perpendicular to the gate lines, and the third region is tilted at an angle of 135 degrees with respect to the gate lines.
10. The method according to claim 5, wherein the first region of the separate region is perpendicular to the gate lines, the second region of the separation region is tilted at an angle of 45 degrees or 135 degrees with respect to the gate lines, and the third region parallels with the gates lines.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A shift register, comprising a plurality of blocks of unit circuits for transferring data in one direction based on a clock signal having pulses, each unit circuit including:
capacitor means for storing the data outputted from a unit circuit upstream in a data transfer direction;
a first transistor including an input-side diffusion layer and an output-side diffusion layer, wherein the first transistor receives a clock signal via the input-side diffusion layer, and the first transistor is turned ON only when the data is being stored in the capacitor means so as to output a pulse of the clock signal via the output-side diffusion layer;
a second transistor including a control electrode, an input-side diffusion layer and an output-side diffusion layer, wherein the control electrode and the input-side diffusion layer are connected to the output-side diffusion layer of the first transistor, and the second transistor is turned ON only when the pulse of the clock signal from the first transistor is inputted to the control electrode and the input-side diffusion layer so as to output the data via the output-side diffusion layer to a unit circuit downstream in the data transfer direction; and
potential controlling means for controlling a potential at the control electrode of the second transistor to be such a potential that the second transistor is kept OFF at least during a period in which the second transistor is supposed to be OFF, wherein:
the potential controlling means includes a fifth transistor including a control electrode, an input-side diffusion layer, and an output-side diffusion layer, the input-side diffusion layer is connected to a portion between the output-side diffusion layer of the first transistor and the control electrode of the second transistor, a predetermined voltage is applied to the output-side diffusion layer, and a control signal for turning ONOFF the fifth transistor is applied to the control electrode of the fifth transistor,
the fifth transistor is controlled by the control signal so that the fifth transistor is ON during a period in which the first transistor and the second transistor are OFF after the data is outputted to a unit circuit downstream in the data transfer direction,
the potential controlling means includes control signal producing means for producing the control signal by using a pulse of the clock signal outputted from the output-side diffusion layer of the first transistor included in the unit circuit downstream in the data transfer direction,
the control signal producing means is a sixth transistor including a control electrode, an input-side diffusion layer, and an output-side diffusion layer, wherein the input-side diffusion layer and the control electrode are connected to the output-side diffusion layer of the first transistor included in the unit circuit downstream in the data transfer direction, and the output-side diffusion layer is connected to the control electrode of the fifth transistor,
the sixth transistor is turned ON when a pulse of the clock signal outputted from the first transistor included in the unit circuit downstream in the data transfer direction is applied to the control electrode and the input-side diffusion layer of the sixth transistor, and
the fifth transistor is turned ON when the sixth transistor is turned ON.
2. The shift register according to claim 1, wherein each unit circuit further includes erasing means for erasing the data stored in the capacitor means after the data is outputted from the unit circuit.
3. The shift register according to claim 2, wherein:
the erasing means is a third transistor including a control electrode, an input-side diffusion layer and an output-side diffusion layer, wherein a predetermined voltage is applied to the output-side diffusion layer, the input-side diffusion layer is connected to the control electrode of the first transistor, and the control electrode is connected to a portion of a unit circuit downstream in the data transfer direction between the output-side diffusion layer of the first transistor and the control electrode of the second transistor; and
the third transistor is turned ON when a pulse of the clock signal is outputted from the output-side diffusion layer of the first transistor included in the unit circuit downstream in the data transfer direction so as to erase the data stored in the capacitor means.
4. The shift register according to claim 1, wherein the control signal producing means further includes turn-OFF means for changing the potential at the control electrode of the fifth transistor so as to turn OFF the fifth transistor when the data is outputted from a unit circuit upstream in the data transfer direction.
5. The shift register according to claim 4, wherein:
the turn-OFF means is a seventh transistor including a control electrode, an input-side diffusion layer and an output-side diffusion layer, wherein the input-side diffusion layer is connected to the output-side diffusion layer of the sixth transistor, the control electrode is connected to the output-side diffusion layer of the first transistor included in the unit circuit upstream in the data transfer direction, and a predetermined voltage is applied to the output-side diffusion layer;
the seventh transistor is turned ON only when a pulse of the clock signal outputted from the first transistor of the unit circuit upstream in the data transfer direction is applied to the control electrode of the seventh transistor; and
the fifth transistor is turned OFF when the seventh transistor is turned ON.
6. The shift register according to claim 1, wherein the potential controlling means of the unit circuit of a last block among the plurality of blocks of unit circuits further includes control signal producing means for producing the control signal by using the data inputted to a unit circuit upstream in the data transfer direction.
7. A MOS-type solid-state image sensor, comprising:
a plurality of light-receiving elements arranged in a matrix pattern each for converting incident light into a signal charge, which is data;
a plurality of signal lines provided between columns of the light-receiving elements arranged in a matrix pattern for reading out the data;
a plurality of column selection transistors each corresponding to one of the plurality of signal lines and each having an input-side diffusion layer connected to the corresponding signal line; and
a shift register according to claim 1 including a plurality of blocks of unit circuits for transferring the data in one direction based on a clock signal having pulses, wherein each unit circuit includes:
capacitor means for storing the data outputted from a unit circuit upstream in a data transfer direction;
a first transistor including an input-side diffusion layer and an output-side diffusion layer, wherein the first transistor receives a clock signal via the input-side diffusion layer, and the first transistor is turned ON only when the data is being stored in the capacitor means so as to output a pulse of the clock signal via the output-side diffusion layer;
a second transistor including a control electrode, an input-side diffusion layer and an output-side diffusion layer, wherein the control electrode and the input-side diffusion layer are connected to the output-side diffusion layer of the first transistor, and the second transistor is turned ON only when the pulse of the clock signal from the first transistor is inputted to the control electrode and the input-side diffusion layer so as to output the data via the output-side diffusion layer to a unit circuit downstream in the data transfer direction; and
potential controlling means for controlling a potential at the output-side diffusion layer of the first transistor to be such a potential that the column selection transistor is kept OFF at least during a period in which the second transistor is supposed to be OFF, wherein:
each column selection transistor includes a control electrode connected to the output-side diffusion layer of the first transistor, and is turned ON when a pulse is outputted from the output-side diffusion layer of the first transistor; and
the shift register, while transferring the data in one direction, applies a pulse from the first transistor of each unit circuit to the control electrode of the corresponding column selection transistor, whereby the column selection transistors are turned ON successively so as to output the data to an outside via the plurality of signal lines.
8. A MOS-type solid-state image sensor, comprising:
a plurality of light-receiving elements arranged in a matrix pattern each for converting incident light into a signal charge, which is data;
a plurality of signal lines provided between rows of the light-receiving elements arranged in a matrix pattern each for selecting a row;
a plurality of row selection transistors each corresponding to one of the plurality of signal lines and each having an input-side diffusion layer connected to the corresponding signal line; and
a shift register according to claim 1 including a plurality of blocks of unit circuits for transferring the data in one direction based on a clock signal having pulses, wherein each unit circuit includes:
capacitor means for storing the data outputted from a unit circuit upstream in a data transfer direction;
a first transistor including an input-side diffusion layer and an output-side diffusion layer, wherein the first transistor receives a clock signal via the input-side diffusion layer, and the first transistor is turned ON only when the data is being stored in the capacitor means so as to output a pulse of the clock signal via the output-side diffusion layer;
a second transistor including a control electrode, an input-side diffusion layer and an output-side diffusion layer, wherein the control electrode and the input-side diffusion layer are connected to the output-side diffusion layer of the first transistor, and the second transistor is turned ON only when the pulse of the clock signal from the first transistor is inputted to the control electrode and the input-side diffusion layer so as to output the data via the output-side diffusion layer to a unit circuit downstream in the data transfer direction; and
potential controlling means for controlling a potential at the output-side diffusion layer of the first transistor to be such a potential that the row selection transistor is kept OFF at least during a period in which the second transistor is supposed to be OFF, wherein:
each row selection transistor includes a control electrode connected to the output-side diffusion layer of the first transistor, and is turned ON when a pulse is outputted from the output-side diffusion layer of the first transistor; and
the shift register, while transferring the data in one direction, applies a pulse from the first transistor of each unit circuit to the control electrode of the corresponding row selection transistor, whereby the row selection transistors are turned ON successively so as to successively select the plurality of signal lines.
9. A camera, comprising:
a plurality of light-receiving elements arranged in a matrix pattern each for converting incident light into a signal charge, which is data;
a plurality of signal lines provided between columns of the light-receiving elements arranged in a matrix pattern for reading out the data;
a plurality of column selection transistors each corresponding to one of the plurality of signal lines and each having an input-side diffusion layer connected to the corresponding signal line;
a shift register according to claim 1 including a plurality of blocks of unit circuits for transferring the data in one direction based on a clock signal having pulses; and
an external circuit for performing a predetermined operation on the data transferred by the shift register, wherein each unit circuit includes:
capacitor means for storing the data outputted from a unit circuit upstream in a data transfer direction;
a first transistor including an input-side diffusion layer and an output-side diffusion layer, wherein the first transistor receives a clock signal via the input-side diffusion layer, and the first transistor is turned ON only when the data is being stored in the capacitor means so as to output a pulse of the clock signal via the output-side diffusion layer;
a second transistor including a control electrode, an input-side diffusion layer and an output-side diffusion layer, wherein the control electrode and the input-side diffusion layer are connected to the output-side diffusion layer of the first transistor, and the second transistor is turned ON only when the pulse of the clock signal from the first transistor is inputted to the control electrode and the input-side diffusion layer so as to output the data via the output-side diffusion layer to a unit circuit downstream in the data transfer direction; and
potential controlling means for controlling a potential at the output-side diffusion layer of the first transistor to be such a potential that the column selection transistor is kept OFF at least during a period in which the second transistor is supposed to be OFF, wherein:
each column selection transistor includes a control electrode connected to the output-side diffusion layer of the first transistor, and is turned ON when a pulse is outputted from the output-side diffusion layer of the first transistor; and
the shift register, while transferring the data in one direction, applies a pulse from the first transistor of each unit circuit to the control electrode of the corresponding column selection transistor, whereby the column selection transistors are turned ON successively so as to output the data to the external circuit via the plurality of signal lines.
10. A camera, comprising:
a plurality of light-receiving elements arranged in a matrix pattern each for converting incident light into a signal charge, which is data;
a plurality of signal lines provided between rows of the light-receiving elements arranged in a matrix pattern each for selecting a row;
a plurality of row selection transistors each corresponding to one of the plurality of signal lines and each having an input-side diffusion layer connected to the corresponding signal line;
a shift register according to claim 1 including a plurality of blocks of unit circuits for transferring the data in one direction based on a clock signal having pulses; and
an external circuit for performing a predetermined operation on the data transferred by the shift register, wherein each unit circuit includes:
capacitor means for storing the data outputted from a unit circuit upstream in a data transfer direction;
a first transistor including an input-side diffusion layer and an output-side diffusion layer, wherein the first transistor receives a clock signal via the input-side diffusion layer, and the first transistor is turned ON only when the data is being stored in the capacitor means so as to output a pulse of the clock signal via the output-side diffusion layer;
a second transistor including a control electrode, an input-side diffusion layer and an output-side diffusion layer, wherein the control electrode and the input-side diffusion layer are connected to the output-side diffusion layer of the first transistor, and the second transistor is turned ON only when the pulse of the clock signal from the first transistor is inputted to the control electrode and the input-side diffusion layer so as to output the data via the output-side diffusion layer to a unit circuit downstream in the data transfer direction; and
potential controlling means for controlling a potential at the output-side diffusion layer of the first transistor to be such a potential that the row selection transistor is kept OFF at least during a period in which the second transistor is supposed to be OFF, wherein:
each row selection transistor includes a control electrode connected to the output-side diffusion layer of the first transistor, and is turned ON when a pulse is outputted from the output-side diffusion layer of the first transistor; and
the shift register, while transferring the data in one direction, applies a pulse from the first transistor of each unit circuit to the control electrode of the corresponding row selection transistor, whereby the row selection transistors are turned ON successively so as to successively select the plurality of signal lines.