Author: claimsbot

1. A wellbore treatment fluid comprising at least one polysaccharide and an effective amount of at least one polyacrylamide to maintain stability of the fluid at a temperature greater than about 250\xb0 F.
2. The wellbore treatment fluid of claim 1, wherein the temperature at which the stability is maintained is in a range of from about 275\xb0 F. to about 325\xb0 F.
3. The wellbore treatment fluid of claim 1, being substantially free of formates.
4. The wellbore treatment fluid of claim 1, wherein the polysaccharide comprises xanthan gum, welan gum, a cellulose derivative, Succinoglycan polysaccharide, Scleroglucan polysaccharide, xanthan polysaccharide, or combinations thereof.
5. The wellbore treatment fluid of claim 1, wherein the polyacrylamide has a molecular weight of from about 20,000 to about 40,000.
6. The wellbore treatment fluid of claim 1, wherein the effective amount of the at least one polyacrylamide is in a range of from about 0.5 to about 10.0 poundbarrel of the fluid.
7. The wellbore treatment fluid of claim 1, wherein an amount of the at least one polysaccharide present in the fluid is in a range of from about 0.2 to about 1.5 poundbarrel of the fluid.
8. The wellbore treatment fluid of claim 1, exhibiting a reduction in yield point of less than or equal to about 15% when it is sequentially hot rolled at a first temperature of about 300\xb0 F. and at a second temperature of about 325\xb0 F.
9. The wellbore treatment fluid of claim 1, exhibiting a yield point of greater than about 10 lb100 ft.2 when exposed to a temperature in a range of from about 300\xb0 F. to about 325\xb0 F.
10. The wellbore treatment fluid of claim 1, comprising water, an ionic salt, a basic material, a weighting agent, a surfactant, calcium carbonate, or combinations thereof.
11. The wellbore treatment fluid of claim 1, comprising a drilling fluid, a completion fluid, a workover fluid, or combinations thereof.
12. The wellbore treatment fluid of claim 1, being disposed in a subterranean wellbore.
13. A drilling fluid comprising:
greater than or equal to about 14 pounds per barrel of an ionic salt;
greater than or equal to about 0.2 pounds per barrel of a polysaccharide; and
a sufficient amount of at least one polyacrylamide to maintain stability of the drilling fluid at a temperature greater than about 250\xb0 F.
14. The drilling fluid of claim 13, further comprising water.
15. The drilling fluid of claim 13, further comprising a weighting agent.
16. The drilling fluid of claim 13, further comprising a sufficient amount of a basic material to adjust its pH to in a range of from about 8 to about 10.
17. The drilling fluid of claim 13, exhibiting a reduction in yield point of less than or equal to about 15% when it is sequentially hot rolled at a first temperature of about 300\xb0 F. and at a second temperature of about 325\xb0 F.
18. The drilling fluid of claim 13, being substantially free of formates.
19. A pre-mixed wellbore treatment fluid, comprising:
water;
at least one polysaccharide; and
an effective amount of at least one polyacrylamide to maintain stability of the fluid at a temperature greater than about 250\xb0 F., wherein the pre-mixed wellbore treatment fluid resides on a truck.
20. The pre-mixed wellbore treatment fluid of claim 19, wherein the temperature at which the stability is maintained is in a range of from about 275\xb0 F. to about 325\xb0 F.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for isomerizing a compound comprising:
contacting a composition comprising 1,1,3,3-tetrafluoropropene with at least one isomerization catalyst selected from the group consisting of metal halides, halogenated metal oxides, and zero-valent metals or metal alloys, wherein said contacting occurs at a reaction temperature from about 50\xb0 C. to about 400\xb0 C. to isomerize at least a portion of said 1,1,3,3-tetrafluoropropene into 1,3,3,3-tetrafluoropropene.
2. The method of claim 1 wherein said 1,3,3,3-tetrafluoropropene is trans-1,3,3,3-tetrafluoropropene.
3. The method of claim 1 wherein said 1,3,3,3-tetrafluoropropene is cis-1,3,3,3-tetrafluoropropene.
4. The method of claim 1 wherein said 1,3,3,3-tetrafluoropropene is a mixture of cis-1,3,3,3-tetrafluoropropene and trans-1,3,3,3-tetrafluoropropene.
5. The method of claim 1 wherein said composition further comprises cis-1,3,3,3-tetrafluoropropene andor 1,1,1,3,3-pentafluoropropane prior to said contacting.
6. The method of claim 1 wherein said isomerization is at least about 95% selective for 1,3,3,3-tetrafluoropropene.
7. The method of claim 1 wherein said isomerization converts at least about 95% of said 1,1,3,3-tetrafluoropropene.
8. The method of claim 1 wherein said contacting step occurs at a pressure of about 2 to about 6 atm.
9. The method of claim 1 wherein said contacting step occurs with a residence time of about 10 to about 60 seconds.
10. A method for producing a fluorinated compound comprising:
reacting a composition comprising 1,1,3,3-tetrafluoropropene in the presence of hydrogen fluoride and at least one catalyst selected from the group consisting of metal halides and halogenated metal oxides wherein said reacting occurs at a reaction temperature from about 100\xb0 C. to about 500\xb0 C. to convert at least a portion of said 1,1,3,3-tetrafluoropropene into a reaction product comprising at least one of 1,3,3,3-tetrafluoropropene and 1,1,1,3,3-pentafluoropropane.
11. The method of claim 10 wherein said reaction product comprises 1,3,3,3-tetrafluoropropene.
12. The method of claim 10 wherein said reaction product comprises 1,1,1,3,3-pentafluoropropane.
13. The method of claim 10 wherein said reacting comprises forming a reaction mixture comprising 1,1,3,3-tetrafluoropropene and hydrogen fluoride in a 1,1,3,3-tetrafluoropropene:hydrogen fluoride ratio of about 1:10 to about 1:1500.
14. The method of claim 10 wherein said reacting occurs in a vapor phase.
15. The method of claim 1 wherein said contacting step occurs at a pressure of about 1 to about 20 atm.
16. The method of claim 1 wherein said contacting step occurs with a residence time of about 0.5 to about 600 seconds.
17. The method of claim 10 wherein said reacting comprises forming a reaction mixture comprising 1,1,3,3-tetrafluoropropene and hydrogen fluoride in a 1,1,3,3-tetrafluoropropene:hydrogen fluoride ratio of about 1:0.1 to about 1:10000.
18. The method of claim 10 wherein said reacting comprises forming a reaction mixture comprising 1,1,3,3-tetrafluoropropene and hydrogen fluoride in a 1,1,3,3-tetrafluoropropene:hydrogen fluoride ratio of about 1:1 to about 1:2000.
19. The method of claim 10 wherein said contacting step occurs at a pressure of about 1 to about 20 atm.
20. The method of claim 10 wherein said contacting step occurs with a residence time of about 0.5 to about 600 seconds.

1. A photoelectric device comprising a glass substrate; an undercoating film adjacent to the glass substrate; a doped zinc oxide transparent conductive oxide layer adjacent to the undercoating film; and a nitrogen-containing cap layer adjacent to the doped zinc oxide transparent conductive layer, said cap layer comprising nitrogen and at least one element selected from Group IIIA of the Periodic Table, and optionally comprising zinc andor oxygen.
2. The photoelectric device of claim 1 wherein said cap layer comprises zinc andor oxygen.
3. The photoelectric device of claim 1 wherein said cap layer comprises zinc, oxygen, and gallium.
4. The photoelectric device of claim 1 wherein said nitrogen-containing cap layer comprises a mixture of ZnwOxNyYz, where w, x, y, z are atomic percents of zinc, oxygen, nitrogen, and Y in the compound, where w is from 0 to 100, x is from 0 to 100, y is from 0 to 100, z is from 0 to 100, such that the sum of all concentrations (w+x+y+z+\u03c7) is equal to one, where \u03c7 represents a total sum of impurities in atomic percent and wherein Y represents one or more elements selected from the group consisting of B, Al, Ga, In, and Tl.
5. The nitrogen-containing cap layer of claim 4 wherein Y is Ga.
6. The nitrogen-containing cap layer of claim 4 where \u03c7 is 10 atomic percent or less.
7. A nitrogen-containing TCO cap composition comprising ZnwOxNyYz, where w, x, y, z are atomic percents of zinc, oxygen, nitrogen, and Y in the composition, where w is from 0 to 100, x is from 0 to 100, y is from 0 to 100, z is from 0 to 100, such that the sum of all concentrations (w+x+y+z+\u03c7) is equal to one, where \u03c7 represents a total sum of impurities in atomic percent and wherein Y represents one or more elements selected from the group consisting of B, Al, Ga, In, Tl, Sn, W, Ta, Nb, F, Cl, Br, I, and At.
8. The nitrogen-containing TCO cap composition of claim 7 wherein Y represents one or more elements selected from the group consisting of B, Al, Ga, In, Tl.
9. The nitrogen-containing TCO cap composition of claim 7 wherein Y is Ga.
10. The nitrogen-containing TCO cap composition of claim 7 where \u03c7 is 10 atomic percent or less.
11. The nitrogen-containing TCO cap composition of claim 7 where w is from 0 to 80, x is from 0 to 50, y is from 10 to 50, z is from 10 to 50.
12. The nitrogen-containing TCO cap composition of claim 7 which is a film or layer.
13. An organic light emitting diode comprising an electrode, wherein said electrode comprises the nitrogen-containing TCO cap composition of claim 7.
14. A touch screen comprising an electrode, wherein said electrode comprises the nitrogen-containing TCO cap composition of claim 7.
15. A display device comprising an electrode, wherein said electrode comprises the nitrogen-containing TCO cap composition of claim 7.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An electronic circuit comprising:
a current source for providing a current responsive to at least one low power signal;
a first stage for receiving said current and directing said current, responsive to at least one enable signal, to one of a first voltage potential and a second stage; and
said second stage for receiving said current and directing said current to one of a plurality of output nodes, in response to at least one control signal.
2. An electronic circuit in accordance with claim 1, wherein said current source is a current mirror.
3. An electronic circuit in accordance with claim 1, wherein said electronic circuit is an integrated circuit.
4. An electronic circuit in accordance with claim 1, wherein said current source comprises:
a first transistor having a gate and two current carrying electrodes, wherein one of the current carrying electrodes of the first transistor is electrically coupled to the gate of the first transistor and to a source of current, and the other current carrying electrode of the first transistor is electrically coupled to a second voltage potential;
a second transistor having a gate and two current carrying electrodes, wherein one of said two carrying electrodes of the second transistor is electrically coupled to said second voltage potential, and the other current carrying electrode of the second transistor is electrically coupled to said second stage;
a third transistor having a gate and two current carrying electrodes, wherein one of the two current carrying electrodes of the third transistor is electrically coupled to said second voltage potential, the other one of the two current carrying electrodes of the third transistor is electrically coupled to the gate of the second transistor, and the gate of the third transistor is electrically coupled to one of said at least one low power signal; and
a fourth transistor, having a gate and two current carrying electrodes, wherein one of the two current carrying electrodes of the fourth transistor is electrically coupled to the gate of the first transistor, the other one of the two current carrying electrodes of the fourth transistor is electrically coupled to the gate of the second transistor, and the gate of the fourth transistor is electrically coupled to another one of said at least one low power signal.
5. An electronic circuit in accordance with claim 1, wherein said first stage comprises:
a first transistor of the first stage having a gate and two current carrying electrodes, wherein one of the two current carrying electrodes of the first transistor of the first stage is electrically coupled to a first voltage potential, the second one of the two current carrying electrodes of the first transistor of the first stage is electrically coupled to said current mirror, and said gate of said first transistor of the first stage is electrically coupled to one of said at least one enable signal; and
a second transistor of the first stage having a gate and two current carrying electrodes, wherein one of the two current carrying electrodes of the second transistor of the first stage is electrically coupled to said current mirror, the other one of the two current carrying electrodes of the second transistor of the first stage is electrically coupled to said second stage, and said gate of the second transistor of the first stage is electrically coupled to another one of said at least one enable signal.
6. An electronic circuit in accordance with claim 1, wherein said second stage comprises:
a plurality of transistors each having a gate and two current carrying electrodes, wherein one of the two current carrying electrodes of each one of said plurality of transistors of the second stage is electrically coupled to said first stage, the other one of the two current carrying electrodes of each one of said plurality of transistors of the second stage is electrically coupled to a different one of said plurality of output nodes, and the gate of each of the plurality of transistors of the second stage is electrically coupled to a different one of the at least one control signal;
a plurality of resistors, wherein each one of the plurality of resistors is electrically coupled between a different one of said plurality of output nodes and said first voltage potential.
7. An electronic circuit in accordance with claim 1 further comprising a pull up circuit for reducing an amount of time in which said current mirror to starts providing said current, wherein said pull up circuit is responsive to a pull up signal.
8. An electronic circuit in accordance with claim 7, wherein said pull up circuit is responsive to a pulse width of said pull up signal.
9. An electronic circuit in accordance with claim 7, wherein said pull up circuit comprises a pull up transistor having a gate and two current carrying electrodes, said two current carrying electrodes of said pull up transistor being electrically coupled between said current mirror and a reference voltage, said gate of said pull up transistor being electrically coupled to said pull up signal.
10. An electronic circuit in accordance with claim 9, wherein said current mirror comprises a current mirror transistor having a gate, and said current carrying electrodes of said pull up transistor are electrically coupled between the current mirror transistor gate and said reference voltage.
11. An electronic circuit in accordance with claim 10, said current mirror provides said current when a voltage on said current mirror transistor gate is one of greater than a threshold voltage and less than a threshold voltage, and said reference voltage is approximately equal to the difference between said first voltage potential and said threshold voltage.
12. An integrated bi-directional buffer circuit comprising:
a first transistor having a gate and two current carrying electrodes, wherein one of the two current carrying electrodes of the first transistor is electrically coupled to the gate of the first transistor and to a current source, and the other one of two current carrying electrode of the first transistor is electrically coupled to a first voltage potential;
a second transistor having a gate, a first current carrying electrode, and a second current carrying electrode, wherein the first current carrying electrode of the second transistor is electrically coupled to said first voltage potential;
a third transistor having a gate and two current carrying electrodes, wherein the two current carrying electrodes of the third transistor are electrically coupled between said first voltage potential and the gate of the second transistor, and the gate of the third transistor is electrically coupled to an inverted low power signal;
a fourth transistor, having a gate and two current carrying electrodes, wherein the two current carrying electrodes of the fourth transistor are electrically coupled between the gate of the first transistor and the gate of the second transistor, and the gate of the fourth transistor is electrically coupled to a low power signal;
a fifth transistor having a gate and two current carrying electrodes, wherein the two current carrying electrodes of the fifth transistor are electrically coupled between a second voltage potential and said second current carrying electrode of said second transistor, and said gate of said fifth transistor is electrically coupled to an enable signal;
a sixth transistor having a gate, a first current carrying electrode, and a second current carrying electrode, wherein the first current carrying electrode of the sixth transistor is electrically coupled to said second current carrying electrode of said second transistor, and said gate of the sixth transistor is electrically coupled to an inverted enable signal;
a seventh transistor having a gate and two current carrying electrodes, wherein the two current carrying electrodes of said seventh transistor are electrically coupled between said second current carrying electrode of said sixth transistor and a first output node, and the gate of the seventh transistor is electrically coupled to a first control signal;
an eighth transistor having a gate and two current carrying electrodes, wherein the two current carrying electrodes of said eighth transistor are electrically coupled between said second current carrying electrode of said sixth transistor and a second output node, and the gate of the eighth transistor is electrically coupled to a second control signal;
a first resistor and a second resistor, wherein the first resistor is electrically coupled between said first output node and said second voltage potential, and said second resistor is eclectically coupled between said second output node and said second voltage potential; and
a ninth transistor having a gate and two current carrying electrodes, wherein the current carrying electrodes of the ninth transistor are electrically coupled between a reference voltage and said gate of said second transistor, and said gate of said ninth transistor is electrically coupled to a pull up signal.