Author: claimsbot

What is claimed is:

1. A portable electronic device including a camera rotatably mounted on a casing having a front wall and a rear wall, and a display for displaying thereon an image taken by said camera at the front wall of said casing, wherein
said camera is arranged in said casing at a location between the front side and the rear side thereof;
said casing has a pair of windows which are formed in, and enclosed on their peripheries by, the front and rear walls thereof, respectively, and through which said camera is operated to rotate by a user and allowed to view the outside of said casing so as to ensure its field of view; and
said camera is rotatably supported on said casing through a rotational operation mechanism which is rotated by the user through said windows formed in the front and rear walls, respectively, from outside of said casing thereby to change a direction of view of said camera in a range between a direction of said front wall and a direction of said rear wall.
2. A portable electronic device comprising:
a casing having a front wall and a rear wall;
a camera disposed in a space between said front and rear walls of said casing so as to be rotatable in a direction from said front wall to the rear wall or vice versa;
a display provided on said front wall of said casing for displaying thereon an image taken by said camera;
a first window which is formed in said front wall of said casing and through which said camera is able to view the outside of said casing and is operated to rotate by a user;
a second window which is formed in said rear wall of said casing, and through which said camera is able to view the outside of said casing and is operated to rotate by the user; and
a bridge portion disposed in a peripheral portion of said casing connecting between said front and rear walls of said casing for forming a part of each of frames for said first and second windows.
3. The portable electronic device as set forth in claim 2, wherein
said casing has an end wall in said peripheral portion of said casing for connecting between corresponding ends of said front wall and said rear wall;
said first window is formed to extend from said front wall to said end wall; and
said second window is also formed to extend from said rear wall to said end wall.
4. The portable electronic device as set forth in claim 3, wherein
said end wall has a thickness equal to a distance between said front wall and said rear wall, and a width in a direction perpendicular to a thicknesswise direction; and
said bridge portion extends in the widthwise direction of said end wall and has a thickness less than that of said end wall.
5. The portable electronic device as set forth in claim 2, wherein
said bridge portion has such a width that it is able to cover the whole or a part of a prescribed proportion or more of the shooting range of said camera at least at a certain rotational position of said camera during the time when said camera is being rotated to reach the bridge portion.
6. The portable electronic device as set forth in claim 2, wherein
said bridge portion includes a prescribed pattern, a picture of which is to be taken by said camera.
7. The portable electronic device as set forth in claim 2, wherein
said bridge portion is integrally molded to said casing.
8. The portable electronic device as set forth in claim 2, wherein
an image display panel with said display mounted thereon and a switch operation panel with a switch mounted thereon are integrally connected with each other in a foldable manner; and
said camera is disposed between said display and an outer peripheral portion of said casing of said image display panel.
9. The portable electronic device as set forth in claim 8, wherein
said camera is rotatable about an axis which is parallel to a folding axis about which said image display panel and said switch operation panel are foldable with respect to each other.
10. The portable electronic device as set forth in claim 8, wherein
said camera is rotatable about an axis perpendicular to a folding axis about which said image display panel and said switch operation panel are foldable with respect to each other.
11. A portable electronic device comprising:
a casing having a front wall and a rear wall;
a camera disposed in a space between said front and rear walls of said casing so as to be rotatable in a direction from said front wall to the rear wall or vice versa;
a display provided on said front wall of said casing for displaying thereon an image taken by said camera;
a first window which is formed in said front wall and through which said camera is able to view the outside of said casing;
a second window which is formed in said rear wall and through which said camera is able to view the outside of said casing;
a bridge portion disposed in a peripheral portion of said casing connecting between said front and rear walls of said casing for forming a part of each of frames for said first and second windows; and
a control part for performing prescribed control based on an image of said bridge portion taken by said camera.
12. The portable electronic device as set forth in claim 11, wherein
said bridge portion includes a prescribed pattern which is to be photographed by said camera, said control part being operable to perform said prescribed control based on an image of said prescribed pattern taken by said camera.
13. The portable electronic device as set forth in claim 11, wherein
said control part performs an indication on said display to the effect that a shooting plane of said camera has been changed from said front side to said rear side or vice versa.
14. A portable electronic device as set forth in claim 11, wherein
said control part controls said display in such a manner that an inverted image taken by said camera is turned upside down to provide an erect image on said display.
15. A portable electronic device including a camera and a display for displaying an image taken by said camera, said camera and said display being disposed in a casing, wherein
said camera is disposed in, and mounted on, said casing for rotation in a direction from a front side to a rear side of said casing or vice versa;
said casing has a pair of windows formed at its front side and rear side, respectively, through which said camera views the outside of said casing; and
a control part is provided for performing prescribed control based on an image of a wall of said casing which is taken by said camera and which lies between said front side and said rear side.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor light emitting diode, comprising:
a light emitting structure comprising an upper surface comprising an N-face; and
an ohmic electrode structure arranged on the light emitting structure, the ohmic electrode structure comprising:
a contact layer arranged on the N-face of the light emitting structure;
a protective layer arranged on the contact layer;
a lower diffusion preventing layer disposed between the contact layer and the N-face of the light emitting structure; and
an upper diffusion preventing layer disposed between the contact layer and the protective layer.
2. The semiconductor light emitting diode according to claim 1, wherein: the lower diffusion preventing layer comprises at least one of Mo and W; the contact layer comprises at least one of Ti, TiN, a Ti\u2014Ni alloy, Ta, and a W\u2014Ti alloy; the upper diffusion preventing layer comprises a metal layer comprising at least one of W, Cr, Ru, Pt, Ni, Pd, Ir, Rh, and Nb, or an oxide film comprising at least one of RuOx, NiOx, IrOx, RhOx, NbOx, TiOx, TaOx, CrOx, and WOx; and the protective layer comprises Al.
3. The semiconductor light emitting diode according to claim 2, wherein the lower diffusion preventing layer comprises a Mo layer or a W layer.
4. The semiconductor light emitting diode according to claim 2, wherein the contact layer comprises a Ti layer.
5. The semiconductor light emitting diode according to claim 2, wherein the contact layer comprises Ti and the upper diffusion preventing layer comprises W.
6. The semiconductor light emitting diode according to claim 2, wherein the lower diffusion preventing layer has a thickness of 1 \u212b to 10 \u212b.
7. The semiconductor light emitting diode according to claim 2, wherein the contact layer has a thickness of 10 \u212b to 50 \u212b.
8. The semiconductor light emitting diode according to claim 2, wherein the upper diffusion preventing layer has a thickness of 100 \u212b to 1000 \u212b.
9. The semiconductor light emitting diode according to claim 1, wherein the light emitting structure comprises an n-type semiconductor layer, an active layer, and a p-type semiconductor layer, and the ohmic electrode structure is arranged on the n-type semiconductor layer.
10. The semiconductor light emitting diode according to claim 9, further comprising an ohmic electrode contacting the p-type semiconductor layer.
11. A method of manufacturing a semiconductor light emitting diode, the method comprising:
forming a light emitting structure comprising an upper surface comprising an N-face; and
forming an ohmic electrode structure on the N-face of the light emitting structure, the ohmic electrode structure comprising a lower diffusion preventing layer, a contact layer, an upper diffusion preventing layer, and a protective layer.
12. The method according to claim 11, wherein: the lower diffusion preventing layer comprises at least one of Mo and W; the contact layer comprises at least one of Ti, TiN, a Ti\u2014Ni alloy, Ta, and a W\u2014Ti alloy; the upper diffusion preventing layer comprises a metal layer formed of at least one of W, Cr, Ru, Pt, Ni, Pd, Ir, Rh, and Nb, or an oxide film formed of at least one of RuOx, NiOx, IrOx, RhOx, NbOx, TiOx, TaOx, CrOx, and WOx; and the protective layer is formed of Al.
13. The method according to claim 12, wherein the contact layer comprises Ti.
14. The method according to claim 13, wherein the upper diffusion preventing layer comprises W.
15. The method according to claim 11, further comprising: surface-treating the light emitting structure before forming the ohmic electrode structure.
16. The method according to claim 15, wherein the surface treatment comprises dipping a surface of the light emitting structure in aqua regia, followed by washing the surface of the light emitting structure using deionized water, and drying the surface of the light emitting structure using nitrogen.
17. The method according to claim 11, further comprising: heat-treating the ohmic electrode structure.
18. The method according to claim 17, wherein the heat treatment is performed at a temperature of 150\xb0 C. to 600\xb0 C.
19. The semiconductor light emitting diode according to claim 1, wherein the lower diffusion preventing layer contacts the N-face of the light emitting structure, the contact layer contacts the lower diffusion preventing layer, the upper diffusing preventing layer contacts the contact layer, and the Al protective layer contacts the upper diffusing preventing layer.
20. The method according to claim 11, wherein forming the ohmic electrode structure comprises:
forming the lower diffusion preventing layer on the N-face of the light emitting structure;
forming the contact layer on the lower diffusion preventing layer;
forming the upper diffusion preventing layer on the contact layer; and
forming the protective layer on the upper diffusion preventing layer.

1. A method operational on a user equipment, comprising:
obtaining a pre-defined list of features, wherein the predefined list of features comprises a list of potential features provided by cells in an access network and service capability information associated with each listed potential feature;
connecting to a cell in the access network subsequent to obtaining the predefined list of features;
receiving a wireless transmission from the cell;
determining at least one feature provided by the cell based in part on information included in the wireless transmission, wherein the at least one feature provided by the cell is derived from the information provided in the wireless transmission;
storing in a storage medium information relating to the at least one feature provided by the cell; and
displaying an indicator identifying a service capability corresponding to the stored information and a capability of the user equipment, wherein displaying the indicator identifying the service capability corresponding to the stored information and the capability of the user equipment comprises:
determining the service capability associated with the at least one feature;

determining that the user equipment is capable of utilizing the at least one feature; and
displaying the indicator when the user equipment is capable of utilizing the at least one feature.
2. The method of claim 1, wherein connecting to the cell comprises:
connecting to the cell in one of an active mode or an idle mode.
3. The method of claim 1, wherein receiving the wireless transmission from the cell comprises at least one of:
receiving a system information block from the cell;
conducting a radio resource control (RRC) connection setup procedure with the cell; or
performing a radio bearer (RB) setup procedure.
4. The method of claim 1, wherein receiving the wireless transmission from the cell comprises:
receiving a wireless communication explicitly identifying the at least one feature as being provided by the cell.
5. The method of claim 1, wherein storing in the storage medium the information relating to the features provided by the cell comprises:
updating the pre-defined list of features stored in the storage medium to indicate that the at least one feature is provided by the cell.
6. The method of claim 1, wherein storing in the storage medium the information relating to the features provided by the cell comprises:
storing in a user identity module the information relating to the features provided by the cell.
7. The method of claim 1, wherein displaying the indicator identifying the service capability corresponding to the stored information and the capability of the user equipment comprises:
displaying the indicator identifying a network generation determined to be associated with the stored information.
8. An apparatus for wireless communication, comprising:
a communications interface adapted to facilitate wireless communication;
a storage medium;
a user interface; and
a processing circuit coupled to the communications interface, the storage medium, and the user interface, the processing circuit adapted to:
obtain a pre-defined list of features, wherein the predefined list of features comprises a list of potential features provided by cells in an access network and service ca ability information associated with each listed potential feature;
connect to a cell in the access network via the communications interface subsequent to obtaining the predefined list of features;
receive a wireless transmission from the cell;
determine at least one feature provided by the cell based in part on information included in the wireless transmission, wherein the at least one feature provided by the cell is derived from the information provided in the wireless transmission;
store in the storage medium information relating to the at least one feature provided by the cell; and
display an indicator on the user interface to identify a service capability corresponding to the stored information and a capability of the apparatus, wherein the processing circuit adapted to display the indicator on the user interface to identify a service capability corresponding to the stored information and a capability of the apparatus comprises the processing circuit adapted to:
determine the service capability associated with the at least one feature;
determine that the apparatus is capable of utilizing the at least one feature; and
display the indicator when the apparatus is capable of utilizing the at least one feature.
9. The apparatus of claim 8, wherein the processing circuit is adapted to connect to the cell in one of an active mode or an idle mode.
10. The apparatus of claim 8, wherein the received transmission comprises at least one of a system information block, a transmission associated with a radio resource control (RRC) connection setup procedure, or a transmission associated with a radio bearer (RB) setup procedure.
11. The apparatus of claim 8, wherein the received transmission comprises an explicit indication of the at least one feature provided by the cell.
12. The apparatus of claim 8, wherein the information relating to the at least one feature provided by the cell is stored by updating the pre-defined list of features stored in the storage medium.
13. The apparatus of claim 8, wherein the storage medium comprises a user identity module.
14. The apparatus of claim 8, wherein the displayed indicator comprises a network generation determined to be associated with the stored information.
15. An apparatus for wireless communication, comprising:
means for obtaining a pre-defined list of features, wherein the predefined list of features comprises a list of potential features provided by cells in an access network and service capability information associated with each listed potential feature;
means for connecting to a cell in the access network subsequent to obtaining the predefined list of features;
means for receiving a wireless transmission from the cell;
means for determining at least one feature provided by the cell based in part on information included in the wireless transmission, wherein the at least one feature provided by the cell is derived from the information provided in the wireless transmission;
means for storing in a storage medium information relating to the at least one feature provided by the cell; and
means for displaying an indicator identifying a service capability corresponding to the stored information and a capability of the apparatus, wherein the means for displaying the indicator identifying the service capability corresponding to the stored information and the capability of the user equipment comprises:
means for determining the service capability associated with the at least one feature;
means for determining that the user equipment is capable of utilizing the at least one feature; and
means for displaying the indicator when the user equipment is capable of utilizing the at least one feature.
16. The apparatus of claim 15, wherein the means for receiving the wireless transmission further comprises at least one of:
means for receiving a system information block from the cell;
means for conducting a radio resource control (RRC) connection setup procedure with the cell; or
means for performing a radio bearer (RB) setup procedure.
17. The apparatus of claim 15, wherein the means for storing in the storage medium further comprises:
means for updating the pre-defined list of features stored in the storage medium to indicate that the at least one feature is provided by the cell.
18. A computer program product for wireless communication, comprising: a non-transitory computer readable medium, comprising:
at least one instruction executable by a computer to obtain a pre-defined list of features, wherein the predefined list of features comprises a list of potential features provided by cells in an access network and service capability information associated with each listed potential feature;
at least one instruction executable by the computer to connect to a cell in the access network subsequent to obtaining the predefined list of features;
at least one instruction executable by the computer to receive a wireless transmission from the cell;
at least one instruction executable by the computer to determine at least one feature provided by the cell based in part on information included in the wireless transmission, wherein the at least one feature provided by the cell is derived from the information provided in the wireless transmission;
at least one instruction executable by the computer to store in a storage medium information relating to the at least one feature provided by the cell; and
at least one instruction executable by the computer to display an indicator identifying a service capability corresponding to the stored information and a capability of the apparatus, wherein the at least one instruction executable by the computer to display the indicator identifying the service capability corresponding to the stored information and the capability of the user equipment comprises:
at least one instruction executable by the computer to determine the service capability associated with the at least one feature;
at least one instruction executable by the computer to determine that the user equipment is capable of utilizing the at least one feature; and
at least one instruction executable by the computer to display the indicator when the user equipment is capable of utilizing the at least one feature.
19. The computer program product of claim 18, wherein the at least one instruction executable by the computer to receive the wireless transmission further comprises at least one of:
at least one instruction executable by the computer to receive a system information block from the cell;
at least one instruction executable by the computer to conduct a radio resource control (RRC) connection setup procedure with the cell; or
at least one instruction executable by the computer to perform a radio bearer (RB) setup procedure.
20. The apparatus of claim 18, wherein the at least one instruction executable by the computer to store in the storage medium further comprises:
at least one instruction executable by the computer to update the pre-defined list of features stored in the storage medium to indicate that the at least one feature is provided by the cell.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A monolithic three-dimensional integrated circuit, comprising:
a three-dimensional memory array including a first layer of memory cells and a second layer of memory cells, the first layer of memory cells includes a first memory cell, the second layer of memory cells includes a second memory cell, the first memory cell is located above the second memory cell, the second memory cell is located above a substrate, the first memory cell and the second memory cell are formed above the substrate without any intervening substrates between the first memory cell and the second memory cell; and
a controller in communication with the three-dimensional memory array, the controller causes a first set of memory operations to be performed on the three-dimensional memory array, a first set of biasing conditions is applied to the three-dimensional memory array during the first set of memory operations, the controller detects that a load current associated with a voltage regulator biasing the three-dimensional memory array during the first set of memory operations is greater than a threshold, the controller determines a second set of biasing conditions different from the first set of biasing conditions in response to detecting that the load current is greater than the threshold, the controller causes a second set of memory operations to be performed on the three-dimensional memory array, the second set of biasing conditions is applied to the three-dimensional memory array during the second set of memory operations.
2. The monolithic three-dimensional integrated circuit of claim 1, wherein:
the first memory cell and the second memory cell are arranged in a vertical column that is perpendicular to the substrate.
3. The monolithic three-dimensional integrated circuit of claim 1, wherein:
the first memory cell and the second memory cell are located within a vertical plane that is perpendicular to the substrate.
4. The monolithic three-dimensional integrated circuit of claim 1, wherein:
the first memory cell and the second memory cell are in communication with a first bit line, the first bit line is arranged in a vertical direction that is perpendicular to the substrate.
5. The monolithic three-dimensional integrated circuit of claim 1, wherein:
the first layer of memory cells includes a third memory cell, the second layer of memory cells includes a fourth memory cell, the third memory cell is located above the fourth memory cell, the first memory cell and the third memory cell are arranged in a first horizontal plane, the second memory cell and the fourth memory cell are arranged in a second horizontal plane that is below the first horizontal plane.
6. The monolithic three-dimensional integrated circuit of claim 1, wherein:
the three-dimensional memory array and the controller are integrated within the monolithic three-dimensional integrated circuit.
7. The monolithic three-dimensional integrated circuit of claim 1, further comprising:
supporting circuitry for the three-dimensional memory array, the supporting circuitry and the controller are integrated within the monolithic three-dimensional integrated circuit, the three-dimensional memory array is fabricated above the supporting circuitry.
8. The monolithic three-dimensional integrated circuit of claim 1, wherein:
the controller detects that a temperature corresponding with the three-dimensional memory array is greater than a temperature threshold, the controller detects that the load current associated with the voltage regulator biasing the three-dimensional memory array during the first set of memory operations is greater than the threshold in response to detecting that the temperature corresponding with the three-dimensional memory array is greater than the temperature threshold.
9. The monolithic three-dimensional integrated circuit of claim 1, wherein:
the first set of memory operations comprises a first set of write operations performed on the three-dimensional memory array, the second set of memory operations comprises a second set of write operations performed on the three-dimensional memory array, the controller adjusts a number of memory cells that are programmed simultaneously within the three-dimensional memory array during the second set of write operations in response to detecting that the load current is greater than the threshold.
10. The monolithic three-dimensional integrated circuit of claim 1, wherein:
the first set of memory operations comprises a first set of read operations, the second set of memory operations comprises a second set of read operations, the controller adjusts a number of memory cells that are read simultaneously from the three-dimensional memory array during the second set of read operations in response to detecting that the load current is greater than the threshold.
11. A monolithic three-dimensional integrated circuit, comprising:
a three-dimensional memory array including a plurality of memory cells, the plurality of memory cells includes a first memory cell and a second memory cell, the first memory cell is formed above the second memory cell, the second memory cell is formed above a substrate, the first memory cell and the second memory cell are arranged in a vertical column that is perpendicular to the substrate, the three-dimensional memory array includes a plurality of control lines connected to the plurality of memory cells;
a voltage regulator, the voltage regulator generates a first reference voltage;
a current load monitoring circuit, the current load monitoring circuit determines a load current associated with the voltage regulator, the current load monitoring circuit includes an input current mirroring stage and a current load measuring circuit, the current load measuring circuit regulates a common node of the input current mirroring stage to the first reference voltage; and
one or more managing circuits in communication with the voltage regulator and the current load monitoring circuit, the one or more managing circuits cause a first set of memory operations to be performed on the three-dimensional memory array, the first reference voltage is applied to the plurality of control lines during the first set of memory operations, the one or more managing circuits detect that the load current associated with the voltage regulator during the first set of memory operations is greater than a threshold, the one or more managing circuits cause the voltage regulator to generate a second reference voltage different from the first reference voltage in response to detecting that the load current is greater than the threshold, the one or more managing circuits cause a second set of memory operations to be performed on the three-dimensional memory array, the second reference voltage is applied to the plurality of control lines during the second set of memory operations.
12. The monolithic three-dimensional integrated circuit of claim 11, wherein:
the plurality of control lines comprises a plurality of word lines, the plurality of word lines includes a first word line in communication with the first memory cell and a second word line in communication with the second memory cell.
13. The monolithic three-dimensional integrated circuit of claim 11, wherein:
the first memory cell and the second memory cell are in communication with a first bit line, the first bit line is arranged in a vertical direction that is perpendicular to the substrate.
14. The monolithic three-dimensional integrated circuit of claim 11, wherein:
the three-dimensional memory array includes a third memory cell and a fourth memory cell, the third memory cell is located above the fourth memory cell, the first memory cell and the third memory cell are arranged in a first horizontal plane, the second memory cell and the fourth memory cell are arranged in a second horizontal plane that is located below the first horizontal plane.
15. The monolithic three-dimensional integrated circuit of claim 11, wherein:
the three-dimensional memory array and the one or more managing circuits are formed within the monolithic three-dimensional integrated circuit, the three-dimensional memory array is formed above the one or more managing circuits.
16. The monolithic three-dimensional integrated circuit of claim 11, further comprising:
a temperature sensor, the temperature sensor determines a temperature associated with the three-dimensional memory array, the one or more managing circuits detect that the temperature associated with the three-dimensional memory array is greater than a temperature threshold, the one or more managing circuits determine whether the load current associated with the voltage regulator during the first set of memory operations is greater than a threshold in response to detecting that the temperature associated with the three-dimensional memory array is greater than the temperature threshold.
17. The monolithic three-dimensional integrated circuit of claim 11, wherein:
the first set of memory operations comprises a first set of write operations, the one or more managing circuits adjust a number of memory cells that are programmed simultaneously within the three-dimensional memory array in response to detecting that the load current is greater than the threshold.
18. The monolithic three-dimensional integrated circuit of claim 11, wherein:
the first set of memory operations comprises a first set of read operations, the one or more managing circuits adjust a number of memory cells that are read simultaneously from the three-dimensional memory array in response to detecting that the load current is greater than the threshold.
19. A monolithic three-dimensional integrated circuit, comprising:
a three-dimensional memory array including a first string of memory cells, the first string of memory cells includes a first memory cell and a second memory cell arranged in a vertical column that is perpendicular to a substrate, the first memory cell and the second memory cell are formed above the substrate without any intervening substrates between the first memory cell and the second memory cell; and
supporting circuitry in communication with the three-dimensional memory array, the supporting circuitry causes a first set of memory operations to be performed on the three-dimensional memory array, the first set of biasing conditions is applied to the three-dimensional memory array during the first set of memory operations, the supporting circuitry detects that a load current associated with a voltage regulator biasing the three-dimensional memory array during the first set of memory operations is greater than a threshold, the supporting circuitry determines a second set of biasing conditions different from the first set of biasing conditions in response to detecting that the load current is greater than the threshold, the supporting circuitry causes a second set of memory operations to be performed on the three-dimensional memory array, the second set of biasing conditions is applied to the three-dimensional memory array during the second set of memory operations.
20. The monolithic three-dimensional integrated circuit of claim 19, wherein:
the first memory cell and the second memory cell are in communication with a first bit line, the first bit line is arranged in a vertical direction that is perpendicular to the substrate.
21. The monolithic three-dimensional integrated circuit of claim 19, wherein:
the three-dimensional memory array includes a second string of memory cells, the second string of memory cells includes a third memory cell and a fourth memory cell, the first memory cell is formed above the second memory cell, the second memory cell is formed above the substrate, the third memory cell is located above the fourth memory cell, the first memory cell and the third memory cell are arranged in a first horizontal plane, the second memory cell and the fourth memory cell are arranged in a second horizontal plane that is below the first horizontal plane.
22. The monolithic three-dimensional integrated circuit of claim 19, wherein:
the three-dimensional memory array and the supporting circuitry are formed within the monolithic three-dimensional integrated circuit, the three-dimensional memory array is formed above the supporting circuitry.
23. A method for operating a monolithic three-dimensional integrated circuit, comprising:
performing a first set of memory operations on a three-dimensional memory array, the three-dimensional memory array includes a first layer of memory cells and a second layer of memory cells, the first layer of memory cells includes a first memory cell, the second layer of memory cells includes a second memory cell, the first memory cell is located above the second memory cell, the second memory cell is located above a substrate, the first memory cell and the second memory cell are arranged in a vertical column that is perpendicular to the substrate, the first set of memory operations includes applying a first voltage to a first control line connected to the first memory cell;
detecting that a load current associated with a voltage regulator generating the first voltage during the first set of memory operations is greater than a threshold;
generating a second voltage different from the first voltage in response to the detecting; and
performing a second set of memory operations on the three-dimensional memory array, the second set of memory operations includes applying the second voltage to the first control line connected to the first memory cell.
24. The method of claim 23, wherein:
the first set of memory operations comprises a first set of write operations, the second set of memory operations comprises a second set of write operations, the first control line comprises a first word line, the voltage regulator generates the second voltage during the second set of memory operations.
25. The method of claim 23, wherein:
the first memory cell and the second memory cell are in communication with a first bit line, the first bit line is arranged in a vertical direction that is perpendicular to the substrate.
26. A monolithic three-dimensional integrated circuit, comprising:
a non-volatile memory, the non-volatile memory is monolithically formed in one or more physical levels of memory cells having active areas disposed above a substrate; and
a controller in communication with the non-volatile memory, the controller causes a first set of memory operations to be performed on the non-volatile memory, a first set of biasing conditions is applied to the non-volatile memory during the first set of memory operations, the controller detects that a load current associated with a voltage regulator biasing the non-volatile memory during the first set of memory operations is greater than a threshold, the controller determines a second set of biasing conditions different from the first set of biasing conditions in response to detecting that the load current is greater than the threshold, the controller causes a second set of memory operations to be performed on the non-volatile memory, the second set of biasing conditions is applied to the non-volatile memory during the second set of memory operations.
27. A monolithic three-dimensional integrated circuit, comprising:
a non-volatile memory, the non-volatile memory is monolithically formed in one or more physical levels of memory cells having active areas disposed above a substrate; and
a voltage regulator, the voltage regulator generates a first reference voltage;
a current load monitoring circuit, the current load monitoring circuit determines a load current associated with the voltage regulator, the current load monitoring circuit includes an input current mirroring stage and a current load measuring circuit, the current load measuring circuit regulates a common node of the input current mirroring stage to the first reference voltage; and
one or more managing circuits in communication with the voltage regulator and the current load monitoring circuit, the one or more managing circuits cause a first set of memory operations to be performed on the non-volatile memory, the first reference voltage is applied to the plurality of control lines during the first set of memory operations, the one or more managing circuits detect that the load current associated with the voltage regulator during the first set of memory operations is greater than a threshold, the one or more managing circuits cause the voltage regulator to generate a second reference voltage different from the first reference voltage in response to detecting that the load current is greater than the threshold, the one or more managing circuits cause a second set of memory operations to be performed on the non-volatile memory, the second reference voltage is applied to the plurality of control lines during the second set of memory operations.
28. A method for operating a monolithic three-dimensional integrated circuit, comprising:
performing a first set of memory operations on a non-volatile memory, the non-volatile memory includes a first memory cell, the non-volatile memory is monolithically formed in one or more physical levels of memory cells having active areas disposed above a substrate, the first set of memory operations includes applying a first voltage to a first control line connected to the first memory cell;
detecting that a load current associated with a voltage regulator generating the first voltage during the first set of memory operations is greater than a threshold;
generating a second voltage different from the first voltage in response to the detecting; and
performing a second set of memory operations on the non-volatile memory, the second set of memory operations includes applying the second voltage to the first control line connected to the first memory cell.