Author: claimsbot

1. A transfer chamber to accept wafers from atmospheric conditions and transfer wafers on to other processing chambers under vacuum condition, comprising:
an enclosure having an entrance to accept wafers from atmospheric conditions;
a robotic arm to feed wafers from a supply source at atmospheric conditions into said enclosure;
a non-contact chuck comprising a cushioned platform positioned above the entrance of said enclosure in a position generally parallel to a wafer in said enclosure on said robotic arm to elevate the wafer from said robotic arm toward said cushioned platform;
an electrostatic chuck generally at the base of said enclosure in a position generally parallel to said non-contact wafer chuck;
a vacuum pump to draw a vacuum in said enclosure.
2. A transfer chamber in accordance with claim 1, wherein the non-contact chuck is configured to apply a negative pressure gas to elevate the wafer from said robotic arm toward said cushioned platform.
3. A transfer chamber in accordance with claim 2, wherein the non-contact chuck is further configured to apply a positive pressure gas to maintain the wafer out of contact with said non-contact chuck while in position adjacent to said non-contact chuck.
4. A transfer chamber in accordance with claim 1, further comprising a carrier configured for transferring said electrostatic chuck from said enclosure and into an adjacent processing chamber.
5. A transfer chamber in accordance with claim 4, further comprising transport system cooperating to move said carrier out of said enclosure and into the adjacent processing chamber under vacuum condition.
6. A transfer chamber in accordance with claim 5, wherein the transport system is configured to transport said carrier back to said enclosure where said wafer is transferred to near contact with said non-contact chuck with positive and negative gas pressures and then released to the robotic arm for removal of the wafer from said load lock.
7. A transfer chamber in accordance with claim 5, further comprising a pedestal to elevate said electrostatic chuck to a position underlying the wafer at said non-contact chuck to transfer the wafer from its position at said non-contact chuck to a position adjacent to said electrostatic chuck in near contact with said electrostatic chuck, and to lower said pedestal with said electrostatic chuck and said wafer while in near contact with said electrostatic chuck away from said non-contact chuck, and wherein said carrier comprises an opening for accepting the pedestal there-through.
8. A transfer chamber in accordance with claim 1, further comprising a drive means to move said robotic arm out of said enclosure and to seal the entrance to said enclosure.
9. A transfer chamber in accordance with claim 1, wherein said electrostatic chuck comprises pathways to supply negative and positive gas pressure through its volume.
10. A transfer chamber in accordance with claim 9, further comprising a pedestal to elevate said electrostatic chuck to a position underlying the wafer at said non-contact chuck to transfer the wafer from its position at said non-contact chuck to a position adjacent to said electrostatic chuck in near contact with said electrostatic chuck, and to lower said pedestal with said electrostatic chuck and said wafer while in near contact with said electrostatic chuck away from said non-contact chuck.
11. A transfer chamber in accordance with claim 10, further comprising means for striking plasma in said enclosure to electrostatically bind the wafer to said electrostatic chuck.
12. A transfer chamber in accordance with claim 1, further comprising a centering mechanism operable to maintain the wafer centered while held by the non-contact chuck.
13. A transfer chamber in accordance with claim 1, further comprising temperature control systems to apply temperature controls to said wafer.
14. A transfer chamber in accordance with claim 1, wherein the non-contact chuck is configured to apply a negative pressure gas to elevate the wafer from said robotic arm toward said cushioned platform and to apply a positive pressure gas to maintain the wafer out of contact with said non-contact chuck while in position adjacent to said non-contact chuck; and further comprising a pedestal to elevate said electrostatic chuck to a position underlying the wafer at said non-contact chuck to transfer the wafer from its position at said non-contact chuck to a position adjacent to said electrostatic chuck in near contact with said electrostatic chuck, and to lower said pedestal with said electrostatic chuck and said wafer while in near contact with said electrostatic chuck away from said non-contact chuck.
15. A transfer chamber in accordance with claim 14, further comprising means for striking plasma in said enclosure to electrostatically bind the wafer to said electrostatic chuck.
16. A transfer chamber in accordance with claim 15, further comprising a centering mechanism operable to maintain the wafer centered while held by the non-contact chuck.
17. A transfer chamber in accordance with claim 16, further comprising a carrier configured for transferring said electrostatic chuck from said enclosure and into an adjacent processing chamber.
18. A transfer chamber in accordance with claim 17, further comprising transport system cooperating to move said carrier out of said enclosure and into the adjacent processing chamber under vacuum condition.
19. A transfer chamber in accordance with claim 18, wherein said electrostatic chuck further comprises temperature control systems to apply temperature controls to said wafer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An optical communication receiver comprising:
an optical splitter having a splitter input and a plurality of splitter outputs, the optical splitter configured to receive an optical channel signal comprising a number K subchannel signals, and output K identical received channel signals;
K subchannel receivers, the subchannel receiver comprising optical and digital circuitry configured to receive the kth of said K identical received channel signals and a reference light beam having a subchannel frequency fk, and output a first digital signal representative of in-phase and quadrature components of a first orthogonal polarization component associated with the subchannel frequency fk, and also output a second digital signal representative of in-phase and quadrature components of a second orthogonal polarization component associated with the subchannel frequency fk, the first and second digital signals containing information representative of a data stream used to modulate the kth subchannel frequency; and
a receiver processor configured to receive said first and second digital signals and output said data stream.
2. The optical communication receiver of claim 1, wherein the receiver further comprises:
a frequency calibration circuit configured to calibrate at least one light source to thereby maintain a frequency spacing of \u0394f between K adjacent subchannel light beams, the frequency calibration circuit receiving, as input, at least K subchannel light beams each characterized by a subchannel frequency fk and outputting at least one frequency calibration control signal applied to at least one light source creating at least one of said K subchannel light beams.
3. The optical communication receiver of claim 2, wherein the frequency calibration circuit comprises:
a first optical switch configured to select from among (a) said K subchannel light beams and (b) a reference light beam, to thereby output a selected beam;
an optical splitter configured to split the selected signal to first and second selected split beams;
an optical delay configured to receive the first selected split beam as input, delay the first selected split beam by a predetermined time delay T, and output a delayed first selected split beam;
an optical detector configured to receive the delayed first selected split beam and the second selected split beam, and output a digitized electrical signal that is proportional to ej\u03c9T, where \u03c9 is the frequency of the selected beam;
a controller configure to receive the digitized electrical signal and output said at least one frequency calibration control signal.
4. The optical communication receiver of claim 1, wherein the kth subchannel receiver comprises:
a polarization beam splitter configured to receive and split the kth of said K identical receiver channel signals into first and second orthogonal polarization components;
a first optical phase detector configured to receive the first orthogonal polarization component and the reference light beam having a subchannel frequency fk as inputs, and output said first digital signal;
a second optical phase detector configured to receive the second orthogonal polarization component and the reference light beam having a subchannel frequency fk as inputs, and output said second digital signal, and wherein
the first and second digital signals are input to said receiver processor.
5. The optical communication receiver of claim 4, wherein the kth subchannel receiver further comprises:
a first variable optical delay configured to selectively delay the first orthogonal polarization component before it is input to the first optical phase detector;
a second variable optical delay configured to selectively delay the second orthogonal polarization component before it is input to the second optical phase detector,
wherein the first and second variable optical delays are controlled by said receiver processor.
6. The optical communication receiver of claim 4, wherein each optical phase detector includes first and second integrate and dump filters configured to integrate detected analog respective in-phase and quadrature signals for an integrating period that is less than a symbol period to thereby produce respective detected analog in-phase and quadrature subchannel signals corresponding to said subchannel frequency fk.
7. The optical communication receiver of claim 1, wherein the receiver processor comprises:
a polarization mode dispersion (PMD) compensation control module configured to digitally compensate the first and second digital signals to thereby produce PMD-compensated first and second digital signals;
a synchronization and symbol timing module configured to produce optical detector control signals including at least one clock signal for controlling the subchannel receiver, based on at least one of the first and second digital signals and the first and second PMD-compensated digital signals; and
a data demodulation module configured to output the data stream that was used to modulate at least one of said K subchannels, based on the first and second PMD-compensated digital signals.
8. The optical communication receiver of claim 7, wherein the synchronization and symbol timing module includes a Stokes-based timing error detector module.
9. The optical communication receiver of claim 7, wherein the synchronization and symbol timing module also includes a Mueller & Muller timing error detector module, and wherein the Stokes-based timing error detector module is invoked first and the Muller and Muller timing error detector module is invoked thereafter.
10. The optical communication receiver of claim 7, wherein the PMD compensation control module is configured to execute an iterative search procedure to find optimum coefficients of a rotation matrix for rotating the first and second digital signals to thereby create the PMD-compensated first and second digital signals.
11. The optical communication receiver of claim 10, wherein, during each iteration, the search procedure calculates at least one metric for each of a plurality of candidate pairs of rotation angles, and selects the candidate pair of rotation angles corresponding to an optimization criterion for said at least one metric, to thereby calculate the coefficients of said rotation matrix, the iterations continuing 5 until a terminating condition is met.
12. The optical communication receiver of claim 11, wherein a step size of the candidate pairs of rotation angles is adjusted at each iteration.
13. The optical communication receiver of claim 7, wherein the receiver processor further comprises a frequency offset compensator.
14. The optical communication receiver of claim 1, wherein the subchannel receiver comprises:
a polarization mode dispersion (PMD) compensator device configured to receive the kth of said K identical receiver channel signals as input and output a PMD-compensated version of said kth identical receiver channel signals, the PMD compensator device being controlled by at least one PMD device control signal from the receiver processor;
a polarization beam splitter configured to receive and split said PMD compensated version of said identical receiver channel signal into first and second orthogonal polarization components;
a first optical phase detector configured to receive the first orthogonal polarization component and the reference light beam having a subchannel frequency fk as inputs, and output said first digital signal;
a second optical phase detector configured to receive the second orthogonal polarization component and the reference light beam having a subchannel frequency fk as inputs, and output said second digital signal, and wherein
the first and second digital signals are input to said receiver processor.
15. The optical communication receiver of claim 14, wherein the subchannel receiver further comprises:
a first variable optical delay configured to selectively delay the first orthogonal polarization component before it is input to the first optical phase detector;
a second variable optical delay configured to selectively delay the second orthogonal polarization component before it is input to the second optical phase detector,
wherein the first and second variable optical delays are controlled by said receiver processor.
16. The optical communication receiver of claim 14, wherein each optical phase detector includes first and second integrate and dump filters configured to integrate detected analog respective in-phase and quadrature signals for an integrating period that is less than a symbol period to thereby produce respective detected analog in-phase and quadrature subchannel signals corresponding to said subchannel frequency fk.
17. The optical communication receiver of claim 14, wherein the receiver processor comprises:
a polarization mode dispersion (PMD) compensation control module configured to produce said at least one PMD device control signal, based on the first and second digital signals;
a synchronization and symbol timing module configured to produce optical detector control signals including at least one clock signal for controlling the subchannel receiver, based on said first and second digital signals; and
a data demodulation module configured to output the data stream that was used to modulate the kth subchannel, based on the first and second digital signals.
18. The optical communication receiver of claim 17, wherein the synchronization and symbol timing module includes Mueller & Muller timing error detector module.
19. The optical communication receiver of claim 17, wherein the PMD compensation control module is configured to execute an iterative search procedure to find optimum rotation angles for producing the PMD device control signals.
20. The optical communication receiver of claim 19, wherein, during each iteration, the search procedure determines a candidate pair of rotation angles, calculates said at least one metric for said candidate pair of rotation angles, stores the metric, and produces said at least one PMD device control signal that is applied to the PMD compensator device, for each candidate pair of rotation angles.
21. The optical communication receiver of claim 20, wherein a step size governing selection of the candidate pairs of rotation angles is adjusted at each iteration.
22. The optical communication receiver of claim 17, wherein the receiver processor further comprises a frequency offset compensator.
23. A frequency calibration system for calibrating a number K of laser light beams, each laser light beam having a frequency fk, k=1, 2, 3, . . . , K, the frequency calibration system comprising:
an optical switch system configured to select one from among the K laser light beams and a reference beam and output a selected beam;
a splitter disposed to receive the selected beam and output first identical first and second selected beams;
an optical detector configured to receive a delayed version of the first selected beam and the second selected beam, and output at least one electrical signal proportional to a phase difference between the two beams;
a controller configured to receive said at least one electrical signal and output at least one frequency calibration control signal to control at least one light source responsible for creating at least one of said plurality of laser light beams.
24. The frequency calibration system of claim 23, wherein the optical switch system comprises a K:1 switch configured to select one from among said K light beams and a 2:1 switch configured a select from among the reference light beam and said one from among said K light beams to thereby output said selected beam.
25. The frequency calibration system of claim 23, wherein the first selected 5 beam is delayed by one symbol period.
26. An iterative method for compensating for polarization mode dispersion (PMD) in an optical signal comprising:
(a) determining a candidate pair of rotation angles for adjusting a state of polarization of the optical signal;
(b) calculating at least one metric for said candidate pair of rotation angles
(c) storing the at least one metric and also outputting at least one PMD device control signal that is applied to a PMD compensator device into which the optical signal is input;
(d) repeating steps (a), (b) and (c) until metrics; for a predetermined set of candidate pairs have been calculated;
(e) finding the optimum metric and the optimum rotation angles corresponding to that metric; and
(f) outputting at least one PMD device control signal which corresponds to the optimum angles, to said PMD compensator device into which the optical signal is input.
27. The method according to claim 26, wherein the metric is an envelope stability metric.
28. The method according to claim 26, further comprising repeating steps (a)\u2013(f) until a predetermined condition is met, and wherein a step size for the candidate pairs of rotation angles is adjusted at each iteration of steps (a)\u2013(f).
29. A method for compensating for polarization mode dispersion (PMD) in an optical signal having two orthogonal polarizations, the method comprising:
(a) determining a candidate pair of rotation angles for adjusting a state of polarization of the optical signal;
(b) calculating at least one metric for said candidate pair of rotation angles;
(c) storing the metric;
(d) performing steps (a), (b) and (c) until metrics for a predetermined set of candidate pairs have been calculated;
(e) finding the optimum metric and the optimum rotation angles corresponding to that metric, and then updating a rotation matrix having coefficients derived from the optimum rotation angles;
(f) digitally compensating for PMD by applying the rotation matrix to digitized signals representing the information set on the two orthogonal polarizations.
30. The method according to claim 29, wherein the metric is an envelope stability metric.
31. The method according to claim 29, further comprising, before step (f), 20 repeating steps (a)\u2013(e) until a predetermined condition is met.
32. The method according to claim 31, further comprising adjusting a step size for the candidate pairs of rotation angles at each iteration of steps (a)\u2013(e).

1. A method of forming a capacitor, comprising:
forming a bottom electrode layer that includes tungsten;
forming a tungsten oxide buffer layer overlying the bottom electrode layer, including annealing the tungsten oxide buffer layer at a temperature of at least 700 degrees Celsius to form an orthorhombic crystal structure;
forming a dielectric layer directly on the tungsten oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
2. The method of claim 1, further comprising patterning the top electrode layer, the buffer layer, the dielectric layer, and the bottom electrode layer to define the capacitor.
3. The method of claim 1, wherein the method is performed in the order presented.
4. A method of forming a capacitor, comprising:
forming a bottom electrode layer, including tungsten, on a substrate;
oxidizing the bottom electrode layer to form a tungsten oxide buffer layer overlying the bottom electrode layer, and annealing the tungsten oxide buffer layer at a temperature of at least 700 degrees Celsius;
forming an orthorhombic crystal structure;
forming a dielectric layer directly on the tungsten oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
5. The method of claim 4, wherein the method is performed in the order presented.
6. A method of forming a capacitor, comprising:
forming a bottom electrode layer, which includes tungsten, on a substrate;
oxidizing the bottom electrode layer to form a tungsten oxide buffer layer overlying the bottom electrode layer;
annealing the tungsten oxide buffer layer at a temperature of about 750 degrees Celsius, wherein the annealing includes converting the tungsten oxide buffer layer to an orthorhombic crystal structure;
forming a dielectric layer directly on the tungsten oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
7. The method of claim 6, wherein the method is performed in the order presented.
8. The method of claim 7, wherein the bottom electrode is deposited by chemical vapor deposition, and the top electrode is deposited by chemical vapor deposition.
9. The method of claim 6, wherein the dielectric layer is formed to a thickness of about 80 \u212b.
10. A method of forming a capacitor, comprising:
forming a bottom electrode layer, which includes tungsten, on a substrate;
oxidizing the bottom electrode layer to form a metal oxide buffer layer overlying the bottom electrode layer;
annealing the buffer layer at about 700 degrees Celsius;
converting a monoclinic crystalline structure to an orthorhombic crystalline structure;
forming a dielectric layer directly on the metal oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
11. The method of claim 10, wherein the buffer layer is annealed for about one minute.
12. The method of claim 10, wherein the buffer layer is annealed in an N2 ambient.
13. A method of forming a capacitor, comprising:
forming a first electrode layer;
forming a second electrode layer, wherein at least one of the first electrode layer and the second electrode layer includes tungsten;
forming a dielectric layer interposed between the first electrode layer and the second electrode layer; and
forming a tungsten oxide buffer layer in direct contact with the dielectric layer and one of the first and second electrode layers, and annealing the tungsten oxide buffer layer at a temperature of at least 700 degrees Celsius and including forming an orthorhombic crystal lattice from a monoclinic crystal lattice.
14. The method of claim 13, wherein forming the tungsten oxide buffer layer includes oxidizing the one of the first and second electrode layers to form the tungsten oxide buffer layer before annealing the tungsten oxide buffer layer.
15. A method of forming a capacitor, comprising:
forming a bottom electrode layer;
forming an orthorhombic crystal structured buffer layer overlying the bottom electrode layer and wherein forming the orthorhombic crystal structured buffer layer includes annealing at a temperature greater than 700 degrees C;
forming a dielectric layer overlying the buffer layer; and
forming a top electrode layer overlying the dielectric layer.
16. The method of claim 15, further comprising patterning the top electrode layer, the buffer layer, the dielectric layer, and the bottom electrode layer to define the capacitor.
17. The method of claim 15, wherein the method is performed in the order presented.
18. A method of forming a capacitor, comprising:
forming a bottom electrode layer;
forming a metal oxide buffer layer overlying the bottom electrode layer;
annealing the metal oxide buffer layer at a temperature of at least 700 degrees C, wherein annealing includes forming at least a portion of an orthorhombic crystal structure;
forming a single compound, dielectric layer directly on the buffer layer, the dielectric layer having a dielectric constant less than a dielectric constant of the buffer layer; and
forming a top electrode layer overlying the dielectric layer.
19. The method of claim 18, further comprising patterning the top electrode layer, the buffer layer, the dielectric layer, and the bottom electrode layer to define the capacitor.
20. The method of claim 18, wherein the method is performed in the order presented.
21. A method of forming a capacitor, comprising:
forming a bottom electrode layer;
annealing the bottom electrode layer;
forming a metal oxide buffer layer overlying the bottom electrode layer;
annealing the buffer layer at a temperature of at least 700 degrees Celsius;
converting a monoclinic crystal lattice to an orthorhombic crystal structure;
forming a dielectric layer directly on the metal oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
22. The method of claim 21, further comprising patterning the top electrode layer, the buffer layer, the dielectric layer, and the bottom electrode layer to define the capacitor.
23. The method of claim 22, wherein the method is performed in the order presented.
24. A method of forming a capacitor, comprising:
forming a bottom electrode layer that includes tungsten;
forming a tungsten oxide buffer layer overlying the bottom electrode layer, wherein the forming includes placing the dielectric layer in an inert gas heated to at least 700 degrees Celsius, and wherein the tungsten oxide buffer layer includes at least a portion of a monoclinic crystal lattice;
converting the at least a portion of monoclinic crystal lattice to at least a portion of an orthorhombic crystal structure;
forming a dielectric layer directly on the tungsten oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer, wherein forming a dielectric layer includes depositing a Ta2O5 layer.
25. The method of claim 1, wherein forming the bottom electrode layer comprises forming a layer of tungsten nitride.
26. The method of claim 10, wherein forming the bottom electrode layer comprises forming a layer of tungsten nitride; and wherein oxidizing the bottom electrode layer includes forming a tungsten oxide layer.
27. The method of claim 26, wherein forming a dielectric layer includes depositing a Ta2O5 layer.
28. The method of claim 15, wherein forming a bottom electrode layer includes forming a tungsten nitride bottom electrode layer, and wherein forming a buffer layer includes oxidizing the tungsten nitride bottom electrode layer to form a tungsten trioxide buffer layer.
29. The method of claim 18, wherein forming a dielectric layer includes depositing a Ta2O5 layer, wherein forming a bottom electrode layer includes forming a tungsten nitride bottom electrode layer, and wherein forming a metal oxide buffer layer includes oxidizing the tungsten nitride bottom electrode layer to form a tungsten trioxide buffer layer.
30. A method of forming a capacitor, comprising:
forming a bottom electrode layer, the bottom electrode layer including a metal material;
forming a buffer layer directly contacting the bottom electrode layer, the buffer layer including a metal oxide material, and the buffer layer having orthorhombic crystal structure;
annealing the buffer layer at about 700 degrees Celsius, wherein annealing includes changing the crystal lattice from a monoclinic crystalline form to an orthorhombic crystalline form;
forming a dielectric layer directly contacting the buffer layer, and the dielectric layer having a dielectric constant less than a dielectric constant of the buffer layer; and
forming a top electrode layer directly contacting the dielectric layer.
31. A method of forming a capacitor, comprising:
forming a bottom electrode layer, the bottom electrode including tungsten;
forming a buffer layer directly contacting the bottom electrode layer, the buffer layer including tungsten oxide;
annealing the buffer layer in an N2 ambient at a temperature of at least 700 degrees Celsius;
changing a monoclinic crystalline structure to an orthorhombic crystalline form;
forming a dielectric layer directly contacting the buffer layer, and the dielectric layer having a dielectric constant less than a dielectric constant of the buffer layer; and
forming a top electrode layer directly contacting the dielectric layer.
32. The method of claim 1, wherein forming a tungsten oxide buffer layer includes forming a buffer layer having a leakage current less than 100\xd710\u221215 Amperes per capacitive cell.
33. The method of claim 1, wherein forming a tungsten oxide buffer layer includes forming a buffer layer having a capacitance greater than 7\xd710\u221215 Farads per capacitive cell.
34. The method of claim 1, wherein forming a bottom electrode includes forming a bottom electrode tat is about 5 times the thickness of the dielectric layer.
35. The method of claim 1, wherein forming a bottom electrode layer includes forming a bottom electrode comprising WNn with 0<n<=6.
36. The method of claim 1, wherein forming a bottom electrode layer includes forming a bottom electrode comprising W2N.
37. The method of claim 4, wherein forming an orthorhombic crystal structure includes forming an orthorhombic crystal structure having a leakage current less than 100\xd710\u221215 Amperes per capacitor.
38. The method of claim 36, wherein forming an orthorhombic crystal structure includes forming an orthorhombic crystal structure having a capacitance of at least 7\xd710\u221215 Farads per capacitor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A memory tag comprising a resonant circuit part and a non-volatile memory,
the resonant circuit part being operable, in response to a reader signal received from a reader, to provide power to the memory,
the tag being operable to read the memory and transmit data stored in the memory in response to the signal from the reader,
wherein the data is stored in the memory in a plurality of data units, each data unit having an associated sequence number,
the tag being operable to store the sequence number of the data unit to be transmitted in a register in the non-volatile memory,
when power is supplied to the memory, the data units are transmitted in a first incremental sequence, the first data unit to be transmitted depending on the stored sequence number, and
wherein, when power is initially supplied to the memory, the stored sequence number is decremented and thereafter the data units are transmitted in the first sequence until power is removed from the memory, such that at least one data unit that was previously transmitted is retransmitted.
2. A memory tag according to claim 1 operable to transmit the data unit in a packet comprising validity information.
3. A memory tag according to claim 2 wherein the validity information comprises cyclic redundancy check data.
4. A memory tag according to claim 2 wherein the packet further comprises the sequence number of the data unit.
5. A memory tag according to claim 1 operable to read the stored sequence number, read the data unit associated with the stored sequence number, transmit the data unit and increment the stored sequence number.
6. A method of operating a memory tag to transmit stored data, wherein the data comprises a plurality of data units each having an associated sequence number,
the method comprising the steps of
determining a first data unit to be transmitted in accordance with a stored sequence number and transmitting the data units in incremental sequence beginning with the first data unit; and
when power is removed and re-supplied to the memory tag, again determining a data unit by retrieving the stored sequence number and decrementing it.
7. A method according to claim 6 further comprising repeating the steps of;
reading a register,
reading the data unit associated with the stored sequence number and transmitting the data unit, and
incrementing the sequence number stored in the register.
8. A method according to claim 6 wherein the step of retrieving the stored sequence number and decrementing it comprises decrementing the sequence number stored in the register.
9. A method according to claim 8 comprising transmitting validation information with the data unit.
10. A memory tag comprising a resonant circuit part and a non-volatile memory,
the resonant circuit part being operable, in response to a reader signal received from a reader, to provide power to the memory,
the tag being operable to read the memory and transmit data stored in the memory in response to the signal from the reader,
wherein the data is stored in the memory in a plurality of data units, each data unit having an associated sequence number,
the memory tag being operable to store the sequence number of the data unit to be transmitted in a register in the non-volatile memory, and
when power is initially supplied to the memory, the memory tag is operable to;
decrementing the sequence number stored in a non-volatile memory of the memory tag to produce a changed sequence number, determine a first data unit to be transmitted in accordance with the changed sequence number, read the first data unit and transmit the first data unit,
and repeat steps of:
reading the stored sequence number,
reading the data unit associated with the stored sequence number and transmitting the data unit, and
incrementing the stored sequence number in the register.
11. A memory tag comprising a resonant circuit part and a non-volatile memory,
the resonant circuit part being operable, in response to a reader signal received from a reader, to provide power to the memory,
the tag being operable to read the memory and transmit data stored in the memory in response to the signal from the reader,
wherein the data is stored in the memory in a plurality of data units, each data unit having an associated sequence number,
the memory tag being operable to store the sequence number of the data unit to be transmitted in a register in the non-volatile memory, and
when power is supplied to the memory, the memory tag is operable to;
read a register stored in a non-volatile memory of the memory tag which stores a sequence number,
decrement the stored sequence number, read the data unit associated with the stored sequence number, transmit the data unit and increment the stored sequence number.
12. A memory tag according to claim 11 operable to repeat the steps of;
reading the register to read the stored sequence number,
reading the data unit associated with the stored sequence number and transmitting the data unit, and
incrementing the sequence number stored in the register.