Author: claimsbot

1. An injection device comprising
a housing (10) containing a cartridge (170) with an amount of liquid to be dispensed,
a drive sleeve (41), which is rotationally constrained to the housing (10) during dose setting and spring driven rotatable relative to the housing (10) during dose dispensing,
a dose dial member (60) for setting a dose to be dispensed, which is rotatable relative to the housing (10) during dose setting and during dose dispensing, and which is rotationally coupled to the drive sleeve (41) during dose dispensing,

wherein the device further comprises a last dose protection mechanism (41, 50, 60) for preventing the setting of a dose, which exceeds the amount of liquid left in a cartridge (170), with a limiter (50), which is interposed between the drive sleeve (41) and the dose dial member (60), and wherein the device further comprises at least one, preferably two different, display member(s) (110, 120), for indicating the set dose.
2. The injection device according to claim 1, wherein the housing (10) has a first aperture or window (12), and wherein the display members comprise a dose indicator (120), which is positioned within the housing (10) and rotatable relative to the housing (10) during dose setting and during dose dispensing, and a gauge element (110), which is interposed between the housing (10) and the dose indicator (120), and which is axially guided within the housing (10) and in threaded engagement with the dose indicator (120) such that rotation of the dose indicator (120) causes an axial displacement of the gauge element (110), with a second aperture (111) or window being provided in the gauge element (110), which is positioned with respect to the first aperture or window (12) of the housing (10) such that at least a part of the dose indicator (120) is visible through the first and second apertures or windows (12, 111).
3. The injection device according to claim 2, wherein the dose dial member (60) is permanently rotationally constrained to the dose indicator (120).
4. The injection device according to any of claim 2 or 3, wherein the dose indicator (120) is a number sleeve having a series of numbers or symbols arranged on a helical line on its outer surface, and wherein the gauge element (110) has a distal part located on the distal side of the second aperture (111) or window and a proximal part located on the proximal side of the second aperture (111) or window, with the distal part and the proximal part having a different outer surface.
5. The injection device according to any of the preceding claims, wherein the last dose protection mechanism comprises a nut member (50) as the limiter, which is rotationally constrained to the drive sleeve (41) and in threaded engagement with the dose dial member (60).
6. The injection device according to any of the preceding claims, wherein the limiter (50) comprises a rotational stop and the dose dial member (60) comprises a corresponding counter stop, which abut if a dose is set, which exceeds the amount of liquid left in a cartridge (170).
7. The injection device according to any of the preceding claims, further comprising a piston rod (30) coupled to the drive sleeve (41), which piston rod (30) is rotationally constrained to the housing (10) during dose setting and is allowed to rotate during dose dispensing.
8. The injection device according to any of the preceding claims, further comprising a ratchet clutch (130), which is arranged between the drive sleeve (41) and the dose dial member (60), and which allows relative rotation of the drive sleeve (41) and the dose dial member (60) during dose setting and which rotationally constrains the drive sleeve (41) to the dose dial member (60) during dose dispensing.
9. The injection device according to any of the preceding claims, wherein during dose dispensing the drive sleeve (41) is coupled to a torsion spring (90), which is strained during dose setting.
10. The injection device according to any of the preceding claims, comprising a limiter mechanism (121, 122) defining a maximum settable dose and a minimum settable dose.
11. The injection device according to any of the preceding claims, wherein the cartridge (170) is located on a first longitudinal axis (I), which is parallel to and spaced from the second longitudinal axis (II), on which the drive sleeve (41) and the dose dial member (60) are located.
12. The injection device according to claim 11, wherein the two different display members (110, 120) are located on the second longitudinal axis (II).
13. The injection device according to any of the preceding claims, wherein the length of the device before and after dose setting is the same.
14. The injection device according to any of the preceding claims, further comprising at least one first clicker (48, 131; 45, 102) producing an audible andor tactile first feedback during dose setting andor dose dispensing and a second clicker (123) producing an audible andor tactile second feedback, distinct from the first feedback, during dose dispensing when the device reaches its minimum dose (zero) position.
15. The injection device according to any of the preceding claims, wherein the cartridge (170) contains a medicament.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for the treatment of liquid comprising organic waste-based material, the method comprising:
continuously introducing the material at the upper part of a vertical mixing vessel,
subjecting the introduced material to mixing,
passing the mixed material on into a first reactor tank for acid treatment, wherein the first reactor tank has disposed therein a first row of rotary processing means,
subjecting the mixed material to an impact action via the first row of rotary processing means as the mixed material therein sinks through the first reactor tank,
passing the material from the first reactor tank on into a second reactor tank for ammonia treatment, the second reactor tank having disposed therein a second row of rotary processing means,
subjecting the material in the second reactor tank to an impact action via the second row of rotary processing means as the material therein sinks through the second reactor tank, and
subsequently drying the material in a drier until a desired solids content is achieved,
wherein the first row of rotary processing means comprises a first set of arm-rings, the second row of rotary processing means comprises a second set of arm-rings, or both rows comprise a set of arm-rings, and wherein at least one arm-ring of the first row of rotary processing means, at least one arm-ring of the second row of rotary processing means, or both moves counter-currently to at least one other arm-ring of that row of rotary processing means.
2. The method of claim 1, further comprising conducting exhaust steam, exhaust gas or both formed due to chemical reactions, mechanical treatment, or both, away from the mixing vessel, the first reactor tank, the second reactor tank, the drier, or a combination thereof to a collection point.
3. The method at claim 2, wherein the collection point comprises a condenser capable of transitioning the exhaust steam, the exhaust gas, or both to a liquid form.
4. The method of claim 1, wherein the drier comprises two cylinders arranged in parallel having several levels of counter-rotating rotors, and wherein drying comprises feeding hot air through the drier in counterflow to a material movement direction and putting the material in vibration by means of a vibrating motor.
5. The method of claim 1, further comprising feeding hot air through the mixing vessel, the first reactor tank, the second reactor tank, or a combination thereof in counterflow to the material movement direction therein.
6. The method of claim 1, further comprising putting the material in the mixing vessel, the first reactor tank, the second reactor tank, or a combination thereof in vibration.
7. The method of claim 1, wherein the desired solids content is in the range of 70-99%.
8. The method of claim 1, wherein acid treatment of the material in the first reactor tank further comprises reducing the pH of the material therein to a level between about 0.5 and 2, and increasing the temperature of the material therein to a temperature above about 70\xb0 C.
9. The method of claim 1, wherein ammonia treatment of the material in the second reactor tank further comprises increasing the pH of the material therein to a level of about 6 and increasing the temperature of the material therein to a temperature above about 90\xb0 C.
10. A system for the treatment of liquid comprising organic waste-based material by contact with chemicals selected from sulphuric acid, nitric acid, ammonia, and combinations thereof and vaporization and degasification of liquid from the material to increase the solids content thereof, the system comprising:
a vertical mixing vessel configured to mix the material,
a first reactor tank configured for acid treatment, wherein the first reactor tank has disposed therein a first row of rotary processing means,
a second reactor tank configured for ammonia treatment, wherein the second reactor tank has disposed therein a second row of rotary processing means, and
a drier configured for drying a material introduced therein to a desired solids content,
wherein the first row of rotary processing means comprises a first set of arm-rings, the second row of rotary processing means comprises a second set of arm-rings, or both rows comprise a set of arm-rings, and wherein at least one arm-ring of the first row of rotary processing means, at least one arm-ring of the second row of rotary processing means, or both moves counter-currently to at least one other arm-ring of that row of rotary processing means.
11. The system of claim 10, further comprising at least one duct configured to carry exhaust steam, exhaust gas, or both formed due to chemical reactions or mechanical treatment away from the mixing vessel, the first reactor tank, the second reactor tank, the drier, or a combination thereof, to a collection point.
12. The system of claim 11, further comprising a condenser fluidly connected with the at least one duct and configured to transform the exhaust steam, the exhaust gas, or both to a liquid form.
13. The system of claim 10, wherein the drier comprises two cylinders arranged in parallel having several levels of counter-rotating rotors and a vibrating motor configured to impart vibrations to a material therein, and wherein the drier is provided with means for flowing hot air in counterflow to a material movement direction within the drier during operation.
14. The system of claim 10, further comprising means for flowing hot air in counterflow direction to a material movement direction in the mixing vessel, the first reactor tank, the second reactor tank, or a combination thereof, during operation.
15. The system of claim 10, further comprising at least one vibrating means coupled with the mixing vessel, the first reactor tank, the second reactor tank, or a combination thereof.
16. The system of claim 10, wherein the drier is configured to dry a material therein to a solids content in the range of 70-99%.
17. The system of claim 16 wherein the drier is configured to dry a material therein to a solids content in the range of 85-90%.
18. The method of claim 1 wherein the liquid comprising organic waste-based material comprises sludge from a sewage disposal plant.
19. The method of claim 1 wherein acid treatment comprises sulphuric acid treatment, nitric acid treatment, or both.
20. The method of claim 7 wherein the desired solids content is in the range of 85-90%.

1. A method for forming RF devices, said method comprising:
providing a substrate;
forming RF devices using an RF metal level that is an uppermost metal level in an integrated circuit device;
forming a passivation layer over said RF metal level;
forming openings in said passivation layer to provide direct access to individual ones of said RF devices; and
forming electrical connections through at least some of said openings to individually and directly couple at least some of said RF devices to a further device formed on a further substrate.
2. The method as in claim 1, wherein said RF devices comprise inductors and said forming openings comprises choosing an inductance value and forming electrical connection to a plurality of said inductors that collectively provide said desired inductance value.
3. The method as in claim 1, wherein said RF devices comprise capacitors and inductors and said forming electrical connections comprises choosing at least one of a capacitance value and an inductance value and coupling said further device to at least one of a plurality of said capacitors and a plurality of said inductors that collectively provide said at least one of a capacitance value and an inductance value.
4. The method as in claim 1, wherein said RF devices are further coupled to other devices formed within said integrated circuit device, through said openings.
5. The method as in claim 1, wherein
said forming RF devices includes depositing and patterning said RF metal level to include connective lines that couple together said RF devices to form a RF device network,
said forming openings includes forming openings to expose relatively thin connective lines of said connective lines, and
further comprising selectively altering said RF metal level by cutting a line in at least one of said relatively thin connective lines using a laser directed through at least one of said openings.
6. The method as in claim 1, wherein said forming RF devices comprises:
depositing and patterning an upper metal level over said substrate wherein said upper metal level comprises lower portions of said RF devices;
forming an insulating material over said upper metal level;
patterning said insulating material to selectively expose said lower portions of said RF devices; and
depositing and patterning said RF metal level overlying said insulating material and said upper metal level thereby completing said RF devices,
and wherein said passivation layer is further formed over said insulating material and said top metal level and said further device is coupled to said RF metal level.
7. The method as in claim 1, wherein said forming electrical connections comprises wire bonding.
8. The method as in claim 1, wherein said forming openings comprises forming openings that expose contact portions of said individual ones of said RF devices.
9. The method as in claim 1, further comprising providing a package that includes said integrated circuit device and said further device in said package.
10. A method for forming RF devices in the manufacture of an integrated circuit device, said method comprising:
providing a substrate;
forming RF devices using an RF metal level that is an uppermost metal level in said integrated circuit device, said RF metal level including connective lines that couple together at least some of said RF devices;
forming a passivation layer over said RF metal level;
forming openings in said passivation layer to expose relatively thin connective lines of said connective lines, and
selectively altering said RF metal level by cutting at least one of said relatively thin connective lines using a laser directed through at least one of said openings.
11. The method as in claim 10, wherein said forming RF devices comprises:
depositing and patterning an upper metal level over said substrate wherein said upper metal level comprises lower portions of said RF devices;
forming an insulating material over said upper metal level;
patterning said insulating material to selectively expose said lower portions of said RF devices; and
depositing and patterning said RF metal level overlying said insulating material and said upper metal level thereby completing said RF devices, wherein said RF devices include capacitors and inductors.
12. The method as in claim 11, wherein said openings further provide access to individual ones of said RF devices and further comprising providing a further circuit on a further substrate and directly connecting said further circuit to at least some of said RF devices through said openings.
13. The method as in claim 12, wherein said RF devices include capacitors and inductors and said selectively altering comprises connecting said further circuit to a selected plurality of said RF devices to provide at least one of a desired capacitance and a desired inductance.
14. A semiconductor device comprising an integrated circuit device comprising:
a patterned upper metal level overlying a substrate wherein said upper metal level comprises bottom plates for capacitors and terminals for inductors;
a dielectric layer overlying said upper level metal;
a patterned RF metal level overlying said upper level metal and said dielectric layer, wherein said RF metal level comprises top plates for said capacitors overlying said bottom plates with said dielectric layer therebetween and wherein said RF metal level further comprises inductive lines for said inductors, at least some of said capacitors and inductors coupled together to form an RF network; and
a passivation layer overlying said RF metal level and including a plurality of openings therethrough, said openings exposing individual ones of said capacitors and inductors to provide direct access to said individual ones of said capacitors and inductors through said openings.
15. The semiconductor device as in claim 14, wherein at least some of said RF devices are directly coupled to a further semiconductor device through said openings.
16. The semiconductor device as in claim 15, wherein said at least some of said RF devices are coupled via wire bonding.
17. The semiconductor device as in claim 15, further comprising a package and wherein said further semiconductor device is disposed on a further substrate contained within said package.
18. The semiconductor device as in claim 15, wherein said further semiconductor device comprises:
a patterned top metal level overlying said substrate wherein said top metal level comprises further bottom plates for further capacitors and further terminals for further inductors;
a further dielectric layer overlying said top level metal; and
a patterned further RF metal level overlying said top level metal, wherein said further RF metal level comprises further top plates for said further capacitors overlying said further bottom plates with said dielectric layer therebetween and wherein said further RF metal level further comprises inductive lines for said further inductors, at least some of said further capacitors and further inductors coupled together to form a further RF network.
19. The semiconductor device as in claim 14, wherein said at least some of said capacitors and inductors are coupled by connective lines including relatively narrow conductive lines and relatively wide conductive lines and wherein said openings extending through said passivation level expose at least some of said relatively narrow conductive lines.
20. The semiconductor device as in claim 19, wherein said relatively narrow conductive lines link said relatively wide conductive lines to form a metal lead, said relatively narrow conductive lines having a width no greater than 20% of a width of said relatively wide conductive lines.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of instruction cache (I-cache) management, comprising:
maintaining a different substantially random instruction mapping policy into an I-cache for each of multiple processes; and
for each process, performing a substantially random mapping scheme for mapping a process instruction into the I-cache based on the substantially random instruction mapping policy for said process.
2. The method of claim 1, wherein said multiple processes include security critical process instructions, such that maintaining a different substantially random instruction mapping policy into an I-cache for each of multiple processes includes maintaining a different substantially random instruction mapping policy into the I-cache for each of multiple security critical processes.
3. The method of claim 2, wherein performing a substantially random mapping scheme further includes detecting execution of security critical processes on one or more processors, and upon receiving an instruction from a security critical process, performing a substantially random mapping scheme for mapping the instruction into the I-cache according to the substantially random instruction mapping policy for the security critical process.
4. The method of claim 1, wherein performing a substantially random I-cache mapping policy includes substantially randomizing an index portion of each virtual I-cache address.
5. The method of claim 1 further comprising:
partitioning an I-cache into multiple logical partitions; and
sharing access to the I-cache by an I-cache mapping policy that provides access to each I-cache partition by only one logical processor.
6. The method of claim 4, wherein partitioning the I-cache further includes partitioning the I-cache into multiple logical partitions corresponding to multiple logical processors.
7. The method of claim 6, wherein providing access to each I-cache partition further includes providing access to each I-cache partition only by a corresponding logical processor.
8. The method of claim 7 further including the step: upon detecting execution of a critical process instruction on a logical processor, preventing access to a corresponding I-cache partition by other logical processors.
9. The method of claim 8, wherein preventing access to the I-cache partition by said other logical processors includes dynamically repartitioning the I-cache to only allow access to the corresponding I-cache partition by the processor executing the critical process.
10. The method of claim 1, wherein:
partitioning the I-cache includes dynamically modifying the mapping index of the I-cache to include a logical processor identification; and
sharing access to the I-cache includes allowing access to different partitions of the I-cache by an I-cache mapping policy based on the logical processor identification.
11. The method of claim 10 further including implementing a substantially random I-cache mapping policy for each cache partition.
12. The method of claim 11, wherein a substantially random I-cache mapping policy for each cache partition includes substantially randomizing the index section of each virtual I-cache address.
13. The method of claim 12, wherein substantially randomizing the index section of each virtual I-cache address includes XORing the address with a substantially random value.
14. The method of claim 12 further including obtaining a different substantially random value for each active process running on a logical processor, for substantially randomizing the I-cache mapping policy for the I-cache partitions.
15. The method of claim 1, wherein the instruction processing is implemented on a simultaneous multithreading (SMT) processor.
16. The method of claim 1, wherein performing a substantially random I-cache mapping policy includes substantially randomizing an index portion of each virtual I-cache address by:
generating a substantially random value from a seed value;
blending the basic I-cache index with the substantially random value to generate a substantially random I-cache index; and
using the substantially random I-cache index for the I-cache instruction mapping.
17. The method of claim 16, wherein generating a substantially random value from a seed includes consecutively computing hash values from an initial seed for each different I-cache access and selecting a set of bits of the hash value to generate a substantially random number.
18. An instruction cache system, comprising:
an instruction cache; and
a cache manager configured for maintaining a different substantially random instruction mapping policy into an I-cache for each of multiple processes, and for each process, performing a substantially random mapping scheme for mapping a process instruction into the I-cache based on the substantially random instruction mapping policy for said process.
19. The system of claim 18, wherein said multiple processes include security critical process instructions, such that the cache manager is configured for maintaining a different substantially random instruction mapping policy into the I-cache for each of multiple security critical processes.
20. The system of claim 19, wherein the cache manager is further configured for detecting execution of security critical processes on one or more processors, and upon receiving an instruction from a security critical process, performing a substantially random mapping scheme for mapping the instruction into the I-cache according to the substantially random instruction mapping policy for the security critical process.
21. The system of claim 18, wherein the cache manager is further configured for substantially randomizing an index portion of each virtual I-cache address.
22. The system of claim 18, wherein the cache manager is further configured for partitioning an I-cache into multiple logical partitions, and providing access to the I-cache by an I-cache mapping policy that provides access to each I-cache partition by only one logical processor.
23. The system of claim 21, wherein the cache manager is configured for partitioning the I-cache into multiple logical partitions corresponding to multiple logical processors.
24. The system of claim 23, wherein the cache manager is configured for providing access to each I-cache partition only by a corresponding logical processor.
25. The system of claim 24, wherein the cache manager is configured for detecting execution of a critical process instruction on a processor, and preventing access to a corresponding I-cache partition by other processes.
26. The system of claim 25, wherein the cache manager is configured for dynamically repartitioning the I-cache to only allow access to the corresponding I-cache partition by the processor executing the critical process.
27. The system of claim 18, wherein the cache manager is further configured for partitioning the I-cache by dynamically modifying the mapping index of the I-cache to include logical processor identification, and allowing access to different partitions of the I-cache by an I-cache mapping policy based on logical processor identification.
28. The system of claim 27, wherein the cache manager is configured for implementing a substantially random I-cache mapping policy for each cache partition.
29. The system of claim 28, wherein the cache manager is further configured for a substantially random I-cache mapping policy for each cache partition by substantially randomizing the index section of each virtual I-cache address.
30. The system of claim 29, wherein the cache manager is further configured for substantially randomizing the index section of each virtual I-cache address by XORing the address with a substantially random value.
31. The system of claim 29, wherein the cache manager is further configured for obtaining a different substantially random value for each active process running on a logical processor, for substantially randomizing the I-cache mapping policy for the I-cache partitions.