Author: claimsbot

1. An anode plate of a field emission display comprising:
a transparent piece of the field emission display; and
a plurality of phosphor lines formed on the transparent piece, wherein the plurality of phosphor lines are to be aligned with and receive electrons from a plurality of emitter lines of a cathode substrate of the field emission display.
2. The anode plate of claim 1 further comprising an anode material formed to contact the plurality of phosphor lines, wherein a potential applied to the anode material accelerates the electrons from the plurality of emitter lines.
3. A method of providing a field emission display comprising:
providing a cathode substrate including a plurality of emitter lines formed on the cathode substrate;
providing a gate frame positioned over the cathode substrate, the gate frame including a plurality of gate wires; and
providing an anode plate including a plurality of phosphor lines positioned over the gate frame, the plurality of phosphor lines aligned with the plurality of emitter lines.
4. A method of making a field emission display comprising:
providing a cathode substrate;
depositing a plurality of emitter lines on the cathode substrate;
providing a gate frame including a plurality of gate wires; and
positioning the gate frame over the cathode substrate.
5. The method of claim 4 further comprising:
providing an anode plate;
depositing a plurality of phosphor lines on a surface of the anode plate; and
positioning the anode plate over the gate frame, the plurality of phosphor lines aligned with the plurality of emitter lines.
6. The method of claim 5 further comprising:
sealing the cathode substrate, the gate frame and the anode plate together.
7. The method of claim 5 further comprising:
sealing a volume formed between the cathode substrate and the anode plate in a vacuum.
8. The method of claim 4 wherein the positioning the gate frame comprises:
positioning the gate frame over the cathode substrate such that the gate wires cross over the plurality of emitter lines.
9. The method of claim 4 further comprising:
forming a plurality of linear isolation barriers on the cathode substrate, wherein the plurality of linear isolation barriers separate emitter lines from each other.
10. The method of claim 9 wherein the positioning the gate frame step comprises:
positioning the gate frame over the cathode substrate such that the linear isolation barriers contact the gate wires and dampen vibrations in the gate wires from a driving frequency.
11. The method of claim 9 wherein the forming the plurality of linear isolation barriers comprises:
forming the plurality of linear isolation barriers on the cathode substrate such that each emitter line is positioned between a respective pair of linear isolation barriers.
12. The method of claim 4 further comprising:
forming a plurality of in-laid isolation barriers within a depth of a top surface of the cathode substrate, wherein each emitter line is formed within a respective in-laid isolation barrier.
13. The method of claim 12 wherein positioning the gate frame step comprises:
positioning the gate frame over the cathode substrate such that portions of the top surface of the cathode substrate in between the in-laid linear isolation barriers contact portions of the gate wires of the gate frame and dampen vibrations in the gate wires from a driving frequency.
14. The method of claim 4 further comprising:
coupling a first alignment barrier to the cathode substrate for aligning the gate frame on the cathode substrate while positioning the gate frame.
15. The method of claim 5 further comprising:
coupling a second alignment barrier to the gate frame for aligning the anode plate on the gate frame while positioning the anode plate.
16. The method of claim 4 wherein the depositing the plurality of emitter lines comprises:
depositing the plurality of emitter lines such that each emitter line comprises a substantially smooth layer of electron emitting material on the cathode substrate.
17. The method of claim 4 wherein the depositing the plurality of emitter lines comprises:
depositing the plurality of emitter lines such that each emitter line comprises a plurality of conical emitters deposited closely together in a linear fashion on the cathode substrate.
18. The method of claim 4 wherein the depositing the plurality of emitter lines comprises:
depositing the plurality of emitter lines such that each emitter line comprises a plurality of emitter portions deposited on a surface of the cathode substrate, wherein there is no separating structure positioned in between adjacent emitter portions on the surface of the cathode substrate.
19. The method of claim 4 wherein the depositing the plurality of emitter lines comprises:
depositing the plurality of emitter lines such that each emitter line comprises a continuous line of deposited emitter material extending across the cathode substrate.
20. A method of operating a field emission display comprising:
applying a first voltage potential between an emitter line of a cathode substrate and one or more gate wires of a gate frame positioned over the cathode substrate;
generating an electric field over a portion of the emitter line below and in between the one or more gate wires; and
emitting electrons from the portion of the emitter line.
21. The method of claim 20 further comprising:
applying a second voltage potential to an anode plate including a plurality of phosphor lines;
whereby accelerating the electrons emitted toward a phosphor line.
22. The method of claim 20 wherein the one or more gate wires cross over the emitter line.
23. The method of claim 20 further comprising:
isolating the electrons emitted from adjacent emitter lines formed on the cathode substrate.
24. The method of claim 20 further comprising:
contacting the one or more gate wires to dampen vibrations in the gate wires from a driving frequency.
25. The method of claim 20 wherein the emitter line is located between a pair of linear isolation barriers.
26. The method of claim 20 wherein the emitter line is located within an in-laid isolation barrier of the cathode substrate.
27. The method of claim 20 wherein the emitter line comprises a substantially smooth layer of electron emitting material on the cathode substrate.
28. The method of claim 20 wherein the emitter line comprises a plurality of conical emitters deposited closely together in a linear fashion on the cathode substrate.
29. The method of claim 20 wherein the emitter line comprises a plurality of emitter portions deposited on a surface of the cathode substrate, wherein there is no separating structure positioned in between adjacent emitter portions on the surface of the cathode substrate.
30. The method of claim 20 wherein the emitter line comprises a continuous line of deposited emitter material extending across the cathode substrate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A power converter comprising a controller and at least one output terminal for providing an output voltage and an output current to a load, the controller configured for monitoring the output voltage and the output current and calculating an efficiency of the power converter based on the monitored output voltage and output current, the controller configured for generating a fault signal after detecting a degradation in the power converter efficiency.
2. The power converter of claim 1 wherein the controller is configured for comparing the calculated efficiency with stored data to detect the degradation.
3. The power converter of claim 2 wherein the controller is configured for generating the fault signal when the degradation exceeds a threshold level.
4. The power converter of claim 2 wherein the stored data includes a plurality of values each corresponding to a particular operating condition of the power converter.
5. The power converter of claim 4 further comprising a look-up table storing the plurality of values.
6. The power converter of claim 5 further comprising at least one input terminal for receiving an input voltage and an input current, wherein the controller is configured to monitor the input voltage and the input current, and to calculate an efficiency of the power converter based on the monitored input voltage, input current, output voltage and output current.
7. The power converter of claim 6 wherein the controller is configured for providing the fault signal to a system hosting the power converter.
8. The power converter of 7 wherein the controller is configured for shutting down the power converter in response to a command from the system hosting the power converter.
9. The power converter of claim 1 wherein the controller is configured for providing the fault signal to a system hosting the power converter.
10. The power converter of 9 wherein the controller is configured for shutting down the power converter in response to a command from the system hosting the power converter.
11. The power converter of claim 1 wherein the controller is configured for shutting down the power converter after generating the fault signal.
12. A method of predicting faults in a power converter, the method comprising:
monitoring an output voltage and an output current of the power converter;
calculating an efficiency of the power converter based on the monitored output voltage and output current; and
generating a fault signal after detecting a degradation in the power converter efficiency.
13. The method of claim 12 further comprising repairing or replacing the power converter in response to the fault signal.
14. The method of claim 12 wherein generating includes generating the fault signal when the degradation exceeds a threshold level.
15. The method of claim 14 wherein monitoring includes monitoring an input voltage and an input current of the power converter, and wherein calculating includes calculating an efficiency of the power converter based on the monitored input voltage, input current, output voltage and output current.
16. The method of claim 15 further comprising comparing the calculated efficiency with stored data.
17. The method of claim 16 wherein the stored data includes a plurality of values each corresponding to a particular operating condition of the power converter.
18. The method of claim 17 wherein the plurality of values are stored in a look-up table.

1. An optical device comprising:
a substrate; and
a photonic crystal optical interconnect comprising:
a first cladding layer over the substrate;
a photonic crystal layer over the first cladding layer, the photonic crystal layer comprising at least one photonic crystal element comprising a plurality of pillars being spaced apart from each other; and
a second cladding layer over the photonic crystal layer, wherein the pillars do not extend into the second cladding layer,
wherein the photonic crystal element comprises a first region having a first photonic crystal structure, a second region having a second different photonic crystal structure, and a third region having a third photonic crystal structure different from that of the first region and the second region, wherein the difference in photonic crystal structure among the three regions is based on a difference in pillar characteristics including at least a difference in pillar shape or size, said photonic crystal element forming a wavelength filter for the interconnect.
2. The optical device of claim 1, wherein the photonic crystal optical interconnect is configured for transmitting electromagnetic radiation.
3. The optical device of claim 2, wherein the photonic crystal optical interconnect has a photonic crystal structure configured such that optical response correlation length is larger than a diameter of an electromagnetic radiation beam incident on the photonic crystal optical interconnect.
4. The optical device of claim 3, wherein the optical interconnect has a photonic crystal structure configured to permit the transmission of a soliton.
5. The optical device of claim 1, further comprising a second photonic crystal element which is a photonic crystal lens associated with the optical interconnect and is configured to focus electromagnetic radiation onto the optical interconnect.
6. The optical device of claim 5, where the photonic crystal lens is a flat lens.
7. The optical device of claim 5, where the photonic crystal lens is configured to have a negative index of refraction.
8. The optical device of claim 1, further comprising a second photonic crystal element which is a photonic crystal filter associated with the optical interconnect and is configured to pass predetermined electromagnetic wavelengths to reach the optical interconnect.
9. The optical device of claim 1, wherein the photonic crystal element further comprises a material within the spacing between the pillars, the material having a dielectric constant that is lower than a dielectric constant of the pillars.
10. The optical device of claim 1, wherein the pillars comprise aluminum oxide.
11. The optical device of claim 1, wherein the photonic crystal element further comprises a third region having a third photonic crystal structure different from the photonic crystal structure of the first and second regions.
12. An integrated circuit comprising:
a substrate;
a first circuit on the substrate;
a second circuit on the substrate; and
a photonic crystal optical interconnect comprising:
a first cladding layer over the substrate;
a photonic crystal layer over the first cladding layer, the photonic crystal layer comprising at least one photonic crystal element for affecting the transmission of electromagnetic radiation from the first circuit to the second circuit, the photonic crystal element comprising a plurality of pillars being spaced apart from each other; and
a second cladding layer over the photonic crystal layer, wherein the pillars do not extend into the second cladding layer,
wherein the photonic crystal element comprises a first region having a first photonic crystal structure, a second region having a second different photonic crystal structure, and a third region having a third photonic crystal structure different from that of the first region and the second region, wherein the difference in photonic crystal structure among the three regions is based on a difference in pillar characteristics including at least a difference in pillar shape or size, said photonic crystal element forming a wavelength filter for the interconnect.
13. The integrated circuit of claim 12, wherein the photonic crystal element further comprises a material within the spacing between the pillars, the material having a dielectric constant that is lower than a dielectric constant of the pillars.
14. The integrated circuit of claim 12, wherein the pillars comprise aluminum oxide.
15. The integrated circuit of claim 12, further comprising a second photonic crystal element which is a photonic crystal lens.
16. The integrated circuit of claim 12, further comprising a second photonic crystal element which is a photonic crystal filter.
17. The integrated circuit of claim 12, wherein the photonic crystal element further comprises a third region having a third photonic crystal structure different from the photonic crystal structure of the first and second regions.
18. A processor-based system comprising:
a processor; and
a circuit coupled to the processor, the circuit comprising:
a substrate; and
a photonic crystal optical interconnect comprising:
a first cladding layer over the substrate;
a photonic crystal layer over the first cladding layer, the photonic crystal layer comprising at least one photonic crystal element comprising a plurality of pillars being spaced apart from each other; and
a second cladding layer over the photonic crystal layer, wherein the pillars do not extend into the second cladding layer,
wherein the photonic crystal element comprises a first region having a first photonic crystal structure, a second region having a second different photonic crystal structure, and a third region having a third photonic crystal structure different from that of the first region and the second region, wherein the difference in photonic crystal structure among the three regions is based on a difference in pillar characteristics including at least a difference in pillar shape or size, said photonic crystal element forming a wavelength filter for the interconnect.
19. The system of claim 18, wherein the photonic crystal element further comprises a third region having a third photonic crystal structure different from the photonic crystal structure of the first and second regions.
20. A photonic crystal optical element for a circuit, the optical element comprising:
a substrate; and
a photonic crystal optical interconnect comprising:
a first cladding layer over the substrate;
a photonic crystal layer over the first cladding layer, the photonic crystal layer comprising at least one photonic crystal element comprising a plurality of pillars being spaced apart from each other;
a second cladding layer over the photonic crystal layer, wherein the pillars do not extend into the second cladding layer; and
a low dielectric constant material within the spacing between the pillars having a dielectric constant that is lower than a dielectric constant of the pillars,
wherein the photonic crystal element comprises a first region having a first photonic crystal structure, a second region having a second different photonic crystal structure, and a third region having a third photonic crystal structure different from that of the first region and the second region, wherein the difference in photonic crystal structure among the three regions is based on a difference in pillar characteristics including at least a difference in pillar shape or size, said photonic crystal element forming a wavelength filter for the interconnect.
21. The photonic crystal optical element of claim 20, wherein the pillars and low dielectric constant material together have an approximately flat top surface.
22. The photonic crystal optical element of claim 20, wherein the pillars have a height within the range of approximately 100 \u212b to approximately 5000 \u212b.
23. The photonic crystal optical element of claim 20, wherein a ratio of the spacing between the pillars to a height of the pillars is within the range of approximately 1 to approximately 10.
24. The photonic crystal optical element of claim 20, wherein at least one of the photonic crystal structures has at least one defect.
25. The photonic crystal optical element of claim 20, wherein the pillars each of at least one of the regions have a circular horizontal cross-sectional shape.
26. The photonic crystal optical element of claim 20, wherein the pillars of at least one of the regions have a pentagonal horizontal cross-sectional shape.
27. The photonic crystal optical element of claim 20, wherein the pillars of at least one of the regions have a rectangular horizontal cross-sectional shape.
28. The photonic crystal optical element of claim 20, wherein the pillars comprise aluminum oxide.
29. The photonic crystal optical element of claim 20, wherein the pillars comprise zirconium oxide.
30. The photonic crystal optical element of claim 20, wherein the pillars comprise hafnium oxide.
31. The photonic crystal optical element of claim 20, wherein the pillars comprise a silver halide.
32. The photonic crystal optical element of claim 20, wherein the pillars comprise a polymer material based on high density polyethylene.
33. The photonic crystal optical element of claim 20, wherein the low dielectric constant material is spun on glass.
34. The photonic crystal optical element of claim 20, wherein the low dielectric constant material is silicon dioxide.
35. The photonic crystal optical element of claim 20, wherein the photonic crystal element is configured to transmit electromagnetic radiation.
36. The photonic crystal optical element of claim 20, wherein the photonic crystal element is configured to transmit solitons.
37. The photonic crystal optical element of claim 20, wherein the photonic crystal element is configured to focus electromagnetic radiation.
38. The photonic crystal optical element of claim 20, wherein the photonic crystal element is configured to pass predetermined wavelengths of electromagnetic radiation.
39. The optical element of claim 20, wherein the photonic crystal element further comprises a third region having a third photonic crystal structure different from the photonic crystal structure of the first and second regions.
40. A method of forming a photonic crystal element for a circuit, the method comprising:
providing a substrate;
providing a first cladding layer over the substrate;
forming a layer of a photonic crystal material over the first cladding layer;
patterning the photonic crystal material layer to form a plurality of pillars, wherein pillars in a first region have a first photonic crystal structure, pillars in a second region have a second different photonic crystal structure, and pillars in a third region have a third photonic crystal structure different from that of the pillars in the first region and the second region, wherein the difference in photonic crystal structure is based on a difference in pillar characteristics including at least a difference in pillar size or shape, said photonic crystal element forming a wavelength filter;
placing a low dielectric constant material having a lower dielectric constant than a dielectric constant of the pillars within the spacing between the pillars; and
providing a second cladding layer over the photonic crystal material and the low dielectric constant material, wherein the pillars do not extend into the second cladding layer.
41. The method of claim 40, wherein the act of forming a layer of a photonic crystal material comprises forming the photonic crystal material layer having a thickness within a range of approximately 100 \u212b to approximately 5000 \u212b.
42. The method of claim 40, wherein the act of patterning the photonic crystal material layer comprises forming at least one defect in the photonic crystal structure.
43. The method of claim 40, wherein the act of patterning the photonic crystal material layer comprises forming the pillars such that a ratio of the spacing between the pillars to the height of the pillars is within the range of approximately 1 to approximately 10.
44. The method of claim 40, wherein the act of patterning the photonic crystal material layer comprises forming the pillars of at least one of the regions with a circular horizontal cross-sectional shape.
45. The method of claim 40, wherein the act of patterning the photonic crystal material layer comprises forming the pillars of at least one of the regions with a rectangular horizontal cross-sectional shape.
46. The method of claim 40, wherein the act of patterning the photonic crystal material layer comprises forming the pillars of at least one of the regions with a pentagonal horizontal cross-sectional shape.
47. The method of claim 40, wherein the act of forming the layer of a photonic crystal material comprises forming a layer of aluminum oxide.
48. The method of claim 40, wherein the act of forming the layer of a photonic crystal material comprises forming a layer of polymer material based on high density polyethylene.
49. The method of claim 40, wherein the act of forming the layer of a photonic crystal material comprises forming a layer of zirconium oxide.
50. The method of claim 40, wherein the act of forming the layer of a photonic crystal material comprises forming a layer of hafnium oxide.
51. The method of claim 40, wherein the act of forming the layer of a photonic crystal material comprises forming a layer of a silver halide.
52. The method of claim 40, wherein the act of placing the low dielectric constant material comprises depositing spun on glass.
53. The method of claim 40, wherein the act of placing the low dielectric constant material comprises depositing silicon dioxide.
54. The method of claim 40, wherein the act of patterning the photonic crystal material layer comprises forming the photonic crystal structure to transmit electromagnetic radiation.
55. The method of claim 40, wherein the act of patterning the photonic crystal material layer comprises forming the photonic crystal structure to transmit solitons.
56. The method of claim 40, wherein the photonic crystal structures are formed to focus electromagnetic radiation.
57. The method of claim 40, wherein the photonic crystal structures are formed to pass predetermined wavelengths of electromagnetic radiation.
58. The method of claim 40, wherein the patterning of the photonic crystal material layer further comprises forming pillars in a third region having a third photonic crystal structure different from the photonic crystal structures of the first and second regions.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1.-8. (canceled)
9. A method for creating a micropolarizer, comprising:
providing a first film comprising a linear polarizer film having a first and a second surface;
providing a second film comprising a stretched PVA;
cleaning said linear polarizer film with 2-propanol within an ultrasonic tank;
buffing said linear polarizer film with a felt roller;
cleaning said stretched PVA film with 2-propanol within an ultrasonic tank;
spraying spacers on a first surface of said PVA film;
making a cell with said sheet of PVA film and said sheet of said linear polarizer film in such a way that a stretching direction of said PVA film is orthogonal to a rubbing direction of said linear polarizing film;
covering said cell with a micropolarizer pattern mask;
ensuring a direction of horizontal rows is oriented 45\xb0 with respect to said stretching direction and rubbing directions;
placing said cell and said mask into a pressing machine to make said cell and said mask closed completely;
controlling a thickness of said cell;
polymerizing the TNLC under the transparent area with UV light into a permanent TN texture,
removing said mask;
heating the cell higher than a nematic-isotropic transition temperature so that unpolymerized LC covered by opaque strips of said mask experience a transition into an isotropic phase;
using UV light to polymerize uncured LC material at isotropic phase.
10. The method of claim 9, wherein said mask has alternate transparent and opaque strips covering said cell or film whereby a solidfying energy is being selectively applied there through; and partially solidifying some portions said liquid crystal.
11. The method of claim 9 wherein a density of said spaces is 50 to 200 sq. mm.
12. The method of claim 9 wherein said spacers have a diameter range of 5 to 20 \u03bcm.
13. The method of claim 9 comprising using a roller machine to laminate said LC between said two sheets as an alternative to filling in said polymerizable twisted nematic.
14. The method of claim 9, wherein said liquid crystal comprises a nematic liquid crystal.
15. The method of claim 14, wherein said nematic liquid crystal comprises a type of polynerizable nematic liquid crystal.
16.-23. (canceled)
24. A liquid crystal display device, comprising:
an input surface for receiving incident light;
an output surface for emanating a processed light; and
a micropolarizer based on twisted nematic liquid crystals produced by a method comprising a liquid crystal display device produced by the method described substantially by claims 9-15.
25. A liquid crystal display device, comprising:
an input surface for receiving said incident light;
an output surface for emanating a processed light; and
a micropolarizer based on twisted nematic liquid crystals produced by a method comprising a liquid crystal display device produced by the method described substantially by claims 9.
26. (canceled)