Author: claimsbot

1. A semiconductor integrated circuit device comprising:
a first active region on a surface of a substrate, wherein the first active region has a length in a first direction;
a second active region on the surface of the substrate, wherein the second active region has a length in the first direction, wherein the length of the second active region is greater than the length of the first active region, and wherein an axis in a second direction intersects centers of the first and second active regions so that the first and second active regions are symmetric about the axis in the second direction;
a first gate electrode that extends across the first active region in the first direction; and
a second gate electrode that extends across the second active region in the first direction.
2. The semiconductor integrated circuit device of claim 1, wherein the surface of the substrate includes a standard cell region, and the first and second active regions are disposed in the standard cell region.
3. The semiconductor integrated circuit device of claim 2 further comprising:
a guard ring surrounding the standard cell region, wherein the guard ring includes first and second sides extending in the first direction and third and fourth sides extending in the second direction.
4. The semiconductor integrated circuit device of claim 2 wherein the standard cell region is a first standard cell region and the axis is a first axis, the device further comprising:
first and second sourcedrain regions in the first active region on opposite sides of the first gate electrode wherein the first active region, the first gate electrode, and the first and second sourcedrain regions define a first MOS transistor of a first conductivity type;
third and fourth sourcedrain regions in the second active region on opposite sides of the second gate electrode wherein the second active region, the second gate electrode, and the third and fourth sourcedrain regions define a second NMOS transistor of the first conductivity type;
a second standard cell region on the surface of a substrate;
a third active region on the surface of the substrate in the second standard cell region;
a fourth active region on the surface of the substrate in the second standard cell region;
a third gate electrode that extends across the third active region in the first direction;
a fourth gate electrode that extends across the fourth active region in the first direction;
fifth and sixth sourcedrain regions in the third active region on opposite sides of the third gate electrode wherein the third active region, the third gate electrode, and the fifth and sixth sourcedrain regions define a first MOS transistor of a second conductivity type different than the first conductivity type; and
seventh and eighth sourcedrain regions in the fourth active region on opposite sides of the fourth gate electrode wherein the fourth active region, the fourth gate electrode, and the seventh and eighth sourcedrain regions define a second MOS transistor of the second conductivity type.
5. The semiconductor integrated circuit device of claim 1 wherein the first and second directions are orthogonal.
6. The semiconductor integrated circuit device of claim 1 wherein a length of the first gate electrode in the first direction is greater than the length of the first active region in the first direction, and wherein a length of the second gate electrode in the first direction is greater than the length of the second active region in the first direction.
7. The semiconductor integrated circuit device of claim 6 wherein the length of the first gate electrode in the first direction is less than the length of the second gate electrode in the first direction.
8. The semiconductor integrated circuit device of claim 7 wherein the length of the first gate electrode in the first direction is less than the length of the second active region in the first direction.
9. The semiconductor integrated circuit device of claim 7 further comprising:
first and second dummy gate patterns at opposite ends of the first gate electrode and spaced apart from the first gate electrode, so that the first gate electrode is arranged between the first and second dummy gate patterns in the first direction.
10. The semiconductor integrated circuit device of claim 6 wherein the lengths of the first and second gate electrodes in the first direction are the same.
11. The semiconductor integrated circuit device of claim 1 further comprising:
a field region on the surface of the substrate surrounding the first and second active regions.
12. The semiconductor integrated circuit device of claim 11 further comprising:
a dummy gate pattern on the field region between the first and second active regions, wherein the dummy gate pattern extends across the field region in the first direction in parallel with the first and second gate electrodes.
13. The semiconductor integrated circuit device of claim 12 wherein a distance between the first gate electrode and the dummy gate pattern in the second direction is the same as a distance between the dummy gate pattern and the second gate electrode in the second direction.
14. The semiconductor integrated circuit device of claim 1 wherein the axis in the second direction intersects centers of the first and second gate electrodes so that the first and second gate electrodes are symmetric about the axis in the second direction.
15. The semiconductor integrated circuit device of claim 14 wherein lengths of the first and second gate electrodes in the first direction are different.
16. A semiconductor integrated circuit device comprising:
a first active region on a surface of a substrate, wherein the first active region has a length in a first direction;
a second active region on the surface of the substrate, wherein the second active region has a length in the first direction, and wherein the length of the second active region is greater than the length of the first active region;
a first gate electrode that extends across the first active region in the first direction, wherein the first gate electrode has a length in the first direction;
a second gate electrode that extends across the second active region in the first direction wherein the second gate electrode has a length in the first direction that is greater than the length of the first gate electrode in the first direction;
a first dummy gate pattern spaced apart from the first gate electrode; and
a second dummy gate pattern spaced apart from the first gate electrode, wherein the first gate electrode is arranged between the first and second dummy gate patterns in the first direction.
17-24. (canceled)
25. The semiconductor integrated circuit device of claim 16 further comprising:
a field region on the surface of the substrate surrounding the first and second active regions.
26. The semiconductor integrated circuit device of claim 25 further comprising:
a dummy gate pattern on the field region between the first and second active regions, wherein the dummy gate pattern extends across the field region in the first direction in parallel with the first and second gate electrodes.
27. The semiconductor integrated circuit device of claim 26 wherein a distance between the first gate electrode and the dummy gate pattern in the second direction is the same as a distance between the dummy gate pattern and the second gate electrode in the second direction.
28. A semiconductor integrated circuit device comprising:
a first active region on a surface of a substrate;
a second active region on the surface of the substrate;
a field region on the surface of the substrate surrounding the first and second active regions;
a first gate electrode that extends across the first active region in the first direction;
a second gate electrode that extends across the second active region in the first direction; and
a dummy gate pattern on the field region between the first and second active regions, wherein the dummy gate pattern extends across the field region in the first direction in parallel with the first and second gate electrodes, wherein an axis in a second direction intersects center points of the first gate electrode, the second gate electrode, and the dummy gate pattern.
29-38. (canceled)

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An electronic device comprising a first circuit element and a second circuit element, which are connected by bonding-bumps structure, said bonding-bumps structure comprising:
a pedestal portion comprising gold and formed on a circuit element;
a barrier layer formed on the pedestal portion;
a soldering portion formed on the barrier layer, the soldering portion comprising a first layer comprising gold, a second layer comprising gold, and an intermediate layer comprising tin and located between the first and second layers;
wherein the relative masses of gold and tin in the soldering portion are such that the composition of the soldering portion corresponds to the eutectic gold-tin composition.
2. The device of claim 1, wherein the height of the pedestal portion is of the order of 30 \u03bcm.
3. The device according to claim 1, wherein the thickness of the first layer of the soldering portion is in the range 1.0 to 1.3 \u03bcm, wherein the thickness of the second layer of the soldering portion is in the range 0.7 to 0.8 \u03bcm, and wherein the thickness of the intermediate layer of the soldering portion is in the range 1.5 to 1.8 \u03bcm.
4. The according to claim 1, wherein the thickness of the first layer of the soldering portion is approximately 1.15 \u03bcm, wherein the thickness of the second layer of the soldering portion is approximately 0.75 \u03bcm, and wherein the thickness of the intermediate layer of the soldering portion is approximately 1.65 \u03bcm.
5. The device according to claim 1, wherein the height of the bonding-bump is of the order of 35 \u03bcm, and the diameter thereof is of the order of 60 \u03bcm.
6. The device according to claim 1, wherein the bump structure is formed on a monolithic microwave integrated circuit.
7. A method of forming a bonding-bump structure for a device according to claim 1, the method comprising the steps of:
(a) forming a titanium seed layer on the circuit element;
(b) removing portions of the seed layer at locations corresponding to contacts (P) on the circuit element;
(c) performing a controlled electroplating process to successively plate, at the locations corresponding to the contacts on the circuit element, the pedestal portion, the barrier layer, the first layer comprising gold, the intermediate layer comprising tin, and the second layer comprising gold;
(d) removing the remaining portions of the titanium seed layer.
8. A bonding-bump formation method according to claim 7, wherein step (b) comprises:
forming a mask layer on the titanium seed layer, and patterning the mask layer to define at least one opening; and
removing the titanium seed layer portion(s) exposed in the at least one opening.
9. A bump-bonding method of connecting a first and a second circuit element, the method comprising the steps of:
forming at least one bonding-bump according to claim 1 on a surface of the first circuit element; bringing the first and second circuit elements into a facing relationship, with the at least one bonding bump contacting the surface of the second circuit element; and
applying heat at a temperature corresponding to the gold-tin eutectic temperature.
10. The electronic device of claim 1, wherein the first circuit element is constituted by an integrated circuit and the second circuit element is constituted by a second integrated circuit or by a substrate, which are connected by bonding-bumps according to claim 9.
11. A mobile terminal comprising an electronic device as claimed in claim 10.

1. An active device array substrate, comprising:
a substrate having a display area and a sensing area;
a first patterned conductor layer disposed on the display area of the substrate;
a gate insulator disposed on the substrate to cover the first patterned conductor layer;
a patterned semiconductor layer disposed on the gate insulator;
a second patterned conductor layer comprising a source electrode, a drain electrode and a lower electrode, wherein the source electrode and the drain electrode are disposed in the display area and cover a part of the patterned semiconductor layer, and the lower electrode is disposed on the gate insulator in the sensing area of the substrate;
a patterned photosensitive dielectric layer comprising an interface protection layer and a photo-sensing layer, wherein the interface protection layer is disposed on the source electrode and the drain electrode, and the photo-sensing layer is disposed on the lower electrode;
a passivation layer disposed on the substrate to cover the patterned photosensitive dielectric layer and the gate insulator, wherein the passivation layer and patterned photosensitive dielectric layer have a first contact window to expose one of the source electrode and the drain electrode, and the passivation layer has a second contact window to expose a portion of the photo-sensing layer; and
a third patterned conductor layer comprising a pixel electrode and an upper electrode, wherein the pixel electrode is electrically connected to one of the source electrode and the drain electrode through the first contact window, and the upper electrode covers the photo-sensing layer through the second contact window.
2. The active device array substrate of claim 1, wherein the first patterned conductor layer comprises a scan line and a gate electrode connected to the scan line.
3. The active device array substrate of claim 2, wherein the first patterned conductor layer further comprises a first bonding pad connected to an end of the scan line.
4. The active device array substrate of claim 3, wherein the gate insulator and the passivation layer further comprises a third contact window to expose the first bonding pad and a part of the third patterned conductor layer above the first bonding pad is electrically connected to the first bonding pad through the third contact window.
5. The active device array substrate of claim 1, wherein the second patterned conductor layer further comprises a data line connected to the source electrode.
6. The active device array substrate of claim 5, wherein the second patterned conductor layer further comprises a second bonding pad connected to an end of the data line.
7. The active device array substrate of claim 6, wherein the passivation layer further comprises a fourth contact window to expose the second bonding pad, and a part of the third patterned conductor layer above the second bonding pad is electrically connected to the second bonding pad through the fourth contact window.
8. The active device array substrate of claim 1, wherein the passivation layer comprises an inorganic protection layer and an organic protection layer disposed on the inorganic protection layer.
9. The active device array substrate of claim 1, further comprising a pad layer between the lower electrode and the gate insulator.
10. The active device array substrate of claim 1, further comprising a patterned heavily doped semiconductor layer is disposed between the patterned semiconductor layer and the second patterned conductor layer.
11. The active device array substrate of claim 1, wherein the patterned photosensitive dielectric layer comprises a silicon rich dielectric layer.
12. The active device array substrate of claim 1, wherein the silicon rich dielectric layer comprises a silicon rich oxide layer, a silicon rich nitride layer, a silicon rich oxynitride layer, a silicon rich carbide layer, a silicon rich carboxide layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus having a morphable free surface, comprising:
a substrate having a surface;
a morphable skin having first and second surfaces, said first surface of said morphable skin being attached to at least a portion of said surface of said substrate, said second surface of said morphable skin comprising at least one asperity, said at least one asperity configured to exhibit a morphable configuration of said second surface relative to said surface of said substrate, said at least one asperity having a height of the order of 10 percent or less than a boundary layer thickness of a fluid passing over said apparatus; and
an actuator in operative communication with said morphable skin, said actuator configured to apply a control signal to said morphable skin;
whereby, in response to a control signal applied to said morphable skin by said actuator, said second surface of said skin assumes a modified surface configuration relative to said surface of said substrate so as to provide a morphable free surface.
2. The apparatus having a morphable free surface of claim 1, wherein said morphable skin comprises an ionic polymer metal composite.
3. The apparatus having a morphable free surface of claim 1, further comprising electrodes in electrical communication with said morphable skin.
4. The apparatus having a morphable free surface of claim 3, wherein said control signal is an electrical signal applied to said electrodes.
5. The apparatus having a morphable free surface of claim 1, wherein said morphable skin comprises a shape memory material.
6. The apparatus having a morphable free surface of claim 1, wherein said control signal is a thermal signal.
7. The apparatus having a morphable free surface of claim 1, wherein said actuator is configured to be controlled by a general purpose programmable computer.
8. The apparatus having a morphable free surface of claim 1, wherein said at least one asperity comprises a surface asperity of the order of 1 millimeter.
9. The apparatus having a morphable free surface of claim 1, wherein said at least one asperity comprises a surface asperity having a height represented by the relation m * \u03bdu\u03c4, in which \u03bd is a fluid kinematic viscosity, u\u03c4 is a friction velocity equal to a square root of a ratio of wall shear stress \u03c4 to a fluid density \u03c1, and 0<m \u2266100.
10. The apparatus having a morphable free surface of claim 1, wherein said modified surface configuration relative to said surface of said substrate has a response frequency of the order of 1 kiloHertz.
11. The apparatus having a morphable free surface of claim 1, wherein said modified surface configuration relative to said surface of said substrate has a response frequency of less than the order of the viscous frequency, given by u\u03c42\u03bd, in which \u03bd is a fluid kinematic viscosity, and u\u03c4 is a friction velocity equal to a square root of a ratio of wall shear stress \u03c4 to a fluid density \u03c1.
12. A method of modifying a shape of a morphable free surface, comprising the steps of:
providing a substrate having a surface;
providing a morphable skin having first and second surfaces, said first surface of said morphable skin attached to at least a portion of said surface of said substrate, said second surface of said morphable skin comprising at least one asperity, said at least one asperity configured to exhibit a morphable configuration of said second surface relative to said surface of said substrate, said at least one asperity having a height of the order of 10 percent or less than a boundary layer thickness of a fluid passing over said apparatus;
providing an actuator in operative communication with said morphable skin, said actuator configured to apply a control signal to said morphable skin; and
applying a control signal to said morphable skin from said actuator;
whereby, in response to said control signal, said second surface of said morphable skin is caused to assume a modified surface configuration relative to said surface of said substrate thereby morphing said second surface of said morphable skin.
13. The method of modifying a shape of a morphable free surface of claim 12, wherein said morphable skin comprises an ionic polymer metal composite.
14. The method of modifying a shape of a morphable free surface of claim 12, further comprising the step of providing electrodes in electrical communication with said morphable skin.
15. The method of modifying a shape of a morphable free surface of claim 14, wherein said control signal is an electrical signal applied to said electrodes.
16. The method of modifying a shape of a morphable free surface of claim 12, wherein said morphable skin comprises a shape memory material.
17. The method of modifying a shape of a morphable free surface of claim 12, wherein said control signal is a thermal signal.
18. The method of modifying a shape of a morphable free surface of claim 12, wherein said actuator is configured to be controlled by a general purpose programmable computer.
19. The method of modifying a shape of a morphable free surface of claim 12, wherein said at least one asperity comprises a surface asperity of the order of 1 millimeter.
20. The method of modifying a shape of a morphable free surface of claim 12, wherein said at least one asperity comprises a surface asperity having a height represented by the relation m * \u03bdu\u03c4, in which \u03bd is a fluid kinematic viscosity, u\u03c4, is a friction velocity equal to a square root of a ratio of wall shear stress \u03c4 to a fluid density \u03c1, and 0<m \u2266100.
21. The method of modifying a shape of a morphable free surface of claim 12, wherein said modified surface configuration relative to said surface of said substrate is attained in a time of the order of 1 millisecond.
22. The method of modifying a shape of a morphable free surface of claim 12, wherein said modified surface configuration relative to said surface of said substrate has a response frequency of less than the order of the viscous frequency, given by u\u03c42\u03c4, in which \u03bdis a fluid kinematic viscosity, and u\u03c4 is a friction velocity equal to a square root of a ratio of wall shear stress \u03c4 to a fluid density \u03c1.