Author: claimsbot

What is claimed is:

1. A method of fabricating a semiconductor transistor, comprising:
forming a gate pattern on a semiconductor substrate;
forming a first insulating layer on an entire surface of the substrate including the gate pattern;
forming L-shaped third and second spacers which are sequentially stacked on the first insulating layer on a sidewall of the gate pattern, the third and second spacers each having a horizontal protruding portion;
simultaneously forming high- and medium-concentration junction areas in the substrate beyond the L-shaped second spacer and in the substrate under the horizontal protruding portion of the L-shaped second spacer, respectively, by performing a high-concentration ion implantation process using the L-shaped second spacer and the gate pattern as an ion implantation mask;
annealing the substrate having undergone the high-concentration ion implantation process;
removing the L-shaped second spacer; and
forming a low-concentration junction area under the horizontal protruding portion of the L-shaped third spacer by performing a low-concentration ion implantation process using the L-shaped third spacer and the gate pattern as an ion implantation mask.
2. The method as claimed in claim 1, wherein forming the L-shaped third and second spacers comprises:
forming second, third, and fourth insulating layers which are sequentially stacked on the first insulating layer;
anisotropically etching the fourth insulating layer to form a first spacer on the sidewall of the third insulating layer;
etching the third insulating layer, using the first spacer as an etch mask, to form an L-shaped second spacer having a horizontal protruding portion under the first spacer; and
etching the second insulating layer at the same time as removing the first spacer to form an L-shaped third spacer having a horizontal protruding portion under the L-shaped second spacer.
3. The method as claimed in claim 1, wherein the first insulating layer is made of silicon oxide.
4. The method as claimed in claim 2, wherein the second insulating layer is made of material having an etch selectivity with respect to the first insulating layer.
5. The method as claimed in claim 2, wherein the third insulating layer is made of material having an etch selectivity with respect to the second insulating layer.
6. The method as claimed in claim 2, wherein the fourth insulating layer is made of material having an etch selectivity with respect to the third insulating layer.
7. The method as claimed in claim 2, wherein removing the first spacer uses an isotropic etch technique.
8. The method as claimed in claim 1, wherein removing the L-shaped second spacer uses an isotropic etch technique.
9. The method as claimed in claim 1, wherein removing the L-shaped second spacer includes etching the first insulating layer exposed on the gate pattern and beyond the L-shaped third spacer to expose a top surface of the gate pattern and to form an L-shaped fourth spacer having a horizontal protruding portion under the L-shaped third spacer.
10. The method as claimed in claim 9, further comprising forming a silicide layer on the substrate at both sides of the L-shaped fourth spacer and on the gate pattern, after the low-concentration ion implantation process is performed.
11. The method as claimed in claim 1, wherein the annealing process step is a rapid thermal process (RTP).
12. The method as claimed in claim 1, wherein forming the medium- and high-concentration junction areas causes the medium-concentration junction area to have a lower impurity concentration than the high-concentration junction area, using the protruding portions of the L-shaped second and third spacers and the first insulating layer as an ion channeling barrier layer.
13. A semiconductor transistor comprising:
a gate pattern formed on a semiconductor substrate;
an L-shaped third spacer having a horizontal protruding portion, the third spacer being formed on a sidewall surface of the gate pattern;
an L-shaped fourth spacer having a vertical sidewall between a vertical sidewall of the L-shaped third spacer and the gate pattern and a horizontal protruding portion between the protruding portion of the L-shaped third spacer and the substrate;
a high-concentration junction area formed in the substrate beyond the L-shaped third spacer;
a low-concentration junction area formed in the substrate under the horizontal protruding portion of the L-shaped third spacer; and
a medium-concentration junction area positioned between the high- and low-concentration junction areas.
14. The semiconductor transistor as claimed in claim 13, wherein the medium- and low-concentration junction areas are formed under the protruding portion of the L-shaped third spacer.
15. The semiconductor transistor as claimed in claim 13, wherein the L-shaped fourth spacer is made of silicon oxide.
16. The semiconductor transistor as claimed in claim 13, wherein the L-shaped third spacer is made of material having an etch selectivity with respect to the L-shaped fourth spacer.
17. The method as claimed in claim 9, wherein the L-shaped third spacer is removed before the low-concentration ion-implantation process is performed.
18. The method as claimed in claim 1, wherein a silicon oxide layer is formed on the substrate before the low concentration ion-implantation process.
19. The method as claimed in claim 4, wherein the second insulating layer is made of a material selected from the group consisting of silicon nitride and silicon oxynitride.
20. The method as claimed in claim 4, wherein the third insulating layer is made of silicon oxide.
21. The method as claimed in claim 6, wherein the fourth insulating layer is made of a material selected from the group consisting of silicon nitride and silicon oxynitride.
22. The method as claimed in claim 1, wherein the first insulating layer is formed to a thickness of between about 2 nm-5 nm.
23. The method as claimed in claim 2, wherein the sum of the thickness of the first and second insulating layers is between about 5 nm-20 nm.
24. The method as claimed in claim 2, wherein the third insulating layer is formed to a thickness of between about 20 nm-70 nm.
25. The method as claimed in claim 2, wherein the fourth insulating layer is formed to a thickness of between about 30 nm-90 nm.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An overheat protection circuit comprising:
a temperature detection circuit;
a bias circuit which allows a bias current to flow in the temperature detection circuit; and
a leak current detection circuit which detects a leak current of a transistor allowing the bias current of the bias circuit to flow,
said leak current detection circuit controlling the bias current when the leak current is detected.
2. The overheat protection circuit according to claim 1, wherein the leak current detection circuit includes:
a first transistor having a gate and a source connected to each other and allowing the leak current to flow,
a first current mirror circuit which mirrors the leak current, and
a pull-up circuit connected to an output of the first current mirror circuit.
3. The overheat protection circuit according to claim 1, wherein the bias circuit includes:
a first current source,
a first current mirror circuit which mirrors a current of the first current source and allows the bias current to flow, and
a switch circuit which controls the operation of the first current mirror circuit in response to a signal from the leak current detection circuit.
4. The overheat protection circuit according to claim 3, wherein the bias circuit further includes a second current mirror circuit which mirrors the current of the first current source and allows the bias current to flow.
5. The overheat protection circuit according to claim 2, wherein the bias circuit includes:
a first current source,
a first current mirror circuit which mirrors the current of the first current source and allows the bias current to flow, and
a switch circuit which controls the operation of the first current mirror circuit in response to the signal from the leak current detection circuit.
6. The overheat protection circuit according to claim 5, wherein the bias circuit further includes a second current mirror circuit which mirrors the current of the first current source and allows the bias current to flow.
7. A voltage regulator comprising:
a reference voltage circuit which outputs a reference voltage;
an output transistor which outputs an output voltage from an output terminal;
an error amplifier circuit which amplifies a difference between a divided voltage obtained by dividing the output voltage and the reference voltage and outputs the same therefrom, and controls a gate of the output transistor; and
the overheat protection circuit according to any of claims 1 to 6, which controls the gate of the output transistor.

1. A method of testing an ionic polymer-metal composite device implanted within a patient’s body, comprising:
supplying power to the device in a first testing interval;
measuring an electrical response of the device in the first testing interval;
supplying power to the device continuously following the first testing interval;
supplying power to the device in a second testing interval after the predetermined time;
measuring the electrical response of the device in the second testing interval; and
detecting a functionality of the device based on the electrical response measured in the first and second testing intervals.
2. The method of claim 1, wherein supplying power in the first and second testing intervals comprises generating a series of pulses.
3. The method of claim 1, wherein measuring the electrical response comprises detecting a voltage within the patient’s body proximate to the device.
4. The method of claim 1, further comprising indicating the functionality of the device when the electrical response measured in the first testing interval is larger than the electrical response measured in the second testing interval.
5. The method of claim 1, wherein the electrical response is associated with a capacitance of the IPMC device.
6. The method of claim 1, wherein power is withheld from the device for a predetermined period before the first testing interval.
7. The method of claim 1, wherein the device is powered continuously for at least one minute following the first testing interval.
8. The method of claim 1, wherein measuring the electrical response comprises taking a series of measurements.
9. The method of claim 8, further comprising detecting an abnormality of the device based on the series of measurements.
10. A device for testing an ionic polymer-metal composite implant, comprising:
a transducer configured to supply power to the implant when the implant is within a patient’s body;
a detector configured to measure an electrical response of the implant within the patient’s body; and
a controller coupled to the transducer and the detector for controlling their respective operations, wherein the controller is configured to perform a test of the implant by supplying power to and measuring the electrical response of the implant in a testing interval, and the controller is configured to detect a functionality of the implant by performing a first test, powering the implant continuously, and performing a second test after the implant is continuously powered.
11. The device of claim 10, wherein the transducer supplies power to the implant through a series of pulses in the testing intervals.
12. The device of claim 10, wherein the detector is configured to measure a voltage level in a vicinity of the implant.
13. The device of claim 10, wherein the controller detects the functionality based on a comparison of the electrical response in the first test and the electrical response in the second test.
14. The device of claim 13, further comprising a user interface, and wherein the controller is configured to signal the functionality of the implant at the user interface when the electrical response of the implant in the first test is larger than the electrical response of the implant in the second test.
15. The device of claim 10, wherein the electrical response is associated with a capacitance of the implant.
16. The device of claim 10, wherein the controller is configured to power the implant continuously for at least one minute.
17. The device of claim 10, wherein the controller is configured to obtain a series of measurements in each testing interval.
18. The device of claim 17, wherein the controller is configured to detect an abnormality of the implant based on the series of measurements.
19. The device of claim 10, further comprising a mouthpiece adapted to be worn in the patient’s mouth, wherein the transducer, detector and controller are attached to the mouthpiece.
20. The device of claim 10, further comprising an elongated body adapted to be inserted into a patient’s mouth and wherein the detector is attached to a distal end of the elongated body.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A connector to be used in a model train, comprising:
a first coupling member having a distal portion configured to attach to a first model train car;
a second coupling member having a distal portion configured to attach to a second model train car, and a proximal portion configured to engage with a proximal portion of the first coupling member; and
a resilient electrical contact associated with the second coupling member and disposed to make an electrical connection to a first electrical contact of the first coupling member when the proximal portion of the second coupling member is engaged with the proximal portion of the first coupling member.
2. The connector of claim 1, further comprising a first electrical conductor connected to the first electrical contact and extending to the distal portion of the first coupling member.
3. The connector of claim 1, wherein the first electrical contact comprises a substantially rigid end disposed against the resilient electrical contact when the proximal portion of the second coupling member is engaged with the proximal portion of the first coupling member.
4. The connector of claim 1, wherein the proximal portion of the second coupling member and the proximal portion of the first coupling member are configured to permit vertical movement of the first coupling member relative to the second coupling member when engaged together.
5. The connector of claim 1, wherein the resilient electrical contract comprises at least one vertically-oriented finger extending from a surface of the second coupling member.
6. The connector of claim 1, wherein the resilient electrical contact comprises a plurality of vertically-oriented fingers extending from a surface of the second coupling member.
7. The connector of claim 1, wherein the resilient electrical contact comprises a piece of metallic sheet material.
8. The connector of claim 1, further comprising a first model car and a second model car coupled together by the first and second coupling members, whereby the first model car is in electrical communication with the second model car.
9. The model train assembly of claim 1, further comprising a wireless transmitter associated with one of the first or second model train cars, the transmitter disposed to communicate with a wireless receiver associated with another of the first or second model train cars only when the proximal portion of the second coupling member is engaged with the proximal portion of the first coupling member.
10. The connector of claim 2, wherein the first electrical conductor is substantially surrounded by at least one layer of insulating material.
11. The connector of claim 2, further comprising a second electrical conductor connected to the resilient electrical contact and extending to the distal portion of the second coupling member.
12. The connector of claim 11, wherein the second electrical conductor is substantially surrounded by at least one layer of insulating material.
13. The connector of claim 4, wherein the resilient electrical contact and the first electrical contact are configured to maintain an electrical connection during the permitted vertical movement.
14. The connector of claim 13, wherein the resilient electrical contact is configured to remain resiliently biased against the first electrical contact while sliding vertically during the permitted vertical movement.
15. The connector of claim 5, wherein the at least one finger is curved in a substantially vertical plane to define an intermediate portion for contacting the first electrical contact between a base of the at least one finger and an end of the at least one finger.
16. The connector of claim 2, wherein the second electrical conductor and the resilient electrical contact comprise an integrated piece of metallic sheet material.
17. The connector of claim 16, wherein the integrated piece of metallic sheet material is shaped to conform to the second coupling member.
18. The connector of claim 10, wherein the first electrical conductor and the first electrical contact comprise an integrated piece of metallic sheet material.
19. The connector of claim 10, wherein the first electrical conductor comprises a mechanical draw bar.