Author: claimsbot

What is claimed is:

1. A photodetector comprising:
a photodetection element for outputting electric charge in an amount corresponding to incident light intensity;
an integration circuit having:
an amplifier,
an integration capacitance section arranged in parallel to said amplifier between an input terminal and an output terminal, and
capacitance value switching means for switching the capacitance value of said integration capacitance section into any one of first through K-th capacitance values, where K indicates an integer greater than or equal to 2,
wherein integration circuit inputs electric charge output from said photodetection element through said input terminal, so as to accumulate said electric charge into said integration capacitance section having the capacitance value switched into by said capacitance value switching means, so as to output through said output terminal a voltage corresponding to the amount of the accumulated electric charge; and an AD converter circuit having
reference voltage switching means for switching a reference voltage used in AD conversion, into any one of first through L-th reference voltages, where L indicates an integer greater than or equal to 2,
wherein said AD converter circuit which inputs the voltage output through said output terminal of said integration circuit, so as to AD-convert said voltage on the basis of the reference voltage switched and set to be by said reference voltage switching means, so as to output a digital value corresponding to said voltage.
2. A photodetector according to claim 1, wherein
when the k-th capacitance value among said first through K-th capacitance values is denoted by Cfk, the relational expression Cf1>Cf2> . . . >Cfk> . . . >CfK-1>CfK holds, while when the l-th reference voltage among said first through L-th reference voltages is denoted by Vref,1, the relational expression Vref,1>Vref,2> . . . >Vref,1> . . . . >Vref,L-1 >Vref,L holds, and wherein
said photodetector further comprises:
a storage section which is provided with first through K-th storage regions and storage region switching means for switching the region into any one of these regions, and which stores the digital value output from said AD converter circuit, into any storage region switched into and selected from said first through K-th storage regions by said storage region switching means; and
controlling means which controls said capacitance value switching means of said integration circuit, said reference voltage switching means of said AD converter circuit, and said storage region switching means of said storage section, so as to set the capacitance value of said integration capacitance section of said integration circuit to be the k-th capacitance value Cfk, set the reference voltage of said AD converter circuit to be the l-th reference voltage Vref,1, and store the digital value output from said AD converter circuit into the k-th storage region.
3. A photodetector according to claim 1, wherein a plurality of said photodetection elements are provided and arranged in two dimensions of M rows by N columns, where M2 and N2, while said integration circuit and said AD converter circuit are arranged for each column of said photodetection elements arranged in two dimensions.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An attaching method of attaching a solid state pickup device including an imaging element having a light receiving surface to an electronic camera including a lens barrel, and a condenser lens supported in said lens barrel, said attaching method comprising steps of:
placing said solid state pickup device in a receiving recess formed in a rear portion of said lens barrel, said receiving recess having a size larger than said solid state pickup device; and
pressing said solid state pickup device in an optical axis direction of said condenser lens and a crosswise direction to said optical axis direction, for fitting and positioning a front face and part of an end face of said solid state pickup device into said receiving recess,
wherein said solid state pickup device further includes a box-shaped shield glass, said imaging element further having plural contact points, said shield glass has a plate portion and a receiving surface border portion, said plate portion is disposed over said light receiving surface, and said receiving surface border portion has substantially a quadrilateral shape, and attached to said imaging element to surround said light receiving surface.
2. The attaching method as defined in claim 1, wherein said imaging element is pushed by a biasing force in said crosswise direction, and pressed against an inside of said receiving recess.
3. The attaching method as defined in claim 2, wherein said imaging element has substantially a quadrilateral shape, and said crosswise direction comprises two directions defined along two adjacent side lines of said imaging element.
4. The attaching method as defined in claim 2, wherein said imaging element has substantially a quadrilateral shape, and said crosswise direction is defined along a diagonal line of said imaging element.
5. An attaching method of attaching a solid state pickup device including an imaging element having a light receiving surface to an electronic camera including a lens barrel, and a condenser lens supported in said lens barrel, said solid state pickup device having a wiring pattern disposed on an outside thereof, said attaching method comprising steps of:
placing said solid state pickup device in a receiving recess formed in a rear portion of said lens barrel, said receiving recess having a size larger than said solid state pickup device; and
pressing said solid state pickup device in an optical axis direction of said condenser lens and a crosswise direction to said optical axis direction, for tightly fitting a front face and part of an end face of said solid state pickup device into said receiving recess, to position said solid state pickup device on said lens barrel, wherein said front face and said part of the end face lacks said wiring pattern,
wherein said solid state pickup device further includes:
a shield glass layer attached to said imaging element to cover said light receiving surface; and
a reinforcing glass layer attached to said imaging element on a side opposite to said light receiving surface.
6. The attaching method as defined in claim 5, wherein said solid state pickup device has substantially a quadrilateral shape, and includes a first end face for being fitted in said receiving recess, a second end face disposed opposite to said first end face, first and second lateral faces directed opposite to each other, and a rear face directed opposite to said front face;
said wiring pattern extends from at least one of said first and second lateral faces toward said rear face.
7. The attaching method as defined in claim 6, wherein said solid state pickup device is pressed in said crosswise direction by a clamper or pressure pad.
8. The attaching method as defined in claim 7, wherein said clamper includes first and second clamp jaws, biased toward each other, for clamping said solid state pickup device therebetween, to position said solid state pickup device in said optical axis direction.
9. The attaching method as defined in claim 8, wherein said clamper clamps said second end face, or clamps a corner between said second end face and said second lateral face, and presses said first end face against said receiving recess, or presses a corner between said first end face and said first lateral face against said receiving recess.
10. The attaching method as defined in claim 7, wherein said pressure pad has an inclined face directed toward a front with an inclination;
said second end face is directed toward a rear with an inclination, pressed by said inclined face, to position said solid state pickup device in said optical axis direction.

1. A method of forming a hold-switch actuator for a portable electronic device comprising:
stamping a hold-switch slider form;
folding a portion of the form to create a double thickness portion of the form; and
stamping a cutout from the double thickness portion of the form.
2. The method of claim 1 further comprising stamping the cutout in a shape that mates with a hold-switch component.
3. The method of claim 1 further comprising stamping the cutout in a shape that mates with a hold-switch component in a tightly-toleranced relationship.
4. The method of claim 1 wherein the device is a hand-held media player.
5. The method of claim 1 wherein the device is a miniature media player.
6. A hold-switch slider for a portable electronic device comprising:
a single thickness portion; and
a double thickness portion, the double thickness portion comprising a folded portion of the single thickness portion.
7. The hold-switch slider of claim 6, the double thickness portion comprising a cutout.
8. The hold-switch slider of claim 6, the double thickness portion comprising a cutout, the cutout comprising a shape that mates with a hold-switch component.
9. A miniature media player comprising a hold-switch slider according to claim 6.
10. A hand-held media player comprising a hold-switch slider according to claim 6.
11. The hold-switch slider of claim 6, the hold-switch slider capable of indicating three different states of operation of a media player.
12. A method of forming a hold-switch actuator for a portable electronic device, the method comprising:
stamping a hold-switch slider form; and
folding a portion of the form to create a double thickness portion of the form.
13. The method of claim 12 further comprising stamping a cutout from the double thickness portion of the form.
14. The method of claim 12 the folding further comprising folding the portion to create a double thickness portion of the form, the double thickness portion of the form comprising a cutout that is adapted to actuate a hold-switch component.
15. The method of claim 12 further comprising stamping a cutout from the double thickness portion of the form in a shape that mates with a hold-switch component.
16. The method of claim 12 further comprising stamping a cutout in a shape that mates with a hold-switch component in a tightly-toleranced relationship.
17. The method of claim 12 further comprising implementing the hold-switch actuator in a hand-held media player.
18. The method of claim 12 further comprising implementing the hold-switch actuator in a miniature media player.
19. A mechanical actuator for use in actuating an component within a hand-held electronic device, the mechanical actuator comprising:
an interface region that provides an interface for a user to move the actuator; and
an actuation region, the actuation region that is thicker than the interface portion, the actuation region that mates with the component within an electronic device.
20. The mechanical actuator of claim 19, the actuation region comprising double the thickness of the interface region, the actuation region comprising a cutout for mating with the component.
21. A miniature media player comprising a mechanical actuator according to claim 19.
22. A hand-held media player comprising a mechanical actuator according to claim 19.
23. A mechanical actuator for use in a miniature electronic device, the mechanical actuator comprising:
an interface region that provides an interface for a user to move the actuator; and
an actuation region, wherein the mechanical actuator comprises a substantially uniform thickness, the actuation region that mates with a component within the electronic device.
24. The mechanical actuator of claim 23, the actuation region comprising double the thickness of the interface region, the actuation region comprising a cutout for mating with the component.
25. A miniature media player comprising a mechanical actuator according to claim 23.
26. A hand-held media player comprising a mechanical actuator according to claim 23.
27. A method of using a hold-switch actuator for use in a portable electronic device, the method comprising:
stamping a hold-switch slider form;
folding a portion of the form to create a double thickness portion of the form;
stamping a cutout from the double thickness portion of the form; and
using the hold-switch actuator to indicate at least three different states of operation of the electronic device.
28. The method of claim 27 further comprising stamping the cutout in a shape that mates with a hold-switch component.
29. The method of claim 27 further comprising stamping the cutout in a shape that mates with a hold-switch component in a tightly-toleranced relationship.
30. The method of claim 27 further comprising implementing the hold-switch actuator in a hand-held media player.
31. The method of claim 27 further comprising implementing the hold-switch actuator in a miniature media player.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for data storage, comprising:
defining at least first and second read commands for reading storage values from analog memory cells, such that the first read command reads the storage values at a first accuracy and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy;
evaluating a condition with respect to a read operation that is to be performed over a given group of the memory cells;
selecting one of the first and second read commands responsively to the evaluated condition; and
reading the storage values from the given group of the memory cells using the selected read command.
2. The method according to claim 1, wherein the first read command has a first execution time, and wherein the second read command has a second execution time that is longer than the first execution time.
3. The method according to claim 1, wherein reading the storage values comprises sensing the storage values over a first sense time duration when using the first read command, and sensing the storage values over a second sense time duration, which is longer than the first sense time duration, when using the second read command.
4. The method according to claim 1, wherein reading the storage values comprises comparing the read storage values to a first number of read thresholds when using the first read command, and comparing the read storage values to a second number of the read thresholds, which is larger than the first number, when using the second read command.
5. The method according to claim 1, wherein reading the storage values comprises applying to the read storage values a first signal processing process having a first execution time when using the first read command, and applying to the read storage values a second signal processing process having a second execution time, which is longer than the first execution time, when using the second read command.
6. The method according to claim 5, wherein the analog memory cells are comprised in a memory device that is connected to a memory controller, wherein applying the first signal processing process comprises performing the first signal processing process by circuitry comprised in the memory device, and wherein applying the second signal processing process comprises performing the second signal processing process by the memory controller.
7. The method according to claim 6, wherein the first and second signal processing processes comprise interference cancellation processes.
8. The method according to claim 1, wherein reading the storage values comprises comparing the read storage values to one or more read thresholds, adaptively adjusting the read thresholds when using the second read command, and refraining from adaptively adjusting the read thresholds when using the first read command.
9. The method according to claim 1, wherein reading the storage values comprises canceling interference in the read storage values when using the second read command, and refraining from canceling the interference when using the first read command.
10. The method according to claim 1, wherein reading the storage values comprises producing respective hard metrics of the read storage values when using the first read command, and producing respective soft metrics of the read storage values when using the second read command.
11. The method according to claim 1, wherein the storage values in the given group of the memory cells represent stored data, and wherein evaluating the condition and selecting the one of the read commands comprise making an attempt to read the storage values from the memory cells in the group and to reconstruct the stored data, and selecting the one of the first and second read commands responsively to the attempt.
12. The method according to claim 11, wherein the stored data is encoded with an Error Correction Code (ECC), and wherein making the attempt comprises decoding the ECC.
13. The method according to claim 11, wherein making the attempt comprises reading the storage values using the first read command, and, responsively to a failure in reconstructing the stored data, re-attempting to read the storage values and reconstruct the stored data using the second read command.
14. The method according to claim 13, wherein re-attempting to reconstruct the stored data comprises reconstructing the stored data using both the storage values read by the first read command and the re-read storage values read using the second read command.
15. The method according to claim 1, wherein evaluating the condition comprises assessing a wear level of the group of the memory cells.
16. The method according to claim 1, wherein evaluating the condition and selecting the one of the read commands comprise selecting the first read command responsively to determining that the read operation reads the storage values from potentially-interfering memory cells in an interference cancellation process.
17. The method according to claim 1, wherein evaluating the condition and selecting the one of the read commands comprise selecting the first read command responsively to determining that the read operation verifies the storage values that were written into the given group of the memory cells.
18. The method according to claim 1, wherein each of the memory cells in the given group stores at least first and second bits, and wherein evaluating the condition and selecting the one of the read commands comprise selecting the first read command responsively to determining that the read operation reads the first bits from the memory cells, and selecting the second read command responsively to determining that the read operation reads the second bits from the memory cells.
19. The method according to claim 1, wherein evaluating the condition and selecting the one of the read commands comprise selecting the first read command responsively to determining that the read operation is used for estimating a statistical distribution of the storage values that were written into the given group of the memory cells.
20. The method according to claim 1, wherein the read commands have respective attributes, and wherein defining the read commands comprises configuring at least one of the attributes.
21. The method according to claim 20, wherein configuring the at least one attribute comprises estimating an impairment in the analog memory cells, and setting the attribute responsively to estimated impairment.
22. Apparatus for data storage, comprising:
a plurality of analog memory cells; and
circuitry, which is configured to execute at least first and second read commands for reading storage values from the analog memory cells, such that the first read command reads the storage values at a first accuracy and the second read command reads the storage values at a second accuracy that is finer than the first accuracy, and which is operative to evaluate a condition with respect to a read operation that is to be performed over a given group of the memory cells, to select one of the first and second read commands responsively to the evaluated condition, and to read the storage values from the given group of the memory cells using the selected read command.
23. The apparatus according to claim 22, wherein the analog memory cells are arrayed in a memory device, and wherein the circuitry comprises:
first circuitry, which is comprised in the memory device and is coupled to receive the selected one of the first and second read commands over an interface and to read the storage values at a respective one of the first and second accuracies; and
second circuitry, which is separate from the memory device and is coupled to evaluate the condition, to select the one of the first and second read commands and to send the selected command to the first circuitry over the interface for execution.
24. The apparatus according to claim 22, wherein the first read command has a first execution time, and wherein the second read command has a second execution time that is longer than the first execution time.
25. The apparatus according to claim 22, wherein the circuitry is configured to sense the storage values over a first sense time duration when executing the first read command, and to sense the storage values over a second sense time duration that is longer than the first sense time duration when executing the second read command.
26. The apparatus according to claim 22, wherein the circuitry is configured to compare the read storage values to a first number of read thresholds when executing the first read command, and to compare the read storage values to a second number of the read thresholds that is larger than the first number when executing the second read command.
27. The apparatus according to claim 22, wherein the circuitry is configured to apply to the read storage values a first signal processing process having a first execution time when executing the first read command, and to apply to the read storage values a second signal processing process having a second execution time, which is longer than the first execution time, when executing the second read command.
28. The apparatus according to claim 27, wherein the analog memory cells are arrayed in a memory device, and wherein the circuitry comprises:
first circuitry, which is comprised in the memory device and is configured to apply the first signal processing process; and
second circuitry, which is separate from the memory device and is configured to apply the second signal processing process.
29. The apparatus according to claim 28, wherein the first and second signal processing processes comprise interference cancellation processes.
30. The apparatus according to claim 22, wherein the circuitry is configured to compare the read storage values to one or more read thresholds, to adaptively adjust the read thresholds when executing the second read command, and to refrain from adaptively adjusting the read thresholds when executing the first read command.
31. The apparatus according to claim 22, wherein the circuitry is configured to cancel interference in the read storage values when executing the second read command, and to refrain from canceling the interference when executing the first read command.
32. The apparatus according to claim 22, wherein the circuitry is configured to produce respective hard metrics of the read storage values when executing the first read command, and to produce respective soft metrics of the read storage values when executing the second read command.
33. The apparatus according to claim 22, wherein the storage values in the given group of the memory cells represent stored data, and wherein the circuitry is configured to make an attempt to read the storage values from the memory cells in the group and to reconstruct the stored data, and to select the one of the first and second read commands responsively to the attempt.
34. The apparatus according to claim 33, wherein the stored data is encoded with an Error Correction Code (ECC), and wherein the circuitry is configured to reconstruct the stored data by decoding the ECC.
35. The apparatus according to claim 33, wherein the circuitry is configured to read the storage values using the first read command, and, responsively to a failure in reconstructing the stored data, to re-attempt to read the storage values and reconstruct the stored data using the second read command.
36. The apparatus according to claim 33, wherein the circuitry is configured to re-attempt to reconstruct the stored data using both the storage values read by the first read command and the re-read storage values read using the second read command.
37. The apparatus according to claim 22, wherein the circuitry is configured to evaluate the condition by assessing a wear level of the group of the memory cells.
38. The apparatus according to claim 22, wherein the circuitry is configured to select the first read command responsively to determining that the read operation reads the storage values from potentially-interfering memory cells in an interference cancellation process.
39. The apparatus according to claim 22, wherein the circuitry is configured to select the first read command responsively to determining that the read operation verifies the storage values that were written into the given group of the memory cells.
40. The apparatus according to claim 22, wherein each of the memory cells in the given group stores at least first and second bits, and wherein the circuitry is configured to select the first read command responsively to determining that the read operation reads the first bits from the memory cells, and to select the second read command responsively to determining that the read operation reads the second bits from the memory cells.
41. The apparatus according to claim 22, wherein the circuitry is configured to select the first read command responsively to determining that the read operation is used for estimating a statistical distribution of the storage values that were written into the given group of the memory cells.
42. The apparatus according to claim 22, wherein the read commands have respective attributes, and wherein the circuitry is configured to configure at least one of the attributes.
43. The apparatus according to claim 42, wherein the circuitry is configured to estimate an impairment in the analog memory cells, and to set the attribute responsively to estimated impairment.