Author: claimsbot

1. A circuit for use with a loudspeaker having a first differential input terminal and a second differential input terminal, the circuit comprising:
a differential power amplifier having a first differential output terminal operatively connected to the first differential input terminal of the loudspeaker and a second differential output terminal operatively connected to the second differential input terminal of the loudspeaker;
a first resistor disposed between the first differential output terminal of the differential power amplifier and the first differential input terminal of the loudspeaker;
a second resistor disposed between the second differential output terminal of the differential power amplifier and the second differential input terminal of the loudspeaker,
the circuit wherein it further comprises:
a first resistive module arranged to generate on a respective output terminal a first control voltage, the first resistive module having a first input terminal connected to the first differential output terminal of the power amplifier and a second input terminal connected to the second differential input terminal of the loudspeaker,
a second resistive module arranged to generate on a respective output terminal a second control voltage, the second resistive module having a first input terminal connected to the second differential output terminal of the power amplifier and a second input terminal connected to the first differential input terminal of the loudspeaker,
the circuit being arranged to control the differential power amplifier on the basis of the first control voltage and the second control voltage.
2. The circuit of claim 1, wherein the first resistive module comprises a third resistor and a fourth resistor, the third resistor having a respective first terminal corresponding to the first input terminal of the first resistive module and a respective second terminal, the fourth resistor having a respective first terminal corresponding to the second input terminal of the first resistive module and a respective second terminal, the second terminal of the third resistor and the second terminal of the fourth resistor being connected together in a node, the output terminal of the first resistive module being connected to said node.
3. The circuit of claim 1, wherein the second resistive module comprises a fifth resistor and a sixth resistor, the fifth resistor having a respective first terminal corresponding to the first input terminal of the second resistive module and a respective second terminal, the sixth resistor having a respective first terminal corresponding to the second input terminal of the second resistive module and a respective second terminal, the second terminal of the fifth resistor and the second terminal of the sixth resistor being connected together in a node, the output terminal of the second resistive module being connected to said node.
4. The circuit of claim 3, wherein the third resistor of the first resistive module, the fourth resistor of the first resistive module, the fifth resistor of the second resistive module and the sixth resistor of the second resistive module have substantially a same first reference value.
5. The circuit of claim 1, wherein the first resistor and the second resistor have substantially a same second reference value.
6. The circuit of claim 4, wherein said second reference value is lower than the first reference value.
7. The circuit of claim 1, further comprising a differential stage having a first differential input terminal to receive the first control voltage and a second differential input terminal to receive the second control voltage, the differential stage having a first differential output terminal and a second differential output terminal.
8. The circuit of claim 7, wherein the differential stage comprises:
a first input NMOS transistor having the gate terminal corresponding to the first differential input terminal of the differential stage, the drain terminal operatively connected to a first reference voltage through a first current generator and the source terminal operatively connected to a second supply voltage through a first source resistor of the differential stage and a second current generator;
a second input NMOS transistor having the gate terminal corresponding to the second differential input terminal of the differential stage, the drain terminal operatively connected to the first reference voltage through a third current generator and the source terminal operatively connected to the second reference voltage through a second source resistor of the differential stage and the second current generator.
9. The circuit of claim 8, wherein the differential stage further comprises:
a first current mirror arranged to mirror the current passing on the first source resistor of the differential stage to a first output branch connected to the first differential output terminal of the differential stage;
a second current mirror arranged to mirror the current passing on the second source resistor of the differential stage to a second output branch connected to the second differential output terminal of the differential stage.
10. The circuit of claim 9, wherein:
the first current mirror comprises a first PMOS transistor having the gate terminal connected to the drain terminal of the first input NMOS transistor of the differential stage, the source terminal connected to the first reference voltage and the drain terminal connected to the source terminal of the first input NMOS transistor of the differential stage, and
the first output branch comprising a second PMOS transistor having the gate terminal connected to the drain terminal of the first input NMOS transistor of the differential stage, the source terminal connected to the first reference voltage and the drain terminal connected to the second reference voltage through a respective current generator, the first differential output terminal of the differential stage corresponding to the drain terminal of the second PMOS transistor of the first output branch.
11. The circuit of claim 9, wherein:
the second current mirror comprises a first PMOS transistor having the gate terminal connected to the drain terminal of the second input NMOS transistor of the differential stage, the source terminal connected to the first reference voltage and the drain terminal connected to the source terminal of the second input NMOS transistor of the differential stage, and
the second output branch comprises a second PMOS transistor having the gate terminal connected to the drain terminal of the second input NMOS transistor of the differential stage, the source terminal connected to the first reference voltage and the drain terminal connected to the second reference voltage through a respective current generator, the second differential output terminal of the differential stage corresponding to the drain terminal of the second PMOS transistor of the second output branch.
12. The circuit of claim 8, wherein:
each of the NMOS transistors and each of the PMOS transistors representing the current generators of the differential stage, is electrically connected in series with a respective NMOS transistor and with a PMOS transistor, in a cascode configuration,
each of the PMOS transistor of the first current mirror is electrically connected in series with a respective PMOS transistor in a cascode configuration and each of the PMOS transistor of the second current mirror is electrically connected in series with a respective PMOS transistor in a cascode configuration.
13. The circuit according to claim 1, further comprising a driving module having a first differential input terminal operatively connected with the first differential output terminal of the differential stage and a second differential input terminal operatively connected to the second differential output terminal of the differential stage, said driving circuit having a first differential output terminal operatively connected to a first differential input terminal of the differential power amplifier and a second differential output terminal operatively connected to a second differential input terminal of the differential power amplifier.
14. The circuit of claim 13, wherein the driving module comprises:
a digital processing unit;
a digital-to-analog converter; and
a analog-to-digital converter.
15. Portable equipment comprising a loudspeaker and a circuit according to claim 1.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An implantable lead comprising:
an insulative sheath; and
a coil member extending through the insulative sheath and including a wound conductor, a proximal end, a first distal end, a reverse wound electrode, and a first outer diameter;
wherein the conductor winds from the proximal end to the first distal end forming the first outer diameter of the coil member, and reverse winds back toward the proximal end to form the electrode on the first outer diameter, the electrode disposed adjacent and distal to the insulative sheath.
2. The implantable lead of claim 1, wherein the wound conductor includes a plurality of common wires, the plurality including from two to six wires.
3. The implantable lead of claim 1, wherein a length of the electrode is between approximately 2 mm and 3 cm.
4. The implantable lead of claim 1, wherein a length of the electrode is between approximately 3 cm and 6 cm.
5. The implantable lead of claim 1, wherein the electrode serves as a pacing and sensing anode.
6. The implantable lead of claim 1, wherein the electrode serves as a defibrillation electrode.
7. The implantable lead of claim 1, wherein the insulative sheath includes an outer diameter and the electrode forms a second outer diameter of the coil member, the second outer diameter substantially equivalent to the outer diameter of the insulative sheath.
8. The implantable lead of claim 1, further comprising an electrode tip positioned at a second distal end, the second distal end disposed distal to the first distal end;
wherein the coil member further includes a second wound conductor winding from the proximal end to the second distal end further forming, proximal to the first distal end, the first outer diameter of the coil;
the second conductor including an outer insulative layer and coupled to the electrode tip.
9. The implantable lead of claim 8, wherein the wound conductor and the second wound conductor each include a plurality of wires, the plurality including a pair of wires.
10. The implantable lead of claim 8, further comprising
an inner tubing forming a lumen and extending within the coil from the proximal end to the second distal end; and
a fiber core extending within the lumen from the proximal end to the second distal end where it is joined to the electrode tip.
11. The implantable lead of claim 8, wherein the coil member further includes a third wound conductor and a first reverse wound intermediate electrode; the third conductor including an outer insulative layer and winding from the proximal end to a position in between the first distal end and the second distal end further forming the first outer diameter of the coil, and reverse winding back toward the proximal end to form the intermediate electrode on the first outer diameter of the coil.
12. The implantable lead of claim 11, wherein the coil member further includes a fourth conductor and a second reverse wound intermediate electrode; the fourth conductor including an outer insulative layer and winding from the proximal end to a position in between the first intermediate electrode and the second distal end further forming the first outer diameter of the coil and reverse winding back toward the proximal end to form the second intermediate electrode on the first outer diameter of the coil.
13. The implantable lead of claim 1, wherein the coil member further includes a second wound conductor, a second distal end, disposed distal to the first distal end, and a second reverse wound electrode; the second conductor including an outer insulative layer and winding from the proximal end to the second distal end further forming the first outer diameter of the coil and reverse winding back toward the proximal end to form the second electrode on the first outer diameter of the coil.
14. The implantable lead of claim 1, further comprising an insulated cable conductor and an electrode tip positioned at a second distal end, the second distal end disposed distal to the first distal end; wherein the cable conductor is disposed within the coil member extending from the proximal end to the second distal end and coupled to the electrode tip.
15. The implantable lead of claim 14, wherein a length of the electrode is between approximately 2 mm and 3 cm.
16. The implantable lead of claim 14, wherein a length of the electrode is between approximately 3 cm and 6 cm.
17. The implantable lead of claim 14, wherein the electrode serves as a pacing and sensing anode.
18. The implantable lead of claim 14, wherein the electrode serves as a defibrillation electrode.
19. The implantable lead of claim 14, wherein the insulative sheath includes an outer diameter and the electrode forms a second outer diameter of the coil member, the second outer diameter substantially equivalent to the outer diameter of the insulative sheath.
20. The implantable lead of claim 14, wherein the coil member further includes a second wound conductor and a first reverse wound intermediate electrode; the second conductor including an outer insulative layer and winding from the proximal end to a position in between the first distal end and the second distal end further forming the first outer diameter of the coil and reverse winding back toward the proximal end forming the first intermediate electrode on the first outer diameter of the coil.
21. The implantable lead of claim 20, wherein the coil member further includes a third wound conductor and a second reverse wound intermediate electrode; the third conductor including an outer insulative layer and winding from the proximal end to a position in between the first intermediate electrode and the second distal end further forming the first outer diameter of the coil and reverse winding back toward the proximal end forming the second intermediate electrode on the first outer diameter of the coil.
22. An implantable lead comprising,
an insulative sheath including an outer diameter;
an electrode tip;
a coil member extending through the insulative sheath including a first wound conductor, a second wound conductor, a proximal end, a first distal end, a second distal end, an reverse wound electrode, a first outer diameter and a second outer diameter;
an inner tubing forming a lumen and extending within the coil from the proximal end to the second distal end; and
a fiber core extending within the lumen from the proximal end to the second distal end where it is joined to the electrode tip;
wherein the first conductor winds from the proximal end to the first distal end forming the first outer diameter of the coil and reverse winds back toward the proximal end forming the electrode on the outer diameter of the coil, the electrode disposed adjacent and distal to the insulative sheath and forming the second outer diameter of the coil substantially equal to the outer diameter of the sheath;
the second conductor includes an outer insulative layer and winds from the proximal end to the second distal end, the second distal end disposed distal to the first distal end, further forming, proximal to the first distal end, the outer diameter of the coil; and
the second conductor coupled to the electrode tip at the second distal end.
23. A method of manufacturing an implantable lead comprising the steps of:
winding a conductor to form a coil member, the coil member including a proximal end, a distal end, and an outer diameter; and
reverse winding the conductor from the distal end back toward the proximal end over the outer diameter of the coil member.

1. A variable data transfer method for isochronously transferring data within a predetermined time on the IEEE 1394 bus, comprising the steps of:
(a) determining that isochronous transfer of data is terminated when the bus is in an idle state for a time interval longer than an isochronous gap period and detecting a residual gap having a first predetermined time interval which is larger than the time interval of the isochronous gap and smaller than the time interval of a subaction gap:
(b) determining whether the detected gap is an isochronous reset gap having a second predetermined time interval which is larger than the first predetermined time interval and smaller than the time interval of the subaction gap;
(c) enabling an isochronous arbitration reset bit when the detected gap is determined to be the isochronous reset gap in the determination step;
(d) determining whether the isochronous reset bit is enabled when it is determined that the detected gap is not the isochronous reset gap in the determination step and proceeding the process to an asynchronous phase;
(e) determining whether real-time transfer packets exist;
(f) checking timing when real-time transfer packets exist in the step (e), throwing away the packets which deviate from a real-time reference, and
transferring the packets which do not deviate from the real-time reference;
(g) determining whether bandwidth is sufficient with respect to packets which are not real-time packets and packets which are real-time packets and do not deviate from the real-time reference, and performing arbitration with respect to real time packets and packets which are not real-time;
(h) transferring the packets when the arbitration is successful; and
(i) transiting a phase to the asynchronous phase.
2. The method of claim 1, further comprising the steps of:
(a) disabling an isochronous arbitration reset bit after the step (h); and
(b) moving a channel to an arbitrary bit rate (ABR) channel.
3. An isochronous data transfer apparatus for isochronously transferring data within a predetermined time interval on the IEEE 1394 bus, comprising:
means for determining that isochronous transfer of data is terminated when the bus is in an idle state for a time interval longer than an isochronous gap period and detecting a residual gap having a first predetermined time interval which is larger than the time interval of the isochronous gap and smaller than the time interval of a subaction gap;
means for determining whether the detected gap is an isochronous reset gap having a second predetermined time interval which is larger than the first predetermined time interval and smaller than the time interval of the subaction gap;
means for enabling an isochronous arbitration reset bit when the detected gap is determined to be the isochronous reset gap by the detection means;
means for determining whether the isochronous reset bit is enabled when it is determined that the detected gap is not the isochronous reset gap by the determination means and driving an asynchronous transfer mode when the isochronous reset bit is not enabled;
means for determining whether real-time transfer packets exist;
means for checking timing when real-time transfer packets exist, throwing away the packets which deviate from a real-time reference, and transferring the packets which do not deviate from the real-time reference;
means for determining whether bandwidth is sufficient with respect to packets which are not real-time packets and packets which are real-time packets and do not deviate from the real-time reference;
means for transferring the packets when the arbitration is successful; and
means for performing asynchronous transfer of data.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of paying for postage stamps, comprising the steps of:
generating a plurality of postage stamps, using a supplier processor, wherein each of the stamps has a postage value and a unique identification code which is indicative of the value of the plurality of stamps; and
debiting an account, using a carrier processor for the value of the plurality of stamps when a carrier identifies one of the plurality of stamps using the unique identification code.
2. The method claimed in claim 1, wherein the unique identification code is an Information Based Indicia.
3. The method claimed in claim 2, wherein the Information Based Indicia includes a meter number.
4. The method claimed in claim 2, wherein the Information Based Indicia includes a user number.
5. The method claimed in claim 2, wherein the Information Based Indicia includes a piece count.
6. The method claimed in claim 1, wherein the postage stamps are customized.
7. The method claimed in claim 1, wherein the account is contained in a meter.
8. The method claimed in claim 1, further including the step of:
debiting the account that generated the plurality of stamps after a predetermined length of time if the carrier has not processed one of the plurality of stamps.
9. The method claimed in claim 8, wherein the predetermined length of time begins when the plurality of stamps have been sold.
10. The method claimed in claim 8, wherein the predetermined length of time begins when the plurality of stamps have been generated.
11. The method claimed in claim 1, wherein the plurality of postage stamps, have different values.
12. The method claimed in claim 1, wherein the plurality of postage stamps, are first class stamps.
13. The method claimed in claim 1, wherein the plurality of postage stamps, are forever stamps.
14. A postage stamp payment system, comprising:
a supplier processor that generates a plurality of postage stamps, wherein each of the stamps has a postage value and a unique identification code which is indicative of the value of the plurality of stamps; and
a carrier processor that debits an account for the postage value of the plurality of stamps when a carrier identifies one of the plurality of stamps using the unique identification code.