Author: claimsbot

1. A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, wherein the co-processor has been configured to implement an instruction set comprising one or more co-processor instructions, the method comprising the steps of:
issuing a co-processor instruction to the co-processor;
determining whether the instruction is mapped to the co-processor;
for an instruction not mapped to the co-processor instruction set, evaluating the need for reconfiguring the co-processor based on performance;
reconfiguring the instruction set of the co-processor when the evaluation indicates said reconfiguration is needed; and
executing the instruction.
2. The method of claim 1, wherein reconfiguring the co-processor instruction set comprises the steps of:
raising a stall signal to delay the main processor;
determining whether there is enough space in the co-processor for the unmapped instruction;
adding the unmapped instruction to the co-processor instruction set, if there is enough space for said instruction; and
clearing the stall signal.
3. The method of claim 2, further comprising the step of, for the case where there is insufficient space for the unmapped instruction, invalidating one or more instructions in the co-processor instruction set.
4. The method of claim 1, further comprising the step of measuring the occurrence of the co-processor instruction in either hardware or software, and determining whether to trigger reconfiguration of the co-processor instruction set by comparing an occurrence of an unmapped instruction to that of one or more mapped instructions.
5. The method of claim 4, wherein measuring the occurrence of the co-processor instruction comprises the steps of:
providing the co-processor instruction with a performance counter;
initializing said performance counter when said co-processor instruction is issued to the co-processor;
incrementing said performance counter when a co-processor miss occurs;
decrementing said performance counter when a different co-processor instruction is issued to the co-processor instruction; and
zeroing said performance counter when said instruction is removed from the co-processor.
6. The method of claim 5, wherein the determination to trigger reconfiguration is based on whether the performance counter of the unmapped instruction exceeds that of a mapped instruction of equal or greater size, or whether the performance counter of the unmapped instruction exceeds a sum of performance counters of those instructions that will be removed to free enough co-processor space to map the unmapped instruction.
7. The method of claim 1, further comprising the step of, for an instruction not implemented in the co-processor instruction set, bouncing the instruction back to the main processor, and emulating the bounced instruction in software.
8. The method of claim 1, further comprising the steps of locking one or more instructions of the co-processor instruction set, whereby said locking can be performed at either design time or at run-time, wherein said locked instructions are protected during reconfiguration of the co-processor, changing the locking state of a mapped, co-processor instruction, and comparing an occurrence of the mapped, unlocked co-processor instructions with un-mapped co-processor instructions in order to determine whether to trigger co-processor reconfiguration.
9. The method of claim 1, further comprising the steps of partitioning the reconfigurable co-processor into tiles, either logically or physically, wherein each co-processor instruction can occupy one or more tiles, and providing a co-processor instruction with one or more implementation options to allow mapping of said instruction onto different tiles of the co-processor.
10. A method for adaptive runtime reconfiguration of a co-processor instruction set, the method comprising the steps of:
providing a main processor and at least one reconfigurable co-processor that are communicatively connected to each other, configuring the co-processor to implement an instruction set comprising one or more co-processor instructions;
partitioning the reconfigurable co-processor into tiles, either logically or physically, wherein each co-processor instruction can occupy one or more tiles, and providing each co-processor instruction with one or more implementation options to allow mapping of said instruction onto different tiles of the co-processor. fetching, by the main processor, an instruction for execution;
at least partially decoding the instruction and determining whether the instruction is a valid co-processor instruction;
for a valid co-processor instruction, issuing the co-processor instruction to the co-processor;
determining whether the instruction is mapped to the co-processor;
for an instruction not mapped to the co-processor instruction set, raising a stall signal to delay the main processor;
determining whether there is enough space in the co-processor for the unmapped instruction;
adding the unmapped instruction to the co-processor instruction set, if there is sufficient space, otherwise invalidating one or more instructions in the co-processor instruction set;
clearing the stall signal; and
executing the instruction.
11. The method of claim 10, further comprising the step of measuring the occurrence of each co-processor instruction, said measuring comprising the steps of:
providing each co-processor instruction with a performance counter;
initializing a performance counter to an initial value when the corresponding co-processor instruction is issued to the co-processor;
incrementing the value of said performance counter by an increment value when said co-processor instruction is targeted to the co-processor but is not mapped to the co-processor;
decrementing the value of said performance counter by a decrement value when an issued co-processor instruction is targeting a different co-processor instruction, wherein said performance counter has a minimum value of zero; and
zeroing said performance counter when said instruction is removed from the co-processor,
wherein the initial value, increment value, and decrement value can be set andor modified under software control individually for each said performance counter corresponding to a co-processor instruction; and
wherein, when there is insufficient space in the co-processor for the unmapped instruction, determining whether to trigger reconfiguration of the co-processor instruction set by comparing the value of the performance counter of the unmapped instruction to that of one or more mapped instructions.
12. The method of claim 11, further comprising the steps of,
bouncing the instruction back to the main processor and emulating the bounced instruction in software, for an instruction not implemented in the co-processor instruction set;
locking one or more instructions of the co-processor instruction set, whereby said locking can be performed at either design time or at run-time, wherein said locked instructions are protected during reconfiguration of the co-processor; and
changing the locking state of a mapped, co-processor instruction, and comparing the performance counters of the mapped, unlocked co-processor instructions with those of un-mapped co-processor instructions in order to determine whether to trigger co-processor reconfiguration;
13. A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, the method comprising the steps of:
configuring the co-processor to implement an instruction set comprising one or more co-processor instructions,
issuing a co-processor instruction to the co-processor;
determining whether the instruction is implemented in the co-processor; and for an instruction not implemented in the co-processor instruction set,
raising a stall signal to delay the main processor;
determining whether there is enough space in the co-processor for the non-implemented instruction;
reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set, if there is enough space for said instruction;
clearing the stall signal; and
executing the instruction.
14. The method of claim 13, further comprising the step of, for the case where there is insufficient space for the non-implemented instruction, invalidating one or more instructions in the co-processor instruction set.
15. The method of claim 13, further comprising the step of, for an instruction not implemented in the co-processor instruction set, bouncing the instruction back to the main processor, and emulating the bounced instruction in software.
16. The method of claim 13, further comprising the step of measuring the occurrence of each co-processor instruction, wherein said measuring comprises the steps of:
providing a co-processor instruction with a performance counter;
initializing said performance counter when said co-processor instruction is mapped to the co-processor, or issued to the co-processor when mapped to the co-processor;
incrementing said performance counter when said co-processor instruction is issued to the co-processor without being mapped to the co-processor;
decrementing said performance counter when a different co-processor instruction is issued to the co-processor, wherein said performance counter has a minimum value of zero; and
zeroing said performance counter when said instruction is removed from the co-processor.
17. The method of claim 16, further comprising the step of comparing an occurrence of an unmapped instruction to that of one or more mapped instructions and determining whether to trigger reconfiguration of the co-processor instruction set, wherein said determination is based on whether the performance counter of the unmapped instruction exceeds that of a mapped instruction of equal or greater size, or whether the performance counter of the unmapped instruction exceeds a sum of performance counters of those instructions that will be removed to free enough co-processor space to map the unmapped instruction.
18. The method of claim 16, further comprising the step of locking one or more instructions of the co-processor instruction set, whereby said locking can be performed at either design time or at run-time, wherein said locked instructions are protected during reconfiguration of the co-processor.
19. The method of claim 18, further comprising the steps of changing the locking state of a mapped, co-processor instruction, and comparing the performance counters of mapped, unlocked co-processor instructions with un-mapped co-processor instructions in order to determine whether to trigger co-processor reconfiguration.
20. The method of claim 1, further comprising the step of partitioning the reconfigurable co-processor into tiles, either logically or physically, wherein each co-processor instruction can occupy one or more tiles, and wherein a co-processor instruction is provided with one or more implementation options to allow mapping of said instruction onto different tiles of the co-processor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method comprising:
generating, by a computer, a model of a website using user interaction primitives to represent hierarchical and hypertextual structures of the website;
generating, by the computer, a linear aural flow of content of the website based upon the model and a set of user constraints;
audibly presenting, by the computer, the linear aural flow of the content such that the linear aural flow of content is controlled through the use of user supplied primitives,
wherein, the linear aural flow can be turned into a dynamic aural flow based upon the user supplied primitives.
2. The method of claim 1 wherein user supplied primitives comprises a spoken command.
3. The method of claim 1 wherein the linear aural flow is further based on a ranking of current topics based upon each topic’s page hits the website has received.
4. The method of claim 2 wherein interrupted audibly presented content is bookmarked such that the bookmark ages over a user stated period and is eliminated upon an ending of a user stated period.
5. The method of claim 1 wherein the set of user constraints is derived from a user’s past audio browsing history in conjunction with the device used to perform the past audio browsing.
6. The method of claim 1 wherein the user supplied primitives are interpreted in context of a user’s session.
7. The method of claim 1 wherein the linear aural flow sequences individual articles into dialogues for audio presentation including a dialog for an article’s headline, a dialog for the article’s summary, and a dialog for the article’s content.
8. The method of claim 2 wherein a spoken command is a name of a category of content available on the website.
9. The method of claim 1 wherein the set of user constraints is derived from popularity measures of articles present on the website.
10. A computer storage medium encoded with a computer program, the program comprising instructions that when executed by a user device cause the user device to perform operations comprising:
receiving a model of a website, the model representing hierarchical and hypertextual structures of the website, wherein the model uses user interaction primitives to represent the hierarchical and the hypertextual structures of the website;
receiving a set of user derived constraints;
generating a linear aural flow of content of the website based upon the model and a set of user derived constraints;
audibly presenting the linear aural flow of the content;
determining whether a user command indicates a desire for a dynamic aural flow;
upon determining that a user command indicates a desire for a dynamic aural flow, audibly presenting a dynamic aural flow.
11. The method of claim 10, wherein interrupted audibly presented content is bookmarked such that the bookmark ages over a user stated period and is eliminated upon an ending of a user stated period.
12. The method of claim 10 wherein the set of user constraints is derived in part from a user’s past audio browsing history in conjunction with the device used to perform the past audio browsing.
13. A system comprising:
a user device;
one or more computers operable to interact with the device;
instructions stored on a machine readable storage device for execution by the one or more computers, wherein upon execution the instructions cause the one or more computers to perform the operations of:
generate a model of a website, the model representing hierarchical and hypertextual structures of the website through usage of user interaction primitives;
generate a linear aural flow of content of the website based upon the model and a set of user constraints;
provide instructions to the user device causing the user device to audibly present the linear aural flow of the content;
upon receiving input from a user, provide instructions to the user device causing the user device to audibly present a dynamic aural flow of the content.
14. The system of claim 13, wherein the one or more computers comprise the user device.
15. The system of claim 13, wherein the linear aural flow is further based on a ranking of current topics based upon each topic’s page hits the website has received.
16. The system of claim 13, wherein the one or more computers comprise a server operable to interact with the device through a data communication network, and the user device is operable to interact with the server as a client.
17. The system of claim 13, wherein the one or more computers consist of one computer, the user device is a user interface device, and the one computer comprises the user interface device.

1. A digital duty cycle correction (DCC) circuit, comprising:
a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and
a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.
2. The duty cycle correction circuit of claim 1, wherein the first conversion circuit comprises:
a first inverter for converting the internal clock into the first clock;
a second inverter for converting the internal clock into the second clock;
a capacitor for supplying the voltage to the second terminal, that is, an output of the second inverter; and
a logic element for combining the first clock and an output of the second inverter and outputting the third clock.
3. The duty cycle correction circuit of claim 1, wherein the second conversion circuit comprises a flip-flop for generating the output clock by using the third clock and the first signal as inputs.
4. The duty cycle correction circuit of claim 2, wherein the first conversion circuit further comprises a capacitor for supplying a second voltage different from the voltage to the second terminal, that is, an output of the second inverter.
5. The duty cycle correction circuit of claim 1, wherein the voltage supplied to the second terminal through the capacitor is generated by:
a phase divider for generating second and third signals having opposite phases in response to the output clock from the second conversion circuit;
a compare control unit for generating a pump reset signal and a compare control signal in response to the output clock;

a duty cycle correction pump for pumping the second and third signals and generating a first pumping clock and a second pumping clock, in response to the pump reset signal;
a voltage comparator for sensing the compare control signal and voltage levels of the first and second pumping clocks, and generating an incrementdecrement signal;

a counter for outputting a counter signal in response to the incrementdecrement signal; and
a voltage generator operating in response to the counter signal.
6. The duty cycle correction circuit of claim 5, wherein the duty cycle correction pump determines duty mismatch by comparing the first clock and the second clock, pumps the first clock and the second clock to a specific level or more or less, and outputs the first pumping clock and the second pumping clock.
7. The duty cycle correction circuit of claim 5, wherein the voltage comparator determines a level of an increase or decrease of a high pulse width by comparing levels of the first pumping clock and the second pumping clock in response to the compare control signal, and outputs a signal that increases or decreases to the counter.
8. The duty cycle correction circuit of claim 7, wherein the voltage comparator outputs the increment signal when the level of the first pumping clock is higher than a specific level, and outputs the decrement signal when the level of the first pumping clock is lower than a specific level.
9. The duty cycle correction circuit of claim 5, wherein the counter converts bits of the increment and decrement signals into a binary number, and outputs a converted binary number as the counter signal.
10. A digital duty cycle correction (DCC) circuit of a delay locked loop (DLL), comprising:
a duty correction circuit for correcting a duty of a internal clock and outputting an output clock;
a phase divider for generating a first clock having the same phase as that of the output clock and a second clock having an opposite phase to that of the first clock in response to the output clock;
a compare control unit for generating a pump reset signal and a compare control signal in response to the output clock;
a DCC pump for pumping the first clock and the second clock and generating a first pumping clock and a second pumping clock in response to a pump reset signal;
a voltage comparator for sensing the compare control signal and the voltage levels of the first pumping clock and the second pumping clock and generating an incrementdecrement signal;
a counter for outputting a counter signal in response to the incrementdecrement signal; and
a voltage generator for generating a voltage in response to the counter signal.
11. The digital duty cycle correction circuit of claim 10, wherein the duty correction circuit comprises:
a buffer unit for receiving the internal clock, buffering the received internal clock, and outputting a first input clock and a second input clock;
a delay control unit for controlling the delay of the second input clock according to the at least one voltage generated by the voltage generator, and generating a delay signal;
a NAND gate for outputting a first logic signal in response to the first input clock and the delay signal; and
a flip-flop unit for generating an output clock having a corrected duty cycle in response to the first logic signal and the delay signal.
12. The digital duty cycle correction circuit of claim 11, wherein the delay control unit comprises a plurality of capacitors.
13. The digital duty cycle correction circuit of claim 12, wherein the plurality of capacitors are formed of metal oxide semiconductor (MOS) transistors.
14. The digital duty cycle correction circuit of claim 11, wherein the flip-flop unit comprises:
a first NAND gate for generating a second logic signal in response to the delay signal and the output clock; and
a second NAND gate for generating the output clock in response to the first logic signal and the second logic signal.
15. The digital duty cycle correction circuit of claim 10, wherein the DCC pump receives the first and second clocks, determines duty cycle mismatch, pumps the first and second clocks to a specific level, and outputs the first pumping clock and the second pumping clock.
16. The digital duty cycle correction circuit of claim 10, wherein the voltage comparator compares levels of the first and second pumping clocks applied thereto, determines an increase or reduction of a pulse width, and outputs the incrementdecrement signal representing an increase or a decrease, in response to the compare control signal.
17. The digital duty cycle correction circuit of claim 16, wherein the voltage comparator outputs the incrementdecrement signal representing an increase when the first pumping clock applied thereto is higher than a specific level, and outputs the incrementdecrement signal representing a decrease when the first pumping clock applied thereto is lower than the specific level.
18. The digital duty cycle correction circuit of claim 10, wherein the counter converts the incrementdecrement signal into a binary number and outputs the result as the counter signal.
19. The digital duty cycle correction circuit of claim 10, wherein the compare control unit outputs a first control signal and a second control signal in order to control a delay time of the duty correction circuit.
20. The digital duty cycle correction circuit of claim 10, wherein the voltage generator generates one or more voltages in order to control an amount of correction of the duty correction circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A nuclear magnetic resonance imaging radio frequency receiver the receiver being adapted to receive analogue signals from at least one radio frequency receiver coil unit, the radio frequency receiver comprising:
an analogue-digital converter for converting the analogue pre-amplified magnetic resonance signal into a digital signal,
means for digital down converting the digital signal and
a first communication interface adapted for transmitting the down converted digital signal via a communication link.
2. The receiver of claim 1, further comprising a local clock oscillator.
3. The receiver of claim 2, wherein the local clock oscillator is synchronizable by a pilot tone signal, the pilot tone signal being generated by a pilot tone transmit coil or wherein the local clock oscillator is synchronizable by a system clock.
4. The receiver of claim 1, further comprising means for encoding andor compressing the down converted digital signal.
5. The receiver of claim 1, wherein the receiver is comprised in the radio frequency receiver coil unit.
6. The receiver of claim 1, further comprising merging means, wherein the merging means are adapted to combine multiple digitized magnetic resonance signals and control and status signals for controlling the receiver, the multiple digitized magnetic resonance signals originating from multiple antenna elements of the receiver coil unit.
7. The receiver of claim 1, further comprising an electronic testing circuit, wherein the electronic test circuit is adapted for examining the electronic components of the radio frequency receiver, wherein the examination is being performable using a test coil, said test coil being adapted in the radio frequency receiver coil unit.
8. The receiver of claim 1, further comprising means for spike detection and removal in the digitized radio frequency signal.
9. The receiver of claim 1, wherein the first communication interface is adapted for providing the digitized signal via the communication link by wireless radio frequency transmission or optical transmission or wired transmission.
10. A magnetic resonance imaging apparatus, comprising a nuclear magnetic resonance imaging radio frequency receiver according to any of the previous claims, the apparatus further comprising:
at least one radio frequency receiver coil unit,
a main magnet adapted for generating a main magnetic field,
magnetic field gradient coils adapted for selectively generating magnetic field gradients to be superimposed to the main magnetic field,
a radio frequency transmit coil for generating a radio frequency pulse sequence
a second communication interface, said second communication interface being adapted for communication with the first communication interface and
a control and data acquisition system, wherein the control and data acquisition system is adapted for communicating with the receiver using the second communication interface.
11. An RF interface structure for a magnetic resonance imaging system comprising:
at least one receiver according to claim 1,
a second communication interface, said second communication interface being adapted for communication with the first communication interface of the receiver
merging means, wherein the merging means are adapted to combine multiple signals being communicated over multiple second communication interfaces, said multiple signals being communicated to or from multiple radio frequency receiver coil units using multiple receivers,
a radio frequency scan control unit, said radio frequency scan control unit being adapted for controlling the at least one receiver.
12. A control and data acquisition system comprising means for generation of pulse sequences andor control commands, said pulse sequences andor control commands being adapted to control an RF interface structure, said slave system comprising a receiver according to claim 1.
13. A method for receiving a radio frequency signal from a magnetic resonance imaging receiver coil unit, the method comprising:
receiving an analogue pre-amplified magnetic resonance signal from the receiver coil unit,
converting the analogue signal into a digital signal,
digital down converting the digital signal and
communicating the digital down converted signal over a first communication interface.