Author: claimsbot

1. A method comprising:
manufacturing a CMOS image sensor having a test pattern for testing an active area of a unit pixel, said manufacturing including:
a) forming a FOX area on a predetermined location of a semiconductor substrate, thereby defining a first active area of a unit pixel part and a second active area of a test pattern part;
b) forming a gate structure in the unit pixel part and a first blocking pad in the test pattern part, the first blocking pad having a pair of sub-blocking pads which are separated by a predetermined distance from each other;
c) carrying out a first ion implantation process so as to form a first ion implantation region corresponding to a deep n-type impurity region of a photodiode and lightly doped drains of transistors in the unit pixel by using the first blocking pad of the test pattern part and the gate structure of the unit pixel part as masks;
d) forming a second blocking pad between the pair of sub-blocking pads in the test pattern;
e) carrying out a second ion implantation process by using the first and the second blocking pads of the test pattern part and the gate structure of the unit pixel part as another masks so as to form a second ion implantation region corresponding to a shallow p-type impurity region of the photodiode and sourcedrain regions of the transistors in the unit pixel; and
f) forming a test pad having a first and a second test pads which is electrically connected to at least one contact, the test pad for measuring the sheet resistivity of the ion implantation region.
2. The method as recited in claim 1, wherein the step b) includes the steps of:
b1) forming a first insulating layer and a conductive layer on the semiconductor substrate; and
b2) patterning the conductive layer and the first insulating layer into a predetermined configuration, to thereby form the gate structure in the unit pixel part and the first blocking pad in the test pattern part.
3. The method as recited in claim 2, wherein the conductive layer uses a polysilicon.
4. The method as recited in claim 1, wherein the step d) includes the steps of:
d1) forming a second insulating layer on the first blocking pad and an exposed surface of the semiconductor substrate; and
d2) anisotropically etching the second insulating layer, thereby forming spacers and the second blocking pad.
5. The method as recited in claim 4, wherein the second insulating layer uses an oxide or a nitride.
6. The method as recited in claim 1, wherein the first ion implantation region in the test pattern part is correspondent to a deep n-type impurity region of a photodiode or LDDs of a transistor.
7. The method as recited in claim 1, wherein the second ion implantation region in the test pattern part is correspondent to a shallow p-type impurity region and a sourcedrain region of the transistor.
8. The method as recited in claim 1, wherein the distance is shorter than two times the width of the spacer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An information processing device for carrying out a process based on at least one image selected by a user from among a plurality of images displayed on a display screen, comprising:
a trajectory obtaining unit that obtains a trajectory of a position on the display screen, the position being designated by the user;
a determination unit that determines images among the plurality of images, the determined images being surrounded by the trajectory obtained by the trajectory obtaining unit;
a surrounding number of times obtaining unit that obtains a number of times that the determined images are surrounded by the obtained trajectory; and
an image selection unit that selects a number of the images that corresponds to the obtained number of times, from among the images determined to be surrounded by the obtained trajectory.
2. The information processing device according to claim 1, wherein the image selection unit selects the number of the images that corresponds to the obtained number of times from among the determined images surrounded by the obtained trajectory, based on a start position or an end position of the obtained and positions of the images determined by the determination unit as being surrounded by the obtained trajectory.
3. The information processing device according to claim 2, wherein the image selection unit selects the number of the images that corresponds to the obtained number of times from among the determined images surrounded by the obtained trajectory beginning with an image having the shortest distance from the start position or the end position of the obtained trajectory.
4. A control method for controlling an information processing device having a processor for carrying out a process based on at least one image selected by a user from among a plurality of images displayed on a display screen, the control method comprising:
obtaining by the processor a trajectory of a position on the display screen, the position being designated by the user;
determining by the processor images among the plurality of images, the images being surrounded by the obtained trajectory;
obtaining by the processor a number of times the determined images are surrounded by the obtained trajectory; and
selecting by the processor a number of images, the number corresponding to the obtained number of times from among the determined images surrounded by the obtained trajectory.
5. A non-transitory computer readable information storage medium storing a program for causing a computer to function as an information processing device for carrying out a process based on at least one image selected by a user from among a plurality of images displayed on a display screen, the program causing the computer to:
obtain a trajectory of a position on the display screen, the position being designated by the user;
determine images from among the plurality of images, the images being surrounded by the obtained trajectory;
obtain a number of times the determined images are surrounded by the obtained trajectory; and
select a number of images, the number corresponding to the obtained number of times from among the determined images surrounded by the obtained trajectory.

1. A method for reducing static power consumption of a processor, comprising:
comparing a cost of entering into and recovering from a nap mode with the cost of not entering the nap mode;
if the cost of entering into and recovering from the nap mode is less than the cost of not entering the nap mode,
halting an instruction-processing portion of the processor, and
reducing a voltage supplied to the instruction-processing portion of the processor, while maintaining full voltage to a second portion of the processor;

whereby the second portion of the processor can continue to operate while the instruction-processing portion of the processor is in a reduced power mode.
2. The method of claim 1, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to a minimum value that maintains state information within the instruction-processing portion of the processor.
3. The method of claim 1, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to zero.
4. The method of claim 3, further comprising saving state information from the instruction-processing portion of the processor prior to reducing the voltage supplied to the instruction-processing portion of the processor, wherein saving state information includes saving state information to one of, the second portion of the processor and a main memory.
5. The method of claim 4, wherein upon receiving a wakeup signal the method further comprises:
restoring full voltage to the instruction-processing portion of the processor;
restoring state information to the instruction-processing portion of the processor; and
resuming processing of computer instructions.
6. The method of claim 1, wherein maintaining full voltage to the second portion of the processor involves maintaining full voltage to a snoop-logic portion of the processor, whereby the processor can continue to perform cache snooping operations while the instruction-processing portion of the processor is in the reduced power mode.
7. The method of claim 1, further comprising reducing the voltage to a cache memory portion of the processor upon receiving the signal.
8. The method of claim 7, further comprising writing cache memory data to main memory prior to reducing the voltage.
9. The method of claim 1, wherein the second portion of the processor includes a control portion of the processor that includes interrupt and clock circuitry.
10. The method of claim 1, wherein the second portion of the processor includes a cache memory portion of the processor.
11. An apparatus, for reducing static power consumption of a processor, comprising:
a comparison mechanism that is configured to compare a cost of entering into and recovering from a nap mode with the cost of not entering the nap mode;
a halting mechanism that is configured to halt an instruction-processing portion of the processor; and
a voltage reducing mechanism that is configured to reduce a voltage supplied to the instruction-processing portion of the processor, while maintaining full voltage to a second portion of the processor;
wherein if the cost of entering into and recovering from the nap mode is less than the cost of not entering the nap mode the halting mechanism is configured to halt an instruction-processing portion of the processor and the voltage-reducing mechanism is configured to reduce the voltage supplied to the instruction-processing portion of the processor;
whereby the second portion of the processor can continue to operate while the instruction-processing portion of the processor is in a reduced power mode.
12. The apparatus of claim 11, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to a minimum value that maintains state information within the instruction-processing portion of the processor.
13. The apparatus of claim 11, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to zero.
14. The apparatus of claim 13, further comprising a saving mechanism that is configured to save state information from the instruction-processing portion of the processor prior to reducing the voltage supplied to the instruction-processing portion of the processor, wherein saving state information includes saving state information to one of, the second portion of the processor and a main memory.
15. The apparatus of claim 14, further comprising:
a voltage restoring mechanism that is configured to restore full voltage to the instruction-processing portion of the processor;
a state restoring mechanism that is configured to restore state information to the instruction-processing portion of the processor; and
a resuming mechanism that is configured to resume processing of computer instructions.
16. The apparatus of claim 11, wherein maintaining full voltage to the second portion of the processor involves maintaining full voltage to a snoop-logic portion of the processor, whereby the processor can continue to perform cache snooping operations while the instruction-processing portion of the processor is in the reduced power mode.
17. The apparatus of claim 11, wherein the voltage reducing mechanism is further configured to reduce the voltage to a cache memory portion of the processor upon receiving the signal.
18. The apparatus of claim 17, further comprising a writing mechanism that is configured to write cache memory data to main memory prior to reducing the voltage.
19. The apparatus of claim 11, wherein the second portion of the processor includes a control portion of the processor that includes interrupt and clock circuitry.
20. (canceled)
21. A method for reducing static power consumption of a processor, comprising:
receiving a signal indicating that instruction execution within the processor is to be temporarily halted; and
in response to the signal,
halting an instruction-processing portion of the processor, and
reducing a voltage supplied to the instruction-processing portion of the processor, while maintaining full voltage to a second portion of the processor, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to a value that will maintain state information within the instruction-processing portion of the processor but which is not sufficient to allow processing to continue;

whereby the second portion of the processor can continue to operate while the instruction-processing portion of the processor is in a reduced power mode.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A seed of hybrid maize variety X8H565, produced by crossing a first plant of variety PH12 KP with a second plant of variety PHVRZ, wherein representative seed of said varieties PH12 KP and PHVRZ have been deposited under ATCC Accession Number PTA-12653 and PTA-11865, respectively.
2. A plant or plant part produced by growing the seed of the hybrid maize variety of claim 1.
3. A method for producing a second maize plant comprising applying plant breeding techniques to a first maize plant, or parts thereof, wherein said first maize plant is the maize plant of claim 2, and wherein application of said techniques results in the production of said second maize plant.
4. The method of claim 3, further defined as producing an inbred maize plant derived from hybrid maize variety X8H565, the method comprising the steps of:
(a) crossing said first maize plant with itself or another maize plant to produce seed of a subsequent generation; and
(b) harvesting and planting the seed of the subsequent generation to produce at least one plant of the subsequent generation; and
(c) repeating steps (a) and (b) for an additional 2-10 generations to produce an inbred maize plant derived from hybrid maize variety X8H565.
5. The method of claim 3, further defined as producing an inbred maize plant derived from hybrid maize variety X8H565, the method comprising the steps of:
(a) crossing said first maize plant with an inducer variety to produce haploid seed; and
(b) doubling the haploid seed to produce an inbred maize plant derived from hybrid maize variety X8H565.
6. A seed of hybrid maize variety X8H565 further comprising a locus conversion, wherein said seed is produced by crossing a first plant of variety PH12 KP with a second plant of variety PHVRZ; wherein representative seed of said varieties PH12 KP and PHVRZ have been deposited under ATCC Accession Number PTA-12653 and PTA-11865, respectively; and wherein at least one of said varieties PH12 KP and PHVRZ further comprises a locus conversion.
7. The seed of claim 6, wherein the locus conversion confers a trait selected from the group consisting of male sterility, site-specific recombination, abiotic stress tolerance, altered phosphorus, altered antioxidants, altered fatty acids, altered essential amino acids, altered carbohydrates, herbicide tolerance, insect resistance and disease resistance.
8. A plant or plant part produced by growing the seed of the maize hybrid variety of claim 6.
9. A method for producing a second maize plant comprising applying plant breeding techniques to a first maize plant, or parts thereof, wherein said first maize plant is the maize plant of claim 8, and wherein application of said techniques results in the production of said second maize plant.
10. The method of claim 9, further defined as producing an inbred maize plant derived from hybrid maize variety X8H565, the method comprising the steps of:
(a) crossing said first maize plant with itself or another maize plant to produce seed of a subsequent generation;
(b) harvesting and planting the seed of the subsequent generation to produce at least one plant of the subsequent generation; and
(c) repeating steps (a) and (b) for an additional 2-10 generations to produce an inbred maize plant derived from hybrid maize variety X8H565.
11. The method of claim 9, further defined as producing an inbred maize plant derived from hybrid maize variety X8H565, the method comprising the steps of:
(a) crossing said first maize plant with an inducer variety to produce haploid seed; and
(b) doubling the haploid seed to produce an inbred maize plant derived from hybrid maize variety X8H565.