Author: claimsbot

1. A system for transporting bulk particulate materials, comprising:
a bag including a discharge spout for holding such material;
means for transporting said bag from a first site to a second site; and
means detachably mountable on said spout for metering the discharge of material from said bag,
wherein said metering means includes an inner frusto-conically configured member and an outer frusto-conically configured member axially displaceable relative to said inner member for clamping a portion of said spout therebetween, said inner member having an outer surface against which a first portion of said spout may be drawn over and positioned, and said second outer member having an inner surface engageable with said first spout portion when drawn over and positioned on said outer surface of said inner member, for clamping said first spout portion between said inner and outer members, and at least one means for removably retaining said outer member in clamping relation with said inner member with said first spout portion disposed therebetween.
2. A system according to claim 1 wherein said outer member includes a lower annular edge around which a second portion of said spout may be turned and an outer surface against which a third portion of said spout may be drawn over and positioned, and wherein said retaining means is functional to removably retain said third spout portion positioned against said outer surface of said outer member.
3. A system according to claim 2 wherein said outer member includes an opening therethrough, a bracket disposed adjacent said opening and a threaded bolt threaded in said bracket and extendable in the direction of said opening and toward said inner member to urge a segment of said third and first spout portions against said inner member in retaining relation.
4. A system according to claim 1 wherein said metering means includes a valve.
5. A system according to claim 4 wherein said valve comprises a butterfly valve.
6. A system according to claim 1 wherein said metering means includes a hopper secured to and communicating with said inner member.
7. A system according to claim 6 wherein said hopper includes means for fluidizing material deposited therein for facilitating the flow of said material therethrough.
8. A system according to claim 7 wherein said hopper includes a frusto-conically configured impermeable wall and said fluidizing means include a permeable wall spaced inwardly relative to said impermeable wall to form a chamber therebetween and means for introducing air under pressure into said chamber.
9. A system according to claim 6 wherein said hopper is supported on said inner member.
10. A system according to claim 6 including a valve supported on said hopper communicating with a discharge outlet thereof.
11. A system according to claim 1 wherein said metering means includes an annular flange providing a support for said outer member when said outer member is not disposed in said clamping relation.
12. A system according to claim 1 wherein said metering means includes said inner and outer members, a hopper supported on said inner member and communicating with an outlet of said inner member and a valve supported on said hopper and communicating with a discharge outlet of said hopper.
13. A system according to claim 12 wherein said metering means includes an annular support flange supported on said inner member upon which said outer member may be rested.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A storage device comprising:
an ordinary data storage unit which stores encrypted contents data;
a secret data storage unit which stores license data containing a contents key for decrypting the encrypted contents data;
a cryptographic processing unit which receives, from a host device, and executes a command corresponding to each of a plurality of sequenced subprocesses produced by dividing each of a series of cryptographic input and output processes for encrypting data to be secured and inputting and outputting the data between the storage device and the host device;
a controller which inputs and outputs the license data via the cryptographic processing unit and inputs and outputs the encrypted contents data bypassing the cryptographic processing unit; and
a bus for receiving the command from the host device, the bus being deallocated for another command when the command is issued, wherein
the cryptographic processing unit receives commands corresponding to a plurality of subprocesses respectively belonging to two or more different cryptographic input and output processes via the bus, refers to identifying information attached to the command, identifies to which cryptographic input and output process the command belongs, manages the sequence of commands executed in each cryptographic input and output process, and rejects the execution of an incorrectly sequenced command when the cryptographic processing unit receives the incorrectly sequenced command.
2. The storage device according to claim 1, wherein
when the cryptographic processing unit receives the incorrectly sequenced command, the cryptographic processing unit interrupts the cryptographic input and output process to which the command belongs.
3. The storage device according to claim 1, wherein the number of the cryptographic input and output processes which can be performed simultaneously by the storage device is predetermined in accordance with a performance of the storage device.
4. The storage device according to claim 1, wherein in response to a request from the host device, the storage device provides to the host device the maximum number of cryptographic input and output processes which can be performed simultaneously by the storage device.
5. The storage device according to claim 1, wherein the storage medium comprises a normal data storing unit and a confidential data storing unit, the normal data storing unit storing normal data to be exchanged bypassing the cryptographic processing unit, the confidential data storing unit storing the secret data to be exchanged via the cryptographic processing unit.
6. A storage device comprising:
an ordinary data storage unit which stores encrypted contents data;
a secret data storage unit which stores license data containing a contents key for decrypting the encrypted contents data;
a cryptographic processing unit for receiving, from a host device, and executing a command corresponding to each of the plurality of sequenced subprocesses produced by dividing each of a series of cryptographic input and output processes for encrypting data to be secured and inputting and outputting the data between the storage device and the host device;
a controller which inputs and outputs the license data via the cryptographic processing unit and inputs and outputs the encrypted contents data bypassing the cryptographic processing unit; and
a bus for receiving the command from the host device, the bus being deallocated for another command when the command is issued,
wherein the cryptographic processing unit receives commands corresponding to a plurality of subprocesses respectively belonging to two or more different cryptographic input and output processes via the bus, refers to identifying information attached to the command, identifies to which cryptographic input and output process the received command belongs to, and rejects the execution of the command when having detected that the command is an incorrectly sequenced command in the cryptographic input and output process to which the command belongs.
7. The storage device according to claim 6, wherein in response to a request from the host device, the storage device provides to the host device the maximum number of cryptographic input and output processes which can be performed simultaneously by the storage device.
8. A host device which exchanges encrypted contents data and license data containing a contents key for decrypting the encrypted contents data, with a storage device that is capable of simultaneously performing a plurality of series of cryptographic input and output processes for encrypting data to be secured and inputting and outputting the data, the host device comprising:
a controller which divides the cryptographic input and output process into a plurality of sequenced subprocesses and issues commands sequentially to the storage device thereby allowing the storage device to execute a subprocess to be executed on the storage-device side; and
a cryptographic processing unit which carries out encryption or decryption that is required of the cryptographic input and output process, wherein
the controller inputs and outputs the license data via the cryptographic processing unit and inputs and outputs the encrypted contents data bypassing the cryptographic processing unit, and
when the controller issues a command, the controller attaches identifying information to the command to identify to which one of the plurality of cryptographic input and output processes the command belongs and to manage the sequence of commands executed in each cryptographic input and output process, and
the controller that issues the command via the bus electrically connecting the host device and the storage device deallocates the bus for another command.
9. The host device according to claim 8, wherein the controller issues a command to allocate a process system for performing the cryptographic input and output process prior to initiation of the cryptographic input and output process.
10. A data input and output method for exchanging encrypted contents data and license data containing a contents key for decrypting the encrypted contents data between a storage device and a host device, wherein, when performing a cryptographic input and output process between the host device and the storage device, which is capable of simultaneously performing a plurality of series of cryptographic input and output processes for encrypting data to be secured and inputting and outputting the data, the license data is input and output through the cryptographic input and output process, and the encrypted data is input and output bypassing the cryptographic input and output process, the method comprising:
dividing the cryptographic input and output process into a plurality of procedures and allowing the host device to execute a procedure to be executed on the host-device side out of the procedures;
allowing the host device to issue a command to the storage device via a bus for electrically connecting the host device and the storage device in order to make the storage device execute a procedure to be executed on the storage-device side;
allowing the host device to deallocate the bus for another command;
allowing the storage device to receive the command; and
allowing the storage device to execute the command, wherein
identifying information is attached to the command to identify to which one of the plurality of cryptographic input and output processes, being performed simultaneously by the storage device, the command belongs, and
the allowing the storage device to receive the command includes:
determining whether the received command is a correctly sequenced command in the cryptographic input and output process;
accepting the command successfully when the received command has been determined to be a correctly sequenced command; and
rejecting the execution of the received command when the received command has been determined to be an incorrectly sequenced command.
11. The data input and output method according to claim 10, further comprising predetermining an upper-limit number of the cryptographic input and output processes that can be performed simultaneously by the storage device in accordance with performance of the storage device.
12. The data inputoutput method according to claim 10, further comprising:
allowing the storage device to predetermine an upper-limit number of the cryptographic input and output processes that the storage device can perform simultaneously in accordance with its own performance, and
informing the host device of the upper limit.
13. The data input and output method according to claim 11, further comprising, prior to performing the cryptographic input and output processes, selecting and allocating identifying information for identifying the cryptographic input and output process to be performed from among the prepared number of pieces of identifying information determined in the determining step.
14. The data input and output method according to claim 12, further comprising, prior to performing the cryptographic input and output processes, selecting and allocating identifying information for identifying the cryptographic input and output process to be performed from among the prepared number of pieces of identifying information determined in the determining step.
15. The data input and output method according to claim 10, wherein
when the received command has been determined to be an incorrectly sequenced command, the execution of the cryptographic input and output process to which the command belongs is interrupted.

1. A device for the encoding of information symbols to transmit or to record, and the correcting errors among the symbols received or read, according to codes defined over a Galois field Fq, where q is an integer greater than 2 and equal to a power of a prime number, and in which a set of elements of Fq are considered which are denoted yl(j), where j=1, . . . ,R with 1\u2266R\u2266q\u22121 and l=0, . . . ,p\u22121 with p>1, said device comprising:
a Reed-Solomon encoder;
a Reed-Solomon decoder; and
a unit serving to calculate the inverse of a Vandermonde matrix;
registers A in which there are stored
for the encoding, said information symbols, and
for the error correction, the symbols received or read after they have been corrected;

registers S in which there are stored
for the encoding, the symbols output from said Reed-Solomon encoder, and
for the correction of errors, the symbols input to said Reed-Solomon decoder; and

registers Y in which said quantities yl(j) are stored.
2. A The device according to claim 1, in which said Reed-Solomon decoder is of length (q\u22121), and further comprising a conversion-X table placing the indices of any register of length R opposite the respective elements of the Galois field Fq.
3. The device according to claim 1 or claim 2, charaer in that which in said registers the powers yl(j)s of the symbols yl(j), where s=2, . . . ,p\u22121, are also stored.
4. The device according to claim 1 or claim 2, further comprising multiplier circuits calculating the powers yl(j)s of the symbols yl(j), where s=2, . . . ,p\u22121, after the values of those symbols have been read in the registers during the post-processing steps.
5. A The device according to claim 1 or claim 2, further comprising a state machines adapted to organize activation and deactivation of all the signals driving the encoding and error correcting operations.
6. The device according to claim 1 or claim 2, further comprising a control unit in the form of an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)
7. A The device according to claim 1 or claim 2, further comprising a control unit in the form of a data processing device capable of being controlled by a computer program.
8. A computer program, containing instructions adapted to operate said control unit of said device according to claim 7.
9. An apparatus for sending and receiving encoded digital signals, comprising means for modulating the encoded digital signals, a modulated data transmitter, a modulated data receiver, means for demodulating the encoded digital signals, means for calculating estimated information symbols from corrected received words, and a device according to claim 1 or claim 2.
10. An apparatus for recording and reading encoded digital signals, comprising means for modulating the encoded digital signals, a modulated data recorder, a modulated data reader, means for demodulating the encoded digital signals, means for calculating estimated information symbols from corrected read words, and a device according to claim 1 or claim 2.
11. A device for encoding information symbols into a linear code, and for detecting error locations and magnitudes of encoded information symbols of the linear code, comprising:
a Reed-Solomon encoder, adapted to encode information symbols into a Reed-Solomon codes;
a Reed-Solomon decoder, adapted to decode Reed-Solomon code; and
address conversion means for matching locations of the linear code to locations of the Reed-Solomon code.
12. The device according to claim 11, further comprising:
pre-processing means for processing information symbols to be input to said Reed-Solomon encoder and encoded information symbols to be input to said Reed-Solomon decoder;
post-processing means for processing symbols output from said Reed-Solomon decoder or from said Reed-Solomon encoder; and
a command unit. adapted to organize activation and deactivation of signals driving the encoding, the decoding, the pre-processing and the post-processing operations.
13. The device according to claim 11, further comprising:
a first register, adapted to store the information symbols or encoded information symbols;
a second register, adapted to store the symbols output from said Reed-Solomon encoder or the symbols input to said Reed-Solomon decoder; and
a third register, adapted to store predetermined values of the first linear code.
14. The device according to claim 12, wherein said post-processing means comprises a unit for calculating an inverse of a Vandermonde matrix.
15. The device according to any one of claims 11 to 14, wherein the linear code is an algebraic geometric code.
16. A device for encoding information symbols into a liner code, comprising:
pre-processing means for performing first operations on information symbols to be encoded and predetermined values of the linear code;
a Reed-Solomon encoder adapted to encode the pre-processed information symbols into a Reed-Solomon code and outputting encoded information symbols; and
post-processing means for performing second operations on the information symbols to be encoded, the symbols encoded by said Reed-Solomon encoder and the predetermined values of the linear code.
17. The device according to claim 16, further comprising:
a plurality of first registers each for storing the information symbols to be encoded;
a plurality of second registers each for storing information symbols encoded by said Reed-Solomon encoder; and
a plurality of third registers each for storing the predetermined values of the linear code.
18. The device according to claim 16, wherein said post-processing means comprises means for calculating an inverse of a Vandermonde matrix from values stored in the plurality of third registers.
19. The device according to claim 16, wherein the linear code is an algebraic geometric code.
20. A device for decoding encoded information symbols of a linear code, comprising:
pre-processing means for performing first operations on encoded information symbols to be decoded and predetermined values of the linear code;
a Reed-Solomon decoder, adapted to decode the pre-processed information symbols; and
post-processing means for performing second operations on the encoded information symbols to be decoded, the symbols decoded by said Reed-Solomon decoder, and the predetermined values of the linear code.
21. The device according to claim 20, further comprising:
a plurality of first registers each for storing encoded information symbols to be decoded;
a plurality of second registers each for storing decoded information symbols; and
a plurality of third registers each for storing predetermined values of the linear code.
22. The device according to claim 20, wherein said post-processing means comprises means for calculating an inverse of a Vandermonde matrix from values stored in sad the plurality of third registers.
23. The device according to claim 20, wherein the linear code is an algebraic geometric code.
24. A method for encoding information symbols into a linear code, comprising the steps of:
pre-processing the information symbols by performing first operations on the information symbols to be encoded and predetermined values of the linear code;
encoding the pre-processed information symbols into a Reed-Solomon code; and
post-processing the encoded information symbols by performing second operations on the information symbols to be encoded, the encoded information symbols. and the predetermined values of the linear code.
25. A method for decoding encoded information symbols of a linear code, comprising the steps of:
pre-processing the encoded information symbols by performing first operations on the encoded information symbols to be decoded and predetermined values of the linear code;
decoding the pre-processed symbols as a Reed-Solomon code; and
post-processing the decoded information symbols by performing second operations on the information symbols to be decoded, the decoded information symbols, and the predetermined values of the linear code.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus, comprising:
a memory configured to receive a calibration command and an attribute, comprising:
a first register configured to store a tuning data pattern; and
a second register configured to receive and store a tuning data pattern responsive, at least in part, to the memory receiving a calibration command;

wherein the memory is further configured to execute an operation on at least one of the tuning data pattern stored in the first register or the tuning data pattern stored in the second register based, at least in part, on the attribute.
2. The apparatus of claim 1, wherein the calibration command and attribute are received by the memory over a plurality of IO lines.
3. The apparatus of claim 1, further comprising:
a device coupled to the memory and configured to provide the calibration command and the attribute, the device further configured to provide a clock signal;
wherein the memory is configured to receive the clock signal, the memory further configured to execute the operation based, at least in part, on the clock signal.
4. The apparatus of claim 3, wherein the device is further configured to vary a frequency of the clock signal.
5. The apparatus of claim 1, wherein the first register comprises non-volatile memory and the second register comprises volatile memory.
6. The apparatus of claim 1, wherein the operation comprises a read volatile operation and wherein the memory is configured to provide the tuning data pattern stored in the second register after a plurality of dummy cycles have elapsed after receipt of the attribute.
7. The apparatus of claim 1, wherein the attribute corresponds to a multi-input operation.
8. The apparatus of claim 1, wherein the attribute is a non-volatile programming attribute, volatile refresh attribute, non-volatile erase attribute, read volatile attribute, or volatile program attribute.
9. The apparatus of claim 1, wherein the tuning data pattern stored in the first register is based, at least in part, on silicon processes, PCB loads, voltage variations, temperature fluctuations, or any combination thereof.
10. The apparatus of claim 1, wherein the second register is further configured to receive a plurality of tuning data patterns responsive at least in part, to the memory receiving the calibration command.
11. An apparatus, comprising:
a memory configured to receive a read command, the memory further configured to provide a tuning data pattern responsive, at least in part, to receipt of the read command and to provide the tuning data pattern after a plurality of dummy cycles have elapsed after receipt of the read command.
12. The apparatus of claim 11, wherein the memory is further configured to operate in accordance with the SPI protocol.
13. The apparatus of claim 11, wherein the memory is further configured to provide the tuning data pattern based, at least in part, on a short calibration flag.
14. The apparatus of claim 11, wherein the memory is further configured to provide data corresponding to the read command after providing the tuning data pattern.
15. The apparatus of claim 11, further comprising a bus having a plurality of IO lines and wherein the read command is provided over the plurality of IO lines.
16. The apparatus of claim 11, wherein the memory is configured to provide as plurality of tuning data patterns on a plurality of IO lines, wherein at least one of the tuning data patterns being different than another one of the tuning data patterns.
17. A method, comprising:
providing a tuning data pattern at a first frequency responsive, at least in part, to receipt of a clock signal having a first frequency; and
providing the tuning data pattern at a second frequency responsive, at least in part, to receipt of a clock signal having a second frequency.
18. The method of claim 17, wherein providing the tuning data pattern comprises providing the tuning data pattern responsive, at least in part, to receipt of a calibration command and an attribute.
19. The method of claim 17, further comprising:
comparing the tuning data pattern provided at the first frequency and the tuning data pattern provided at the second frequency.
20. The method of claim 19, wherein providing the tuning data patterns comprises providing the tuning data patterns from a memory coupled to a device, the method further comprising:
determining a sample point based, at least in part, on said comparing the tuning data pattern provided at the first frequency and the tuning data pattern provided at the second frequency at the device.
21. The method of claim 17, wherein said providing a tuning data pattern at a first:
frequency comprises providing the tuning data pattern from a memory over a plurality of IO lines.
22. The method of claim 17, wherein providing the tuning data pattern comprises providing the tuning data pattern responsive, at least in part, to receipt of a read volatile attribute.
23. The method of claim 17, wherein the second frequency is greater than the first frequency.
24. A method, comprising:
receiving at a memory a read command;
providing a tuning data pattern responsive, at least in part, to receipt of the read command; and
after providing the tuning data pattern from the memory, providing read data corresponding to the read command.
25. The method of claim 24, further comprising:
before said providing a tuning data pattern, waiting for a plurality of dummy cycles to elapse after receipt of the read command.
26. The method of claim 24, wherein said providing from the memory a tuning data pattern comprises:
determining the status of a short calibration flag; and
if it is determined that the short calibration flag has an enabled state, providing the a tuning data pattern.
27. The method of claim 24, wherein said providing from the memory a tuning data pattern comprises:
providing the tuning data pattern from a non-volatile memory to a volatile memory; and
providing the tuning data pattern from the volatile memory.
28. A method, comprising:
receiving a calibration command;
providing a tuning data pattern from a first register to a second register responsive, at least in part, to receipt of the calibration command;
receiving an attribute; and
executing an operation on the tuning data pattern based, at least in part, on the attribute.
29. The method of claim 28, wherein the tuning data pattern is a first data tuning pattern, the method further comprising:
after said receiving the attribute, receiving a second tuning data pattern.
30. The method of claim 29, wherein receiving a second tuning data pattern comprises storing the second tuning data pattern in the first register, and wherein the method further comprises providing the second tuning data pattern from the first register to the second register.
31. The method of claim 28, further comprising:
after said receiving the attribute, waiting for a plurality of dummy cycles to elapse.
32. The method of claim 28, wherein said executing an operation comprises:
providing the tuning data pattern from the second register to a bus.