Author: claimsbot

1. An electrically erasable and programmable memory (EEPROM) comprising:
a memory array comprising
word lines and a plurality of columns of bit lines,
memory cells connected to the word lines and bit lines,
read circuits connected to the memory cells via the bit lines,
a programming line, and
a plurality of programming latches each connecting one of the bit lines to the programming line;

a plurality of switches each being connected in a bit line between the memory cells and the programming latches, the switches of one column of bit lines defining a group of switches for interrupting connections between memory cells of the column and associated read circuits of the column when data has been loaded into the programming latches of the column, without interrupting connections between the programming latches of the column and the read circuits of the column; and
a plurality of memory circuits each for controlling one group of switches of one column of bit lines and providing a signal to open the switches of the group after a loading signal is received by the programming latches of the column.
2. A memory according to claim 1, further comprising a plurality of column selection circuits connected to the memory array; wherein each memory circuit is an element of one of the column selection circuits.
3. A memory according to claim 1, wherein, in a programming mode, the memory circuits, upon receiving a resetting signal, close the switches that were opened in a read mode.
4. A memory according to claim 1, wherein each switch comprises first and second parallel-connected switches, the first switch being driven by the memory circuit, the second switch being closed when the memory is in a programming mode and open if not.
5. A memory according to claim 1, wherein the programming latches comprise symmetrically structured latches that can receive bits equal to 1 or 0 without requiring a resetting of the latches.
6. A memory according to claim 1, wherein the memory cells of one column of bit lines and connected to one word line comprise a bit string formed by at least two binary words and one error correction code.
7. A memory according to claim 6, further comprising a programming and error correction circuit connected to the memory array for, upon the reception of a word to be recorded in the memory array at a specified address, reading the bit string designated by the address of the word to be recorded, inserting the word into the bit string and computing a new error correction code, and loading the new bit string into the programming latches designated by the address of the word to be record.
8. A memory according to claim 7, wherein the programming and error correction circuit, upon the reception of a word to be recorded in a bit string that has been previously loaded into the programming latches, reads the bit string loaded into the programming latches via the read circuits, inserts the binary word into the bit string and computes a new error correction code, and loads the new bit string into the programming latches.
9. An electrically erasable and programmable memory (EEPROM) comprising:
a memory array comprising
word lines and a plurality of columns of bit lines,
memory coils connected to the word lines and bit lines,
read circuits connected to the memory cells via the bit lines,
a programming line, and
a plurality of programming latches each connecting one of the bit lines to the programming line;

a plurality of switches each being connected in a bit line between the memory cells and the programming latches, the switches of one column of bit lines defining a group of switches; and
a plurality of memory circuits each for controlling one group of switches of one column of bit lines and opening the switches of the group after data has been loaded into the programming latches of the column.
10. A memory according to claim 9, further comprising a plurality of column selection circuits connected to the memory array; wherein each memory circuit is an element of one of the column selection circuits.
11. A memory according to claim 9, wherein, in a programming mode, the memory circuits, upon receiving a resetting signal, close the switches that were opened in a read mode.
12. A memory according to claim 9, wherein each switch comprises first and second parallel-connected switches, the first switch being driven by the memory circuit, the second switch being closed when the memory is in a programming mode and open if not.
13. A memory according to claim 9, wherein the programming latches comprise symmetrically structured latches that can receive bits equal to 1 or 0 without requiring a resetting of the latches.
14. A memory according to claim 9, wherein the memory cells of one column of bit lines and connected to one word line comprise a bit string formed by at least two binary words and one error correction code.
15. A memory according to claim 14, further comprising a programming and error correction circuit connected to the memory array for, upon the reception of a word to be recorded in the memory array at a specified address, reading the bit string designated by the address of the word to be recorded, inserting the word into the bit string and computing a new error correction code, and loading the new bit string into the programming latches designated by the address of the word to be recorded.
16. A memory according to claim 15, wherein the programming and error correction circuit, upon the reception of a word to be recorded in a bit string that has been previously loaded into the programming latches, reads the bit string loaded into the programming latches via the read circuits, inserts the binary word into the bit string and computes a new error correction code, and loads the new bit string into the programming latches.
17. A method for the recording of the binary words into an electrically erasable and programmable memory (EEPROM) comprising a memory array including memory cells connected to word lines and a plurality of columns of bit lines, read circuits connected to the bit lines, a plurality of programming latches each connecting one of the bit lines to a programming line, and a plurality of switches each being connected in a bit line between the memory cells and the programming latches, the switches of one column of bit lines defining a group of switches for interrupting connections between memory cells of the column and associated read circuits of the column, the method comprising:
loading, into the programming latches of one of the columns, a bit string comprising at least two binary words;
opening the switches of the associated group of switches of the column to interrupt the connection between the memory cells of the column and the read circuits of the column without interrupting the connection between the programming latches of the column and the read circuits of the column;
reading the bit string loaded into the programming latches of the column via the read circuits;
replacing one of the binary words in the bit string with another binary word to form a new bit string; and
loading the new bit string into the programming latches of the column.
18. A method according to claim 17, wherein a bit string comprises an error correction code that is recomputed when the another binary word is inserted into the bit string and that is inserted into the new bit string instead of an initial error correction code.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A ceramic article which is resistant to erosion by halogen-containing plasmas used in semiconductor processing, said article comprising: a solid solution ceramic formed from yttrium oxide at a molar concentration ranging from about 90 mole % to about 70 mole %, and zirconium oxide at a molar concentration ranging from about 10 mole % to about 30 mole %.
2. A ceramic article in accordance with claim 1, wherein said ceramic is formed from yttrium oxide at a concentration ranging from about 90 mole % to about 80 mole %, and zirconium oxide at a concentration ranging from about 10 mole % to about 20 mole %.
3. A ceramic article in accordance with claim 1 or claim 2, wherein a mean grain size of said ceramic ranges from about 2 \u03bcm to about 8 \u03bcm.
4. A ceramic article in accordance with claim 1, wherein a flexural strength of said ceramic ranges from about 120 MPa to about 140 MPa.
5. A ceramic article in accordance with claim 1, wherein a fracture toughness of said ceramic ranges from about 1.1 MPa\xb7m12 to about 1.3 MPa\xb7m12.
6. A ceramic article in accordance with claim 1 or claim 2, wherein said article is selected from the group consisting of a lid, a lid liner, a nozzle, a gas distribution plate, a shower head, an electrostatic chuck component, a shadow frame, a substrate holding frame, a processing kit, and a chamber liner.
7. A method of reducing the plasma erosion of a semiconductor processing apparatus contacted by a halogen-containing plasma, comprising: selecting said semiconductor processing apparatus to comprise a solid solution ceramic, said ceramic formed from yttrium oxide at a molar concentration ranging from about 90 mole % to about 70 mole %, and zirconium oxide at a molar concentration ranging from about 10 mole % to about 30 mole %.
8. A method in accordance with claim 7, further comprising selecting said ceramic for said semiconductor processing apparatus to be formed from yttrium oxide at a molar concentration ranging from about 90 mole % to about 80 mole %, and zirconium oxide at a concentration ranging from about 10 mole % to about 20 mole %.
9. A method in accordance with claim 7 or 8, wherein said plasma erosion rate for a surface of said semiconductor processing apparatus upon exposure to a halogen-comprising plasma is less than about 0.2 \u03bcmhr.
10. A method in accordance with claim 9, wherein said plasma erosion rate for a surface of said semiconductor processing apparatus upon exposure to a halogen-comprising plasma ranges from about 0.1 to about 0.2 \u03bcmhr.
11. A semiconductor processing apparatus having at least one surface exposed to a halogen-comprising plasma during a process, wherein said semiconductor processing apparatus surface is a solid solution-comprising ceramic which is resistant to erosion by halogen-containing plasmas, wherein said ceramic is formed from yttrium oxide at a molar concentration ranging from about 90 mole % to about 70 mole %, and zirconium oxide at a molar concentration ranging from about 10 mole % to about 30 mole %.
12. A semiconductor processing apparatus in accordance with claim 11, wherein underlying said ceramic is a high purity aluminum alloy.
13. A method in accordance with claim 11, wherein said semiconductor processing apparatus is a solid body ceramic semiconductor processing apparatus.
14. A semiconductor processing apparatus, said apparatus having at least one surface exposed to a halogen-comprising plasma during a process, wherein said surface is a solid solution-comprising ceramic which is resistant to erosion by halogen-containing plasmas, wherein said ceramic is formed from zirconium oxide at a molar concentration ranging from about 96 mole % to about 94 mole %, and yttrium oxide at a molar concentration ranging from about 4 mole % to about 6 mole %.
15. A semiconductor processing apparatus in accordance with claim 14, wherein underlying said ceramic is a high purity aluminum alloy.
16. A semiconductor processing apparatus in accordance with claim 14, wherein said apparatus is a solid body ceramic apparatus.
17. A semiconductor processing apparatus in accordance with claim 14, wherein said apparatus is selected from the group consisting of a lid, a lid liner, a nozzle, a gas distribution plate, a shower head, an electrostatic chuck component, a shadow frame, a substrate holding frame, a processing kit, and a chamber liner.
18. A semiconductor processing apparatus in accordance with claim 14, wherein a mean grain size of said ceramic ranges from about 0.5 \u03bcm to about 8.0 \u03bcm.
19. A semiconductor processing apparatus in accordance with claim 14, wherein a flexural strength of said ceramic ranges from about 1100 MPa to about 1300 MPa.
20. A semiconductor processing apparatus in accordance with claim 14, wherein a fracture toughness of said ceramic ranges from about 10 MPa\xb7m12 to about 12 MPa\xb7m12.
21. A method of reducing the plasma erosion of a semiconductor processing apparatus contacted by a halogen-containing plasma, comprising: selecting said semiconductor processing apparatus to be a solid solution ceramic-comprising article, said ceramic formed from zirconium oxide at a molar concentration ranging from about 96 mole % to about 94 mole %, and yttrium oxide at a molar concentration ranging from about 4 mole % to about 6 mole %.
22. A method in accordance with claim 21, wherein said plasma erosion rate for a surface of said semiconductor processing apparatus, upon exposure to a halogen-comprising plasma, is less than about 0.4 \u03bcmhr.
23. A method in accordance with claim 22 wherein said plasma erosion rate for a surface of said semiconductor processing apparatus, upon exposure to a halogen-comprising plasma, ranges from about 0.1 \u03bcmhr to about 0.4 \u03bcmhr.
24. A method in accordance with claim 21, wherein at least one surface of said semiconductor processing apparatus, which surface is said ceramic, is exposed to said halogen-comprising plasma during said semiconductor processing.
25. A method in accordance with claim 24, wherein underlying said ceramic is a high purity aluminum alloy.
26. A method in accordance with claim 24, wherein said semiconductor processing apparatus is a solid body ceramic semiconductor processing apparatus.

1. An infant pad assembly comprising:
a flat central section having a top and a bottom and at least four straight sides;
a flat side section for each of the at least four straight sides of the central section, each side section having a inner edge, first and second end ends each with first and second end edges and a top edge, each inner edge being hingedly attached to the side of the central section for pivotal movement relative thereto;
wherein, when all the side sections are positioned in a flat position co-planar with the central section, the infant pad assembly forms an infant play mat;
wherein the central section and the flat side sections are configured so that, when all the side section are pivoted toward the top of the central section to an upright position perpendicular to the central section, each side section is between two other side sections and immediately adjacent thereto so that each pair of adjacent side sections forms a corner and so that the side sections collectively form a substantially complete side wall around the central section comprising a portable infant bed;
a corner connector for removably attaching adjacent side sections to each other;
wherein at least one of the side sections includes a receiver on each of its first and second ends and wherein the end of each side section adjacent to the at least one side section includes a stability tab connectable to the receiver on the adjacent end of the at least one side section, so that when the corner connector is disconnected and each of the stability tabs is connected to the corresponding receiver, the at least one side section is prevented from pivoting past the flat position toward the bottom of the central section, and so that when the at least one side section is thereby secured in the flat position and the remaining side sections are all in the upright position, the infant pad assembly forms a changing mat; and
wherein the central section and all the side sections are flexible panels so that when all the corner connectors and stability tabs are disconnected, the side sections can be pivoted all the way toward the top of the central section into a collapsed position and so that the infant pad assembly in the collapsed positioned can be rolled into a carrying case; and
a shoulder strap on the bottom of the central section for carrying the infant pad assembly in the carrying case mode.
2. The infant pad assembly of claim 1 wherein the at least four sides of the central section is only four sides.
3. The infant pad assembly of claim 2 wherein the central section is rectangular.
4. The infant pad assembly of claim 3 wherein each corner connector comprises a tab extending from the end edge of the end of one of the adjacent side panels, a first strip of hook and loop fastener fixed to the tab, and a second strip of hook and loop fastener on the end of the other of the adjacent side panels, the second strip engageable with the first strip.
5. The infant pad assembly of claim 4 wherein the first and second strips of hook and loop fastener extend along substantially the entire end of the adjacent side panels.
6. The infant pad assembly of claim 1 wherein the receiver comprises a strip of hook and loop fastener and wherein the stability tab comprises a cooperating piece of hook of look fastener.
7. The infant pad assembly of claim 1 wherein the infant pad assembly comprises at least one pocket.
8. The infant pad assembly of claim 7 wherein the infant pad assembly comprises two pockets including a first pocket on one of the at least four side panels and a second pocket on another of the at least four side panels.
9. The infant pad assembly of claim 8 wherein the first pocket is formed by a net panel.
10. The infant pad assembly of claim 9 wherein the second pocket is a fabric enclosure.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. System positioned within an opening or access of a paint supply device; said system including a fluid-dispensing head, which has a plurality of nozzles for the supply of a plurality of fluids in controlled quantities into a container set underneath said head on a resting surface of the paint supply device inside said opening or access; said system comprising:
means for releasing or clamping said fluid-dispensing head configured for enabling movement of said supply head between a first clamped position of use, wherein said nozzles supply the plurality of fluids into a container, and a second extracted position, distinct from said first position of use, wherein said nozzles are accessible for being cleaned;
wherein said means for releasing or clamping comprise:
an L-shaped bracket fixed to said paint supply device, having a first surface set substantially vertically and a second surface set horizontally parallel to the ground;
a plate housed on said second surface of said L-shaped bracket and having a recess or slot opened on a side facing said opening or access of the paint supply device in which the fluid dispensing head is removably mounted to direct the nozzles downward toward the container and to enable manual extraction of the fluid dispensing head; and
clamping means for clamping said fluid dispensing head in said recess or slot of said plate.
2. System according to claim 1, wherein said means for releasing or clamping are configured for enabling movement of said supply head in a third position of use in which the nozzles are oriented upwardly.
3. System according to claim 2, further comprising means for blocking delivery of said plurality of fluids by said nozzles when said fluid-dispensing head is in said second position or in a third position.
4. System according to claim 1, said clamping means comprising an element for pressing the fluid-dispensing head into the recess or slot, and a pin on which said element is pivoted at one end thereof.