Author: claimsbot

1. A method for enumerating an asset using at least one processor, the method comprising:
receiving an enumeration request for enumerating the asset;
translating the enumeration request from an information model format to a data acquisition (DAQ) format to obtain a translated request;
obtaining a DAQ definition from the translated request, wherein the DAQ definition complies with the DAQ format;
identifying an actual uniform resource identifier (URI) from the DAQ definition, wherein the identifying is based on the enumeration request, wherein the actual URI comprises an identifier of an enumeration mechanism and an identifier of a protocol;
triggering, according to the protocol, a protocol handler to enumerate the asset using the enumeration mechanism identified in the actual URI;
obtaining information about at least one instance of the asset from the protocol handler after the protocol handler enumerates the asset;
managing the at least one instance of the asset using the information, wherein the asset is at least one selected from a group consisting of a hardware component in a computer and software executing on the computer;
determining a relative URI of the enumeration mechanism; and
setting the relative URI in a native asset interface (NAI) definition before receiving the enumeration request, wherein the DAQ definition is a runtime binding of the NAI definition.
2. The method of claim 1, wherein the enumeration request specifies an asset type.
3. The method of claim 1, wherein the enumeration mechanism is a script.
4. The method of claim 1, further comprising: replacing a variable in the relative URI to obtain the actual URI.
5. The method of claim 1, further comprising:
transmitting the information to a management application.
6. The method of claim 1, wherein the NAI definition is defined in extensible markup language.
7. The method of claim 1, further comprising:
identifying an asset type of the asset from an enumeration request, wherein the DAQ definition is based on the asset type.
8. A system for enumerating an asset comprising:
a processor;
a data acquisition (DAQ) definition;
a DAQ manager executing on the processor and configured to:
receive an enumeration request for enumerating the asset;
obtain the DAQ definition associated with the enumeration request;
identify an actual uniform resource identifier (URI) from the DAQ definition, wherein the identifying is based on the enumeration request, wherein the URI comprises an identifier of an enumeration mechanism and an identifier of a protocol;
trigger, according to the protocol, a protocol handler to enumerate the asset using the enumeration mechanism identified in the actual URI; and
obtain information about at least one instance of the asset from the protocol handler after the protocol handler enumerates the asset; and

a developer environment configured to:
determine a relative URI of the enumeration mechanism; and
set the relative URI in an NAI definition before receiving the enumeration request, wherein the DAQ definition is a runtime binding of the NAI definition,

wherein an information model request is translated from an information model format to a DAQ format to obtain the enumeration request, wherein the DAQ definition complies with the DAQ format, and
wherein the at least one instance of the asset is managed using the information, wherein the asset is at least one selected from a group consisting of a hardware component in a computer and software executing on the computer.
9. The system of claim 8, wherein the enumeration request specifies an asset type.
10. The system of claim 8, wherein the enumeration mechanism is a script.
11. The system of claim 8, further comprising:
an administrator environment configured to:
replace a variable in the relative URI to obtain the actual URI.
12. The system of claim 8, further comprising:
an information model runtime configured to:
transmit the information to a management application.
13. The system of claim 8, wherein the NAI definition is in extensible markup language.
14. The system of claim 8, further comprising:
an information model runtime configured to translate the information model request from the information model format to the DAQ format.
15. A distributed computer system having a plurality of nodes, wherein at least one node of the plurality of nodes comprises a processor configured to execute instructions for performing a method, the method comprising:
receiving an enumeration request for enumerating an asset;
translating the enumeration request from an information model format to a data acquisition (DAQ) format to obtain a translated request;
obtaining a DAQ definition from the translated request, wherein the DAQ definition complies with the DAQ format;
identifying an actual uniform resource identifier (URI) from the DAQ definition, wherein the identifying is based on the enumeration request, wherein the actual URI comprises an identifier of an enumeration mechanism and an identifier of a protocol;
triggering, according to the protocol, a protocol handler to enumerate the asset using the enumeration mechanism identified in the actual URI;
obtaining information about at least one instance of the asset from the protocol handler after the protocol handler enumerates the asset;
managing the at least one instance of the asset using the information, wherein the asset is at least one selected from a group consisting of a hardware component in a computer and software executing on the computer;
determining a relative URI of the enumeration mechanism; and
setting the relative URI in a native asset interface (NAI) definition before receiving the enumeration request, wherein the DAQ definition is a runtime binding of the NAI definition,
wherein the protocol handler and the enumeration mechanism are distributed across one or more of the plurality of nodes.
16. The method of claim 1, wherein the enumeration request is received from a management application, wherein the enumeration request complies with the information model format, and wherein the method further comprises:
identifying an asset type of the asset from the enumeration request;
identifying a mapping specification entry matching the type of the asset, wherein the enumeration request is translated based on the mapping specification entry to create the translated request.
17. The method of claim 1, wherein the asset comprises at least one selected from a group consisting of an application and a hardware device, and wherein the DAQ definition is identified based on an asset type of the asset.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A reference voltage circuit comprising:
first and second current-to-voltage conversion circuits, each for receiving a current and converting the current to a voltage;
control means for performing control so that the voltage of said first current-to voltage conversion circuit becomes equal to the voltage of the second current-to-voltage conversion circuit;
a first current mirror circuit for outputting a current proportionate to a value of the current supplied to one of said first current-to-voltage conversion circuit and said second current-to-voltage conversion circuit; and
a third current-to-voltage conversion circuit for receiving the output current from said first current mirror circuit, and converting the output current to a voltage, for output;
wherein each of said first and second current-to-voltage conversion circuits includes one of:
a circuit comprising a serial circuit comprising a first diode and a first resistor connected in series with each other, and a second resistor connected in parallel with the series circuit; and
a circuit comprising a parallel circuit comprising a first diode and a first resistor connected in parallel with each other, and a second resistor, having only two terminal elements, connected in series with the parallel circuit.
2. The reference voltage circuit according to claim 1, wherein said third current-to-voltage conversion circuit comprises a resistor.
3. The reference voltage circuit according to claim 1, further comprising:
a third diode connected in parallel with said first current-to-voltage conversion circuit; and
a fourth diode connected in parallel with said second current-to-voltage conversion circuit.
4. The reference voltage circuit according to claim 1, wherein said control means includes a differential amplifier.
5. The reference voltage circuit according to claim 4, wherein each of said first and second current-voltage conversion circuits includes the circuit comprising the series circuit including the first diode and the first resistor connected in series with each other, and the second resistor connected in parallel with the series circuit,
intermediate potentials of said second resistors in said first and second current-to-voltage conversion circuits being supplied to input terminals of said differential amplifier, respectively.
6. The reference voltage circuit according to claim 1, wherein said control means includes a second current mirror circuit which is self-biased by a current mirror circuit including said first current mirror circuit.
7. The reference voltage circuit according to claim 1, wherein said control means comprises second and third current mirrors,
said control means comparing the current supplied to said first current-to-voltage conversion circuit with the current supplied to said second current-to-voltage conversion circuit by said second current mirror circuit, and
by biasing the third current mirror circuit by an output of said second current mirror circuit, said control means performing control so that the voltage of said first current-to-voltage conversion circuit becomes equal to the voltage of said second current-to-voltage conversion circuit.
8. The reference voltage circuit according to claim 1, wherein said control means includes a second mirror circuit self-biased by an inverse Widlar current mirror circuit including said first current mirror circuit.
9. A reference voltage circuit comprising:
first and second current-to-voltage conversion circuits, each for receiving a current and converting the current to a voltage;
control means for performing control so that the voltage of said first current-to-voltage conversion circuit becomes equal to the voltage of said second current-to-voltage conversion circuit;
a first current mirror circuit for outputting a current proportionate to a value of the current supplied to one of said first current-to-voltage conversion circuit and said second current-to-voltage conversion circuit; and
a third current-to-voltage conversion circuit for receiving the output current from said first current mirror circuit, and converting the output current to a voltage, for output;
wherein each of said first and third current-to-voltage conversion circuits includes a diode-connected first bipolar transistor, said first bipolar transistor having an emitter grounded through a first emitter resistor and having a base directly grounded with a second resistor connected in parallel therewith, or grounded through the first emitter resistor; and
wherein said second current-to-voltage conversion circuit includes second and third bipolar transistors, said second bipolar transistor having an emitter grounded through a second emitter resistor, having a base connected to an output terminal of said first current-to-voltage conversion circuit, and having a collector connected to a base of said third bipolar transistor and directly grounded with a fourth resistor connected in parallel therewith or grounded through said second emitter resistor, a collector of said third bipolar transistor driving said first current mirror circuit.
10. A reference voltage circuit comprising:
a first current-to-voltage conversion circuit including a diode-connected first bipolar transistor having an emitter grounded through a first emitter resistor, and having a base directly grounded with a second resistor connected in parallel therewith;
a second current-to-voltage conversion circuit including second and third bipolar transistors;
fourth and fifth bipolar transistors;
said second bipolar transistor having an emitter grounded through a second emitter resistor, having a base connected to an output terminal of said first current-to-voltage conversion circuit, and having a collector connected to bases of said third and fourth bipolar transistors and being directly grounded with a fourth resistor connected in parallel therewith;
transistor sizes of said third and fourth bipolar transistors being the same as transistor sizes of said first and second bipolar transistors, respectively;
said third and fourth bipolar transistors having emitters grounded through third and fourth emitter resistors, respectively, values of said third and fourth emitter resistors being equal to values of said first and second emitter resistors, respectively; and
a seventh resistor, one terminal of said seventh resistor being grounded to bias said fifth bipolar transistor, a value of said seventh resistor being equal to that of each of said second and fourth resistors, said fifth bipolar transistor having an emitter grounded through a fifth emitter resistor, said fifth bipolar transistor having a transistor size being equal to that of said third or fourth bipolar transistor;
said reference voltage circuit further comprising:
means for causing a current flowing through said fifth bipolar transistor to be equal to a current flowing though said third or fourth bipolar transistor; and
means for causing a sum of currents flowing through said third and fourth bipolar transistors and a current flowing through said seventh resistor to drive said first current-to-voltage conversion circuit, said second bipolar transistor, and said fourth emitter resistor,
wherein said third current-to-voltage conversion circuit is driven by a current proportionate to a sum of a current flowing through said first or second bipolar transistor and a current flowing through said second or fourth resistor.
11. The reference voltage circuit according to claim 9, wherein said third current-to-voltage conversion circuit comprises a resistor element.
12. The reference voltage circuit according to claim 1, wherein the diode comprises a diode-connected bipolar transistor.
13. A reference voltage circuit comprising:
first and second current-to-voltage conversion circuits each for receiving a current and converting the current to a voltage;
a first current mirror circuit for outputting a current proportionate to a value of the current supplied to said first current-to-voltage conversion circuit or said second current-to-voltage conversion circuit;
a second current mirror circuit connected between outputs of said first and second current-to-voltage conversion circuits and said first current mirror circuit; and
a third current-to-voltage conversion circuit for receiving the output current from said first current mirror circuit, and converting the output current to a voltage, for output;
wherein each of said first and second current-to-voltage conversion circuits includes one of:
a circuit comprising a series circuit including a first diode and a first resistor connected in series with each other and a second resistor connected in parallel with the series circuit; and
a circuit comprising a parallel circuit including a first diode and a first resistor connected in parallel with each other and a second resistor, having only two terminal elements, connected in series with the parallel circuit;

wherein said third current-to-voltage conversion circuit comprises a resistor element; and
wherein said second current mirror circuit is self-biased by said first current mirror circuit, a voltage of said first current-to-voltage conversion circuit and a voltage of said second current-to-voltage circuit being thereby controlled to be equal.
14. A reference voltage circuit comprising:
first and second current-to-voltage conversion circuits each for receiving a current and converting the current to a voltage;
a first current mirror circuit for outputting a current proportionate to a value of the current supplied to said first current-to-voltage conversion circuit and a second current mirror circuit for outputting a current proportionate to a value of the current supplied to said second current-to-voltage conversion circuit;
first and second transistors, said first transistor being corrected between an output of said first current-to-voltage conversion circuit and an input of said first current mirror circuit, said second transistor being connected between an output of said second current-to-voltage conversion circuit and an input of said second current mirror circuit;
a third current mirror circuit for receiving output currents from said first and second current mirror circuits, and performing current comparison thereof; and
a third current-to-voltage conversion circuit for receiving the output current of said first current mirror circuit, and converting the output current to a voltage, for output, wherein each of said first and second current mirror circuits includes one of:
a circuit comprising a series circuit including a first diode and a first resistor connected in series, and a second resistor connected in parallel with the series circuit, and
a circuit comprising a parallel circuit including a first diode and a first resistor connected in parallel, and the second resistor connected in series with the parallel circuit,

wherein said third current-to-voltage circuit comprises a resistor element, and
wherein an output of said third current mirror circuit is connected to a control terminal connected in common of said first and second transistors,
said reference voltage circuit further comprising:
fourth and fifth current-to-voltage conversion circuits, each having a same configuration as said first current-to-voltage conversion circuit being connected to said third current mirror circuit.
15. A reference voltage circuit comprising:
first and second current-to-voltage conversion circuits each for receiving a current and converting the current to a voltage;
a first current mirror circuit comprising first and second outputs;
first and second transistors, said first transistor being connected between said first current-to-voltage conversion circuit and an input of said first current mirror circuit, said second transistor being connected between said second current-to-voltage conversion circuit and the first output of said second current mirror circuit;
a third current-to–voltage conversion circuit for receiving an output current from the second output of said first current mirror circuit, converting the output current to a voltage, for output;
a third transistor having a control terminal thereof connected in common to control terminals of said first and second transistors, said third transistor being diode-connected, said third transistor being connected to a fourth current-to-voltage conversion circuit having a same configuration as said first current-to-voltage circuit, said third transistor constituting a current mirror circuit with said first and second transistors; and
a fourth transistor connected between an output of said third transistor and a power supply, a control terminal of said fourth transistor being connected to the first output of said first current mirror circuit;
wherein each of said first and second, current mirror circuits includes one of:
a circuit comprising a series circuit including a first diode and a first resistor connected in series with each other, and a second resistor connected in parallel with the series circuit; and
a circuit comprising a parallel circuit including a first diode and a first resistor connected in parallel with each other, and a second resistor connected in series with the parallel circuit; and

wherein said third current-to-voltage circuit comprises a resistor element.
16. The reference voltage circuit according to claim 13, further comprising:
diodes connected in parallel with said first and second current-to-voltage conversion circuits, respectively.
17. The reference voltage circuit according to claim 14, further comprising:
diodes connected in parallel with said first, second, fourth, and fifth current-to-voltage conversion circuits, respectively.
18. The reference voltage circuit according to claim 15, further comprising:
diodes connected in parallel with said first, second, and fourth current-to-voltage conversion circuits, respectively.
19. The reference voltage circuit according to claim 1, wherein each of said first and second current-to-voltage conversion circuits includes the circuit comprising the serial circuit including the first diode and the first resistor connected in series with each other, and the second resistor connected in parallel with the series circuit.
20. The reference voltage circuit according to claim 1, wherein the first current mirror circuit comprises three transistors, and
wherein each transistor provides current to one of said first, second, and third current-to-voltage conversion circuits.
21. The reference voltage circuit according to claim 13, wherein each of said first and second current-to-voltage conversion circuits includes the circuit comprising the serial circuit including the first diode and the first resistor connected in series with each other, and the second resistor connected in parallel with the series circuit.
22. The reference voltage circuit according to claim 13, wherein the first current mirror circuit comprises three transistors, and
wherein each transistor provides current to one of said first, second, and third current-to-voltage conversion circuits.

1. A beverage preparation system comprising: a first machine for preparing and dispensing a first beverage via a first outlet onto a beverage dispensing area for positioning a cup or mug; a second machine for preparing and dispensing a second beverage via a second beverage outlet, wherein the first and the second machine are both operable in a standalone configuration, the second machine being disconnectably connected to the first machine and separable therefrom; and;
the first and second machines, when connected, are configurable so that the second outlet is positioned or positionable adjacent to the first outlet to dispense the second beverage onto the beverage dispensing area and into a cup or mug in position for collecting the first beverage from the first beverage outlet.
2. The system of claim 1, wherein the second machine comprises a milk supply arrangement comprising a cooling cavity containing a milk tank.
3. The system of claim 2, wherein the second machine comprises an arrangement for frothing andor heating milk from the milk supply arrangement.
4. The system of claim 3, wherein the second machine comprises a collector reservoir for collecting a cleaning liquid circulated through the frothing andor heating arrangement.
5. The system of claim 1, wherein the second beverage outlet is movable between an operative position for dispensing the second beverage onto the beverage dispensing area and a distant position.
6. The system of claim 5, wherein the second outlet is movable manually into the operative position.
7. The system of claim 5, wherein the second outlet is movable automatically into the operative position.
8. The system of claim 5, wherein the second machine comprises an actuator for automatically returning the second outlet from the operative position into the distant position.
9. The system of claim 1, wherein the first and second machines are directly or indirectly rigidly connected by a disconnectable mechanical link.
10. The system of claim 1, wherein the first machine comprises a first control module for controlling preparation of the first beverage and wherein the second machine comprises a second control module for controlling the preparation of said second beverage, the first and second control modules being in direct or indirect data-communication when the second machine is connected to the first machine.
11. The system of claim 10, wherein the first and second control modules are in data-communication to coordinate dispensing of the first and second beverages via the first and second outlets.
12. The system of claim 11, wherein the first and second control modules are arranged to coordinate and dispense the first and second beverages on a single user-request of a combined beverage of the first and second beverages.
13. The system of claim 11, wherein the first and second control modules are arranged to provide information to a user via a user-interface that is integrated either in the first machine or in the second machine.
14. The system of claim 1, wherein at least one of the first and second machines are configured for beverage preparation and dispensing when the first and second machines are disconnected.
15. A second machine for preparing a second beverage and for use with a first machine and second machine comprising:
a control module and a second outlet for dispensing a second beverage onto a beverage dispensing area for positioning a user-recipient; and
a connector disconnectably connectable to the first machine for preparing and delivering a first beverage, the first machine having a first control module;
the second control module is arranged to be in data-communication with the first module to coordinate and dispense the first and second beverages on a single user-request of a combined beverage of the first and second beverages.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of generating a clock distribution network on an integrated circuit comprising the steps of:
determining an allowable placement region for each of at least one clock tree leaf element;
grouping said at least one clock tree leaf element into at least one cluster; and
placing said at least one clock tree leaf element at a location within said allowable placement region wherein a cost function is minimized.
2. The method as recited in claim 1, wherein said allowable placement region is formed by intersecting a plurality of sub-regions.
3. The method as recited in claim 2, wherein at least one of said sub-regions that generates an allowable placement region for a given clock tree leaf element is determined based on a slack of a connection of said given clock tree leaf element.
4. The method as recited in claim 3, wherein said at least one of said sub-regions is generated using a binary search.
5. The method as recited in claim 2, wherein at least one of said sub-regions that generates an allowable placement region for a given clock tree leaf element is based on at least one congestion value.
6. The method as recited in claim 5, wherein said congestion value is selected from the group consisting of a placement congestion value, a wiring congestion value, a power congestion value, and any combination thereof.
7. The method as recited in claim 1, further comprising determining final placement locations for a plurality of sinks in a clock distribution network of an integrated circuit chip, comprising the steps of:
a) starting at a root net of a clock tree, determining a final placement location within an allowable placement region for at least one element of a first level of said sinks coupled to said root net while minimizing a cost function;
b) selecting at least one element of a second level of said sinks coupled to said at least one element of said first level of sinks, and determining for said element of said second level of sinks a final placement location within its allowable placement regions while minimizing the cost function; and
c) repeating step b) for elements of subsequent levels of sinks until a last level of sinks is reached.
8. The method of claim 7 further comprising the step of placing the elements of the last level of sinks at positions within their allowable placement regions to minimize the total wire length between the elements of the last level of sinks.
9. The method of claim 8 wherein said elements of said last level of sinks are latches.
10. The method as recited in claim 1 further comprising the step of removing blockages from said allowable placement regions.
11. The method as recited in claim 10, wherein removing said blockages from said allowable placement regions comprises the steps of:
identifying blockages which are respectively superimposed on allowable placement regions; and
redefining said respective allowable placement regions as said allowable placement regions from which their respective superimposed blockages have been subtracted.
12. The method as recited in claim 1 further comprising the step of removing congested regions from said allowable placement regions.
13. The method of claim 1, wherein said clock distribution network includes at least one first clocked element driving at least one second clocked element, and wherein said method further comprises the steps of:
d) determining allowable placement regions for each of said at least one first and second clocked elements;
e) assigning a final placement location for said at least one first clocked element within said allowable placement region of said at least one first clocked element; and
f) assigning a final placement location for said at least one second clocked element within said allowable placement region of said at least second clocked element, wherein said final placement location of said at least one second clocked element is based on said final placement location of said least one first clocked element.
14. The method of claim 1, wherein said allowable placement region for said at least one clock tree leaf element includes an initial placement location of said at least one clock tree leaf element.
15. The method of claim 3, wherein said at least one sub-region is determined based on the slack of said connection of said given clock tree leaf element including only locations at which said given clock tree leaf element can be placed without reducing said slack by more than a computed allowable slack reduction value.
16. The method of claim 15, wherein said computed allowable slack reduction value is one-half of said slack.
17. The method of claim 15, wherein said allowable slack reduction values are computed for a plurality of clock tree leaf element connections in an order that is determined by slacks of said plurality of clock tree leaf element connections.
18. A method of generating allowable placement regions in a clock distribution network of an integrated circuit (IC) chip comprising the steps of:
a) allocating the entire IC chip area to an allowable placement region of at least one clock tree leaf element having at least one non-clock port;
b) determining a sub-region associated with at least one of said non-clock ports of said clock tree leaf element;
c) redefining said clock tree leaf element allowable placement region to be an intersection of said clock tree leaf element allowable placement region with said sub-region;
d) generating a list of congested regions and subtracting congested regions from said allowable placement region; and
e) generating a list of blockage regions and subtracting blockage regions from said allowable placement region.
19. The method as recited in claim 2, wherein each of said intersected sub-regions is related to a constraint on said clocked element.
20. The method as recited in claim 19, wherein intersecting said allowable placement regions comprises the steps of:
a) forming a region for each connection of said clocked element within which timing requirements between said clocked element and its connection are satisfied and, if they cannot be satisfied, within which they are not worsened; and
b) forming a region that avoids placing said clocked element at a location that causes local circuit or wiring density requirements to exceed a predetermined limit.
21. The method as recited in claim 20, wherein in step a) at least one of said regions is shaped as a diamond having 90\xb0 angles, and wherein all the points on said diamond are equidistant from the center of a Manhattan space.
22. The method as recited in claim 20 wherein in step b) said regions have arbitrary shapes.
23. The method as recited in claim 1, wherein said grouping of said clock tree leaf elements into clusters is based on said allowed placement regions of said clock tree leaf elements.
24. The method as recited in claim 23, wherein each of said clusters is driven by a respective clock net, and each clock tree leaf element that has been clustered is moved to a point of its allowed placement region that minimizes the amount of wire for said respective clock net, thereby reducing power consumption.
25. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for generating a clock distribution network on an integrated circuit, said method steps comprising:
determining an allowable placement region for each of at least one clock tree leaf element;
grouping said at least one clock tree leaf element into at least one cluster; and
placing said at least one clock tree leaf element at a location within said allowable placement region wherein a cost function is minimized.