What is claimed is:
1. A circuit for protecting ICs against ESD transients, comprising:
a master circuit responsive to ESD voltage V(t) and having an output; and
a slave circuit comprising multiple parallel shunt devices having a common input coupled to the output of the master circuit; wherein
as V(t) increases the master circuit applies a portion of V(t) to the input of the slave circuit shunt devices thereby lowering a threshold voltage Vt1 at which the slave circuit shunt devices would otherwise turn on, to a smaller value Vt1 much closer to a holding voltage Vh of the shunt devices; and
wherein when V(t) reaches Vt1, all of the slave circuit devices turn on substantially simultaneously, thereby shunting the ESD transient harmlessly to ground.
2. The circuit of claim 1 wherein the master circuit comprises a transient voltage divider having a time constant at least 5 times the ESD transient rise time to Vt1.
3. The circuit of claim 1 wherein the master circuit comprises a transient voltage divider having a first resistor R1, a capacitor C1 and a second resistor R2 series coupled between V(t) and ground, and an active device having a control terminal T1 and power terminals T2, T3, wherein T1 is coupled to a first terminal of C1 whose second terminal is coupled through R2 to V(t), T1 is also coupled to a first terminal of R2 whose second terminal is coupled to ground, T2 is coupled to a second terminal of C1 and through R2 to V(t), and T3 is coupled through a third resistor R3 to ground, wherein the output of the master circuit is derived from T3.
4. The circuit of claim 3 wherein R1, R2 and C1 are chosen so that during the time wherein the ESD transient rises to about Vt1, there is negligible voltage drop across C1.
5. The circuit of claim 1 wherein the portion of V(t) applied to the input of the slave circuit shunt devices is sufficient to reduce Vt1 to approximately its minimum value Vt1
6. The circuit of claim 1 wherein the parallel shunt devices are NMOS devices and the portion of V(t) applied to gate inputs of the NMOS devices is a voltage that minimizes Vt1.
7. The circuit of claim 1 wherein the multiple parallel shunt devices comprise NMOS transistors having gates coupled to the slave circuit input, collectors coupled to V(t) and sources coupled to a ground potential, and further comprising parasitic NPN bipolar transistors formed by the NMOS drains acting as collectors and a P substrate or well regions of the NMOS transistor acting as bases and the NMOS sources acting as emitters, whereby Vt1 and Vt1 are the collector-base breakdown voltages of the parasitic NPN transistors respectively without and with bias applied to the NMOS gates, wherein Vt1<Vt1.
8. The circuit of claim 1 wherein Vt1 is within 20% of Vh.
9. The circuit of claim 2 wherein R1 and R2 are substantially equal.
10. A method for harmlessly clamping a transient voltage V(t) appearing on a node of an IC, comprising:
dividing the transient voltage V(t) to obtain a reduced transient voltage Vmi;
coupling the reduced voltage Vmi to a control terminal of an active device whose output terminal is coupled to a reference ground of the IC through a resistance, to produce an output voltage Vmo; and
substantially simultaneously coupling the output voltage Vmo to inputs of multiple parallel active devices whose power terminals are coupled between the node and the reference ground, wherein the output voltage Vmo is sufficient to reduce turn-on voltages of the multiple parallel active devices to a level sufficient to cause the multiple parallel devices to turn on substantially simultaneously at substantially voltage V(t), thereby clamping the transient voltage appearing at the node to a safe level.
11. The method of claim 10 wherein in the first coupling step comprises, coupling the reduced voltage to a control terminal of an active device whose output terminal is coupled to a reference ground of the IC through a resistor to produce an output voltage about a threshold voltage less than the reduced voltage.
12. The method of claim 10 wherein the dividing step and the first coupling step comprise, reducing the transient voltage by a Zener diode generated voltage to obtain an output voltage Vmo less than the transient voltage V(t).
13. The method of claim 10 further comprising, providing a guard band wherein the multiple parallel devices provide sufficient current carrying capacity to prevent occurrence of increased leakage in the IC after the ESD transient has passed.
14. A circuit for protecting a node of an IC against an ESD transient rising to voltage V(t) by substantially shunting the ESD transient to ground, the circuit comprising:
a master circuit responsive to V(t), producing an output voltage Vmo less than V(t) without triggering a breakdown in any component of the master circuit; and
a slave circuit comprising multiple parallel devices having power terminals coupled between the node and ground, and wherein the multiple parallel devices have common input terminals for receiving the output voltage Vmo of the master circuit, the output voltage being substantially simultaneously applied to all of the common input terminals, wherein the output voltage acting at the common input terminals reduces a breakdown voltage of at least one of the power terminals of each of the multiple parallel devices to a value less than or equal to the current ESD voltage V(t), thereby causing the power terminals to become conductive substantially simultaneously and shunt the EST transient to ground.
15. The device of claim 14 wherein the master circuit comprises a transient voltage divider responsive to V(t) and producing Vmo equal to a voltage that minimizes the breakdown voltage.
16. The device of claim 15 wherein the master circuit comprises a transistor having a threshold voltage Vth and producing Vmo equal to a voltage that minimizes the breakdown voltage.
17. The device of claim 14 wherein the master circuit comprises a capacitor of value C and one or more resistors series coupled to the capacitor and having a total resistance value of R, wherein the product RC is such that the during the ESD transient rise time to V(t), there is negligible voltage drop across the capacitor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electrical test connector comprising:
a substrate having a thickness, a top surface, an end edge, and a bottom surface;
a plurality of conductive probe tips connected to the substrate’s end edge;
a plurality of test paths, each connected to one of the probe tips and extending along the substrate; and
at least one of the test paths including an electrical component adjacent to the test path’s probe tip.
2. The electrical test connector as defined in claim 1, wherein the electrical component is a resistor.
3. The electrical test connector as defined in claim 1, wherein the probe tips have a length extending from the top surface to the bottom surface of the substrate.
4. The electrical test connector as defined in claim 3, wherein the thickness of the substrate is less than or equal to 15 mils (0.015 inch).
5. The electrical test connector as defined in claim 1, wherein each of the probe tips comprises a plurality of probe tip layers.
6. The electrical test connector as defined in claim 5, wherein each probe tip layer covers a smaller area than the probe tip layer it covers, creating a taper on the sides of the probe tip.
7. The electrical test connector as defined in claim 6, wherein a first probe tip layer is attached to the substrate’s end edge and subsequent probe tip layers are narrower than the first probe tip layer.
8. The electrical test connector as defined in claim 1, wherein the test paths comprise a plurality of transmission lines attached to the top surface of the substrate.
9. The electrical test connector as defined in claim 8, further comprising either a high-speed buffer andor a resistive element electrically connected to the transmission lines attached to the top surface of the substrate.
10. A method of manufacturing an electrical test connector comprising the steps of:
providing a substrate having a top surface and a bottom surface;
forming a plurality of transmission lines on the substrate’s top surface;
forming a patterned ground plane on the substrate’s bottom surface;
forming a conductive path connecting the ground plane on the bottom surface to selected transmission lines on the top surface;
separating the substrate into a plurality of strips, each strip having a top surface, an end edge, and a bottom surface;
forming a plurality of probe tips by placing a plurality of probe tip layers per probe tip on each strip’s end edge; and
separating an individual electrical test connector from each strip.
11. The method of manufacturing an electrical test connector of claim 10, further comprising the step of forming a resistor on each strip that is electrically connected to at least one of the transmission lines and a probe tip prior to the step of separating at least one electrical test connector from each strip.
12. The method of manufacturing an electrical test connector of claim 10, further comprising the step of cutting crenellations in each strip’s end edge between the probe tips.
13. The method of manufacturing an electrical test connector of claim 12, wherein the step of cutting crenellations in each strip’s end edge between the probe tips is performed prior to the step of separating at least one electrical test connector from each strip.
14. The method of manufacturing an electrical test connector of claim 11, further comprising the step of bringing any resistors that are out of specification into specification by trimming them.
15. The method of manufacturing an electrical test connector of claim 10, wherein the strips are stacked before the probe tips are formed on each strip’s end edge
16. The method of manufacturing an electrical test connector of claim 15, wherein a spacer is inserted between each strip as they are stacked.
17. The method of manufacturing an electrical test connector of claim 15, wherein the strips are unstacked prior to the step of separating at least one electrical test connector from each strip.
18. An electrical test connector comprising:
a substrate having a thickness, a top surface, an end edge, and a bottom surface;
a plurality of conductive probe tips having connected to the substrate’s end edge, wherein each of the probe tips comprises a plurality of probe tip layers; and
a plurality of test paths, each connected to one of the probe tips and extending along the substrate.
19. The electrical test connector as defined in claim 18, further comprising at least one of the test paths including an electrical component adjacent to the test path’s probe tip.
20. The electrical test connector as defined in claim 19, wherein the electrical component is a resistor.
21. The electrical test connector as defined in claim 18, wherein each probe tip layer covers a smaller area than the probe tip layer it covers, creating a taper on the sides of the probe tip.
22. The electrical test connector as defined in claim 18, wherein the test paths comprise a plurality of transmission lines attached to the top surface and a patterned ground plane on the bottom surface of the substrate.
23. The electrical test connector as defined in claim 22, further comprising a high-speed buffer andor a resistive network electrically connected to the transmission lines attached to the top surface of the substrate.
24. The electrical test connector as defined in claim 10, wherein each individual electrical test connector comprises a single probe tip.
25. The electrical test connector as defined in claim 10, wherein each individual electrical test connector comprises a plurality of probe tips.
26. The electrical test connector as defined in claim 10, wherein the conductive path is selected from the group comprising through hole vias formed from pre-drilled holes in the substrate, edge plating, edge printing, and conductive mechanical clips contacting the top surface and the bottom surface of the substrate.
27. The electrical test connector as defined in claim 26, wherein the spacing between the through hole vias is less than \xbc of the uppermost wavelength of the signal to be measured by the electrical test connector.