Author: claimsbot

1. An on-chip test circuit for testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, the on-chip test circuit comprising:
a flip-flop, for serially receiving, registering and serially outputting test patterns;
a mode selector, coupled to the power switch and the flip-flop, for controlling operation mode of the power switch according to a test indication signal, the test indication signal indicates whether the power switch is in test mode or not; and
a voltage level control circuit, coupled to the decoupling capacitance, for controlling voltage level of the decoupling capacitance;
wherein under test mode, the mode selector selects the test patterns serially output from the flip-flop into the power switch and the voltage level control circuit pre-charges or discharges the decoupling capacitance, so that the voltage level of the decoupling capacitance is analyzed for determining whether the power switch is passed or failed.
2. The on-chip test circuit of claim 1, further comprising:
a test result isolation element, coupled to the voltage level control circuit and the decoupling capacitance, for outputting test result provided by the power switch under test and for blocking test result test result provided by other power switches not being under test when the on-chip test circuit are used to test a plurality of power switches in multiple power domain.
3. The on-chip test circuit of claim 1, wherein the mode selector has:
a control terminal for receiving the test indication signal;
a first input terminal for receiving a power switch control signal;
a second input terminal for receiving the test patterns output from the flip-flop; and
an output terminal for coupling to the power switch and the voltage level control circuit;
wherein,
when the test indication signal indicates the power switch being under normal mode, the mode selector outputs the power switch control signal to the power switch; and
when the test indication signal indicates the power switch being under test mode, the mode selector outputs the test patterns from the flip-flop to the power switch.
4. The on-chip test circuit of claim 1, wherein the power switch includes a header type power switch and the voltage level control circuit is a discharge circuit for discharging charges in the decoupling capacitance.
5. The on-chip test circuit of claim 4, wherein the voltage level control circuit includes:
a logic gate, receiving a discharge signal and the output from the mode selector; and
a MOS transistor, coupled to the decoupling capacitance, for discharging the decoupling capacitance under control of an output from the logic gate.
6. The on-chip test circuit of claim 1, wherein the power switch includes a footer type power switch and the voltage level control circuit is a pre-charge circuit for pre-charging the decoupling capacitance.
7. The on-chip test circuit of claim 6, wherein the voltage level control circuit includes:
a logic gate, receiving a pre-charge signal and the output from the mode selector; and
a MOS transistor, coupled to the decoupling capacitance, for pre-charging the decoupling capacitance under control of an output from the logic gate.
8. The on-chip test circuit of claim 1, wherein:
the power switch includes a footer type power switch and a header type power switch; and
the voltage level control circuit includes a pre-charge circuit for pre-charging the decoupling capacitance and a discharge circuit for discharging the decoupling capacitance.
9. An on-chip test method for testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, the on-chip test method comprising:
controlling the power switch to enter a test mode under control of a test indication signal;
controlling charges stored in the decoupling capacitance;
controlling the power switch under control of test patterns; and
analyzing a voltage level at the decoupling capacitance for determining whether the power switch is passed or failed.
10. The on-chip test method of claim 9, wherein the power switch includes a header type power switch.
11. The on-chip test method of claim 10, wherein when the header type power switch being under ON test, the test method further comprising:
turning off the power switch, before the step of controlling charges stored in the decoupling capacitance;
turning on the power switch, before the analyzing step; and
the step of controlling charges stored in the decoupling capacitance comprising discharging charges stored in the decoupling capacitance.
12. The on-chip test method of claim 10, when the header type power switch being under OFF test, the test method further comprising:
turning off the power switch, before the step of controlling charges stored in the decoupling capacitance;
the step of controlling charges stored in the decoupling capacitance comprising discharging charges stored in the decoupling capacitance; and
the step of analyzing comprising measuring a leakage current flowing through the power switch.
13. The on-chip test method of claim 9, wherein the power switch includes a footer type power switch.
14. The on-chip test method of claim 13, wherein when the footer type power switch being under ON test, the test method further comprising:
turning off the power switch, before the step of controlling charges stored in the decoupling capacitance;
turning on the power switch, before the analyzing step; and
the step of controlling charges stored in the decoupling capacitance comprising pre-charging charges stored in the decoupling capacitance.
15. The on-chip test method of claim 13, wherein when the footer type power switch being under OFF test, the test method further comprising:
turning off the power switch, before the step of controlling charges stored in the decoupling capacitance;
the step of controlling charges stored in the decoupling capacitance comprising pre-charging charges stored in the decoupling capacitance; and
the step of analyzing comprising measuring a leakage current flowing through the power switch.
16. The on-chip test method of claim 9, wherein the power switch includes a header type power switch and a footer type power switch.
17. The on-chip test method of claim 16, wherein further comprising:
turning on one of the header type power switch and the footer type power switch when testing the other one.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for determining a location of an improved carrier signal emitted from a base station relative to a position of a communication device, the carrier signal having a signal strength and the communication device receiving signal strength information of the carrier signal from an operating wireless communications network, the method comprising the steps of:
receiving information of a signal strength at an adjacent location, wherein the adjacent location is determined by performing a lookup on a digital map, the receiving further comprising determining if the signal strength at the adjacent location is greater than the signal strength at a current location of the communication device, and if the signal strength of the adjacent location is less that of the signal strength at the current location, then locating a next adjacent grid reference in a 360 degree radius from the communication device; and
in response the received information of an improved signal strength being received at the adjacent location, displaying a direction of a position of the adjacent location on the communication device.
2. A method as claimed in claim 1 wherein the digital map comprises a grid reference depicting a location of a base station and geographical terrain.
3. A method as claimed in claim 1 wherein the digital map further comprises a signal strength emitted by the base station at a grid reference.
4. A method as claimed in claim 3, wherein the digital map further comprises statistical data comprising refraction and deflection characteristics of the terrain and an effect the statistical data has on the carrier signal strength at the grid reference.
5. A method as claimed in claim 1 wherein the digital map is maintained by a service provider.
6. A method as claimed in claim 5 wherein the digital map is requested from the service provider and stored on the communication device.
7. A method as claimed in claim 1 wherein an icon displays the direction of the adjacent location having improved signal strength on a display of the communication device.
8. A method as claimed in claim 7 wherein the icon is a signal strength direction indicator.
9. A method as claimed in claim 1 wherein a graphical map displays the direction of the adjacent location of the improved signal strength on the communication device.
10. A method as claimed in claim 1 wherein in response to an improved signal strength at the adjacent location, returning a ranked list of adjacent locations of improved signal strengths.
11. A system for determining a location of an improved carrier signal emitted from a base station relative to a position of a communication device, the carrier signal having a signal strength and the communication device receiving signal strength information of the carrier signal from an operating wireless communications network, the system comprising:
means for receiving information of a signal strength at an adjacent location, wherein the adjacent location is determined by performing a lookup on a digital map, wherein the means for receiving comprises means for determining if the signal strength at the adjacent location is greater than the signal strength at a current location of the communication device, and if the signal strength of the adjacent location is less that of the signal strength at the current location, then locating a next adjacent grid reference in a 360 degree radius from the communication device; and
in response the received information of an improved signal strength being received at the adjacent location, means for displaying a direction of a position of the adjacent location on the communication device.
12. A system as claimed in claim 11 wherein the digital map comprises a grid reference depicting a location of a base station and geographical terrain.
13. A system as claimed in claim 11 wherein the digital map further comprises a signal strength emitted by the base station at a grid reference.
14. A system as claimed in claim 12, wherein the digital map further comprises statistical data comprising refraction and deflection characteristics of the terrain and an effect the statistical data has on the signal strength at the grid reference.
15. A system as claimed in claim 11 wherein the digital map is maintained by a service provider.
16. A system as claimed in claim 15 wherein the digital map is requested from the service provider and stored on the communication device.
17. A system as claimed in claim 11 wherein an icon displays the direction of the adjacent location having improved signal strength on a display of the communication device.
18. A system as claimed in claim 17 wherein the icon is a signal strength direction indicator.
19. A system as claimed in claim 11 wherein a graphical map displays the direction of the adjacent location of the improved signal strength on the communication device.
20. A system as claimed in claim 11 further comprising means for returning a ranked list of adjacent locations of improved signal strengths, in response to an improved signal strength at the adjacent location.
21. A computer program product loadable into the internal memory of a digital computer, comprising software code portions for performing, when said product is run on a computer, the method of claim 1.
22. A service for determining a location of an improved carrier signal emitted from a base station relative to a position of a communication device, the carrier signal having a signal strength and the communication device receiving signal strength information of the carrier signal from an operating wireless communications network, the service comprising the steps of:
receiving information of a signal strength at an adjacent location, wherein the adjacent location is determined by performing a lookup on a digital map, the receiving further comprising determining if the signal strength at the adjacent location is greater than the signal strength at a current location of the communication device, and if the signal strength of the adjacent location is less that of the signal strength at the current location, then locating a next adjacent grid reference in a 360 degree radius from the communication device; and
in response to the received information of an improved signal strength being received at the adjacent location, displaying a direction of a position of the adjacent location on the communication device.

1. A method of fabricating a separation column for use with a gas chromatograph, comprising:
depositing a metal oxide by atomic layer deposition to create a stationary phase medium on said separation column.
2. The method of claim 1 wherein said metal oxide is aluminum oxide.
3. The method of claim 3 wherein said aluminum oxide is deposited as a plurality of layers with each layer deposited in a cycle comprising (a) exposure to trimethylaluminum (b) purge (c) exposure to water (d) and purge.
4. The method of claim 3 wherein each cycle deposits a layer of about 1-2 angstroms.
5. The method of claim 2 wherein said aluminum oxide is functionalized by exposure to silane.
6. The method of claim 5 wherein said silane is an alkylsilane.
7. The method of claim 6 wherein said silane is chlorodimethyloctadecylsilane.
8. The method of claim 2 wherein said aluminum oxide is functionalized by exposure to a plurality of silanes.
9. A detector comprising:
a micro-purge extractor in communication with a micro-scale gas chromatography column for the extraction and analysis of water organic compounds from an aqueous sample;
said micro-purge extractor having a cavity in communication with a sample inlet port, a purge gas inlet port, a waste outlet port and a purged water organic compound outlet port;
said sample inlet port adapted to receive an aqueous sample;
said purge gas inlet port, spaced apart from said sample inlet port, and adapted to receive inert gas which is used to purge water organic compounds from said cavity of said micro-purge extractor;
said waste outlet opposingly located from said purge outlet port, said waste outlet adapted for draining water from the chip;
said purge outlet in communication with a micro-thermal preconcentrator;
said micro-thermal preconcentrator adapted to adsorb and desorb water organic compounds;
at least one resistive heating element that when activated, causes said water organic compounds to be desorbed; and
said micro-scale gas chromatography column adapted to separate said water organic compounds and a micro-thermal conductivity detector for identifying said water organic compounds.
10. The detector of claim 9 wherein said separation column has an aluminum oxide stationary phase medium.
11. The detector of claim 10 wherein said aluminum oxide is functionalized by exposure to silane.
12. The method of claim 11 wherein said silane is an alkylsilane.
13. The method of claim 11 wherein said silane is chlorodimethyloctadecylsilane.
14. The method of claim 10 wherein said aluminum oxide is functionalized by exposure to a plurality of silanes.
15. The detector of claim 9 wherein said purge outlet port and said sample inlet port are located on a top side of said micro-purge extractor, said purge gas inlet is located on a side of said micro-purge extractor, and said waste outlet port is located on a bottom side of said micro-purge extractor.
16. A detector for detecting hazardous air pollutants at parts-per-billion concentrations in complex mixtures comprising:
a microfabricated preconcentrator;
a separation column with an on-chip thermal conductivity detector;
a controller for controlling flow and thermal management; and
a user interface.
17. The detector of claim 16 wherein said thermal conductivity detector includes a first resistor located at an inlet of said separation column and a second resistor located at an outlet of said separation column.
18. The detector of claim 16 wherein said separation column includes a medium comprised of silica a nanoparticle layer with a Tenax TA coating.
19. The detector of claim 16 wherein said separation column includes at least one channel that linearly decreases in width.
20. The detector of claim 16 wherein said separation column includes at least one channel that decreases in width in a stepwise fashion.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A forward-forward converter FFC having a first gapped transformer with a primary winding for receiving electrical energy from a source of electrical power and a secondary winding coupled to said primary winding, said converter also having a power switch for intermittently coupling said transformer to said source of electrical power and a clamp switch for intermittently coupling said transformer to said clamp capacitor, said converter, comprising:
a second gapped transformer, having an input winding coupled to said secondary winding of the first transformer, configured to form an intermediate circuit mesh and extend said zero-voltage switching possibility said converter and output energy transfer, through an output winding coupled to said input winding, during conduction of said clamp switch.
2. The forward-forward converter as recited in claim 1 wherein a reverse current circulating in said intermediate circuit mesh is coupled to said primary winding to achieve zero-voltage switching (ZVS) of said power and clamp switches.
3. The forward-forward converter as recited in claim 2 wherein a reverse current circulates during an interval between non-conducting and conducting periods of said power and clamp switches.
4. The forward-forward converter as recited in claim 2 further to use leakage inductance in said intermediate circuit mesh to provide said reverse current.
5. The forward-forward converter as recited in claim 2 further to use leakage inductance in series with auxiliary inductance in said intermediate circuit mesh to provide said reverse current.
6. The forward-forward converter as recited in claim 1 wherein said primary, secondary and input winding use a same voltage phase, and said output winding uses an opposite voltage phase.
7. The forward-forward converter as recited in claim 1 wherein said primary, secondary and input winding use a same voltage phase, and said output windings use a same and an opposite voltage phase.
8. The forward-forward converter as recited in claim 1 wherein a volt-second requirement for said second transformer is less than said first transformer.
9. The forward-forward converter as recited in claim 1 wherein each of said power and clamp switches employ a MOSFET having parasitic capacitance.
10. A method of conversion energy for use with a forward-forward converter, comprising:
employing a first transformer with a primary winding for receiving electrical energy from a source of electrical power and a secondary winding coupled to said primary winding, said converter also having a power switch for intermittently coupling said transformer to said source of electrical power and a clamp switch for intermittently coupling said transformer to said clamp capacitor, said converter; and
further employing a second transformer, having an input winding coupled to said secondary winding, that forms an intermediate circuit mesh and extend said output energy transfer, through an output winding coupled to said input winding, during conduction of said clamp switch.
11. The method as recited in claim 10 wherein a second transformer, having an input winding coupled to said secondary winding, that forms an intermediate circuit mesh and extend said output energy transfer, through the output windings coupled to said input winding, during conduction of said power and clamp switches.
12. The method as recited in claim 10 wherein a reverse current circulating in said intermediate circuit mesh is coupled to say primary winding and extends zero-voltage switching (ZVS) of said power and clamp switches.
13. The method as recited in claim 10 wherein said reverse current circulates during the intervals between non-conducting and conducting periods of said power and clamp switches.
14. The method as recited in claim 12 further comprising using a leakage inductance in said intermediate circuit mesh to provide said reverse current.
15. The method as recited in claim 12 further comprising using a leakage inductance in series with auxiliary inductance in said intermediate circuit mesh to provide said reverse current.
16. The method as recited in claim 10 wherein said primary, secondary and input windings use a same voltage phase, said output winding uses opposite voltage phase.
17. The method as recited in claim 11 wherein said primary, secondary and input windings use a same voltage phase, said output windings use a same and opposite voltage phase.
18. The method as recited in claim 10 wherein a volt-second requirement for said second transformer is less than said first transformer.
19. The method as recited in claim 10 wherein each of said power and clamp switches uses a MOSFET having a parasitic capacitance.
20. A forward-forward converter (FFC), comprising:
an input voltage a source of electrical power;
power and clamp switches coupled to said input voltage;
a conversion circuit, including:
a first transformer, having a primary winding coupled to said power and clamp switches and a secondary winding coupled to said primary winding that provides an output energy transfer of said forward-forward converter during conduction of said power switch, and
a second transformer, having an input winding coupled to secondary winding, that forms an intermediate circuit mesh and extends said output energy transfer, through an output winding coupled to said input winding, during conduction of said clamp switch;
a rectifier circuit, coupled to said conversion circuit, that provides rectification of said output energy transfer; and
an output filter, coupled to said rectifier circuit, that provides an output voltage from said rectification of said output energy transfer.
21. The converter as recited in claim 20 wherein a second transformer, having an input winding coupled to secondary winding, that forms an intermediate circuit mesh and extends said output energy transfer, through the output windings coupled to said input winding, during conduction of said power and clamp switches;
22. The converter as recited in claim 20 wherein a reverse current circulating in said intermediate circuit mesh is coupled to said primary winding to extend zero-voltage switching (ZVS) opportunity of said power and clamp switches.
23. The converter as recited in claim 22 wherein said reverse current circulates during an interval between non-conducting and conducting periods of said power and clamp switches.
24. The converter as recited in claim 22 wherein further comprising a leakage inductance in said intermediate circuit mesh to provide said reverse current.
25. The converter as recited in claim 22 wherein further comprising a leakage inductance in series with an auxiliary inductance in said intermediate circuit mesh to provide said reverse current.
26. The converter as recited in claim 22 wherein said primary, secondary and input windings use a same voltage phase, and output winding uses an opposite voltage phase.
27. The converter as recited in claim 21 wherein said primary, secondary and input windings and one output use a same voltage phase, and other output winding uses an opposite voltage phase.
28. The converter as recited in claim 20 wherein a volt-second requirement for said second transformer is less than first transformer.
29. The converter as recited in claim 20 wherein each of said power and clamp switches employs a MOSFET having a parasitic capacitance.