Author: claimsbot

1. A method comprising:
providing an integrated circuit having a plurality of terminals for making electrical connection to the integrated circuit;
providing at least one device adjacent an outer edge of the integrated circuit, the at least one device comprising at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation;
coupling the at least one device to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use; and
forming a plurality of capacitors as the at least one device, wherein the plurality of capacitors comprise a common first electrode, the common first electrode comprising a continuous outer metal conductor around the outer edge of the integrated circuit, and a plurality of second electrodes of the plurality of capacitors, the plurality of second electrodes comprising an electrically discontinuous inner metal conductor located between the plurality of terminals and the first electrode.
2. The method of claim 1 further comprising:
forming the at least one device as an inductor that couples inductance to the one or more functional circuits during a non-testing operation of the integrated circuit.
3. The method of claim 2 further comprising:
forming the inductor with a continuous metal conductor having a first end electrically connected to a first terminal of a predetermined one of the one or more functional circuits and a second end electrically connected to a second terminal of the predetermined one of the one or more functional circuits, the inductor looping between the outer edge and the plurality of terminals at least around the integrated circuit once.
4. The method of claim 1, wherein each of the plurality of capacitors couples capacitance to any of the one or more functional circuits during non-testing operation of the integrated circuit.
5. The method of claim 1 further comprising:
forming the at least one device between an outer edge of the integrated circuit and the plurality of terminals.
6. The method of claim 1, wherein the common first electrode is coupled to a first power supply pad and wherein one of the plurality of second electrodes is coupled to a second power supply pad.
7. A method comprising:
providing an integrated circuit having a plurality of terminals for making electrical connection to the integrated circuit;
providing at least one device adjacent a periphery of the integrated circuit, a portion of the at least one device comprising a first metal conductor extending entirely around the integrated circuit to form an edge seal for protecting the integrated circuit during die singulation; and
coupling the at least one device to a functional circuit within the integrated circuit by routing the first metal conductor to the functional circuit, the functional circuit implementing non-test functions within the integrated circuit by using the at least one device, wherein forming the at least one device comprises:
forming the at least one device as a plurality of capacitors comprising a common first electrode comprising a continuous outer metal conductor around the periphery of the integrated circuit, and a plurality of second electrodes of the plurality of capacitors comprising an electrically discontinuous metal conductor located between the plurality of terminals and the first electrode.
8. The method of claim 7 further comprising:
forming the at least one device between an outer edge of the integrated circuit and the plurality of terminals.
9. The method of claim 8 further comprising:
forming the at least one device as an inductor.
10. The method of claim 9 further comprising:
forming the inductor with a continuous metal conductor having a first end electrically connected to a first terminal of the functional circuit and a second end electrically connected to a second terminal of the functional circuit, the inductor looping around the periphery of the integrated circuit at least once.
11. The method of claim 7, wherein the common first electrode is coupled to a first power supply pad and wherein one of the plurality of second electrodes is coupled to a second power supply pad.
12. A method comprising:
providing an integrated circuit having a plurality of terminals for making electrical connection to the integrated circuit;
providing at least one device adjacent an outer edge of the integrated circuit, the at least one device comprising at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation;
coupling the at least one device to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use; and
forming the at least one device as an inductor that couples inductance to the one or more functional circuits during a non-testing operation of the integrated circuit, wherein forming the at least one device as the inductor comprises forming the inductor with a continuous metal conductor having a first end electrically connected to a first terminal of a predetermined one of the one or more functional circuits and a second end electrically connected to a second terminal of the predetermined one of the one or more functional circuits, the inductor looping between the outer edge and the plurality of terminals at least around the integrated circuit once, and wherein providing the at least one device further comprises:
forming a plurality of capacitors comprising a common first electrode, the common first electrode comprising a continuous outer metal conductor around the outer edge of the integrated circuit, and forming a plurality of second electrodes of the plurality of capacitors, the plurality of second electrodes comprising an electrically discontinuous inner metal conductor located between the plurality of terminals and the first electrode.
13. The method of claim 12 further comprising:
forming the at least one device as a capacitor that couples capacitance to the one or more functional circuits during a non-test operation of the integrated circuit.
14. The method of claim 12, wherein each of the plurality of capacitors couples capacitance to any of the one or more functional circuits during non-testing operation of the integrated circuit.
15. The method of claim 12, wherein the common first electrode is coupled to a first power supply pad and wherein one of the plurality of second electrodes is coupled to a second power supply pad.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A button assembly, comprising:
a switch body;
a tactile switch coupled with a first surface of the switch body;
a polymeric film extending over and surrounding the tactile switch, wherein the polymeric film is joined to the switch body by a weld, the weld defining a plurality of gaps that allow air to pass into and out of an interior volume defined by the switch body and the polymeric film without allowing liquids to enter the interior volume through a joint formed by the weld; and
a protective layer coupled to a second surface of the switch body, the second surface being positioned opposite the first surface, wherein the protective layer prevents ingress of liquids into the switch body through a plurality of tooling pin holes defined by the second surface of the switch body.
2. The button assembly as recited in claim 1, wherein the plurality of gaps are covered by pieces of pressure sensitive adhesive subsequent to the button assembly being installed in an electronic device.
3. The button assembly as recited in claim 1, wherein the plurality of gaps in the weld are defined by a series of troughs defined by the first surface of the switch body.
4. The button assembly as recited in claim 1, wherein the polymeric film is joined to the switch body by a plurality of welds that cooperate to form a channel through which surface tension prevents moisture intrusion into the interior volume.
5. The button assembly as recited in claim 4, wherein a portion of each of two of the plurality of welds run substantially parallel to one another to define the channel.
6. The button assembly as recited in claim 5, wherein the channel is no narrower than about 0.03 mm and wherein the channel extends for at least two millimeters.
7. The button assembly as recited in claim 1, wherein the plurality of gaps is closed by adhering the polymeric film to the switch body with a piece of pressure sensitive adhesive.
8. The button assembly as recited in claim 1, further comprising a plurality of welds that close the plurality of gaps after the button assembly is mounted within an electronic device.
9. The button assembly as recited in claim 8, wherein an angle formed by an intersection between the weld and each of the plurality of welds is greater than 90 degrees.
10. An electronic device, comprising:
a housing;
a display assembly, comprising a substantially transparent display cover; and
a button assembly, comprising:
a button cap positioned within an opening defined by the substantially transparent display cover and configured to receive a user input,
a switch body,
a tactile switch coupled with a first surface of the switch body and configured to receive the user input by way of the button cap,
a polymeric film coupled to the switch body and surrounding the tactile switch so that an interior volume is defined by the polymeric film and the switch body, wherein an interface between the polymeric film and the switch body prevents liquids from entering the interior volume through the interface, and
a protective layer coupled to a second surface of the switch body, the second surface being positioned opposite the first surface, wherein the protective layer prevents ingress of liquids into the switch body through a plurality of tooling pin holes defined by the second surface of the switch body.
11. (canceled)
12. The button assembly as recited in claim 10, wherein the protective layer is coupled to the switch body by a weld.
13. The button assembly as recited in claim 12, wherein the weld joining the protective layer to the switch body defines a plurality of gaps that allow air to pass through the interface between the protective layer and the switch body, and wherein air passing through the plurality of gaps prevents a pressure build up within the interior volume sufficient to reduce performance of the polymeric film during heating and cooling of the button assembly.
14. A button bracket for supporting button circuitry, the button bracket comprising:
a rigid substrate defining a plurality of fastener openings;
a tactile switch mounted to a first end of the rigid substrate; and
a snap clip coupled with a second end of the rigid substrate,
wherein the rigid substrate is configured to be attached to a housing body by way of the fastener openings and wherein the snap clip is configured to receive a rail extending from a protective cover that cooperates with the housing body to define an internal volume for an electronic device.
15. The button bracket as recited in claim 14, wherein the snap clip is welded to the rigid substrate.
16. The button bracket as recited in claim 14, wherein the rigid substrate defines a slot upon which the tactile switch is mounted.
17. The button bracket as recited in claim 14, wherein the snap clip is formed from a stamped sheet of metal.
18. The button bracket as recited in claim 14, wherein the button bracket is configured to be mounted to a sidewall of the housing body.
19. The button bracket as recited in claim 18, wherein the button bracket is configured to align the tactile switch with a user actuated button disposed through an opening defined by the sidewall.
20. The button bracket as recited in claim 14, wherein the snap clip is configured to retain the rail, thereby securing the protective cover to the housing body.

1. An interpolator, comprising:
a capacitor;
a reset circuit configured to charge said capacitor to an initial voltage value during a first predetermined time period;
an initialization circuit configured to control charging of said capacitor during a second predetermined time period, said initialization circuit including a reference voltage source and a diode bridge;
a time to voltage conversion circuit configured to discharge said capacitor during a third predetermined time period; and
a sampling period current source configured to charge said capacitor during a fourth predetermined time period,
wherein charging current is supplied at least in part to said capacitor by a current mirror transistor pair coupled to said diode bridge,
whereby improved capacitor voltage settling time is provided.
2. The interpolator of claim 1, further comprising:
an analog to digital converter configured to sample voltage across said capacitor.
3. The interpolator of claim 1, wherein said analog to digital converter is configured to sample the capacitor voltage level a plurality of times during the second predetermined period, whereby plural samples may be provided for process to cancel effects of slow settling during capacitor initialization.
4. The interpolator of claim 3, wherein said analog to digital converter is configured to sample the capacitor voltage level twice during the second predetermined period.
5. The interpolator of claim 2, wherein said analog to digital converter is configured to sample the capacitor voltage level a plurality of times during the fourth predetermined period, whereby plural samples may be provided for process to improve sampling resolution and accuracy.
6. The interpolator of claim 5, wherein said analog to digital converter is configured to sample the capacitor voltage level four times during said fourth predetermined period.
7. The interpolator of claim 2, further comprising:
a temperature sensor,
whereby temperature calibration tables may be provided prior to interpolator operation and interpolator operational temperature data may be provided for compensation of temperature related measurement variations in accordance with previously obtained temperature calibration tables.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A liquid crystal display for displaying a color image, comprising:
a plurality of data signal lines;
a plurality of scanning signal lines intersecting the data signal lines; and
a plurality of pixel-forming portions each related to one of the intersections made by the data signal lines and the scanning lines, and disposed in a matrix pattern;
each of the pixel-forming portions including:
a switching element turned on and off by the scanning signal line passing the related intersection and serving as a feeding scanning signal line;
a pixel electrode connected via the switching element to the data signal line passing the related intersection and serving as a feeding data signal line;
a counter electrode common to the pixel-forming portions for holding predetermined capacities between the counter electrode and the pixel electrodes; and
a liquid crystal layer common to the pixel-forming portions, sandwiched between the pixel electrodes and the counter electrode;
wherein, simultaneously-selected pixel electrodes that are a group of the pixel electrodes each connected to one of the switching elements turned on and off by a same scanning signal line, are assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions, and in a horizontally periodical pattern having a cycle of \u201cup, down, up\u201d or \u201cdown, up, down\u201d as to which of the up row and the down row is selected in the assignment of three pixel electrodes.
2. The liquid crystal display according to claim 1, further comprising:
an output circuit outputting and thereby feeding the data signal lines with data signals for displaying the color image so that a polarity of voltage applied to the pixel electrode is the same for the simultaneously-selected pixel electrodes and is altered for each horizontal scanning period; and
a delaying circuit selectively delaying the feeding of the data signal to the data signal lines feeding the pixel-forming portions including the simultaneously-selected pixel electrodes assigned to the up row of the two rows, by a single cycle of the horizontal scanning period.
3. A liquid crystal display for displaying a color image, comprising:
a plurality of data signal lines;
a plurality of scanning signal lines intersecting the data signal lines; and
a plurality of pixel-forming portions each related to one of the intersections made by the data signal lines and the scanning lines, and disposed in a matrix pattern;
each of the pixel-forming portions including:
a switching element turned on and off by the scanning signal line passing the related intersection and serving as a feeding scanning signal line;
a pixel electrode connected via the switching element to the data signal line passing the related intersection and serving as a feeding data signal line;
a counter electrode common to the pixel-forming portions for holding predetermined capacities between the counter electrode and the pixel electrodes; and
a liquid crystal layer common to the pixel-forming portions, sandwiched between the pixel electrodes and the counter electrode;
wherein simultaneously-selected pixel electrodes that are a group of the pixel electrodes each connected to one of the switching elements turned on and off by a same scanning signal line, are assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions, and in a horizontally periodical pattern having a cycle of \u201cup, down, up, down, up, down, down, up, down, up, down, up\u201d or \u201cdown, up, down, up, down, up, up, down, up, down, up, down\u201d as to which of the up row and the down row is selected in the assignment of twelve pixel electrodes.
4. The liquid crystal display according to claim 3, further comprising:
an output circuit outputting and thereby feeding the data signal lines with data signals for displaying the color image so that a polarity of voltage applied to the pixel electrode is the same for the simultaneously-selected pixel electrodes and is altered for each horizontal scanning period; and
a delaying circuit selectively delaying the feeding of the data signal to the data signal lines feeding the pixel-forming portions including the simultaneously-selected pixel electrodes assigned to the up row of the two rows, by a single cycle of the horizontal scanning period.
5. A column electrode driving circuit supplying data signals for displaying an image in a liquid crystal panel including: a plurality of data signal lines; a plurality of scanning signal lines intersecting the data signal lines; and a plurality of pixel-forming portions each related to one of the intersections made by the data signal lines and the scanning lines, and disposed in a matrix pattern; simultaneously-selected pixel electrodes that are a group of the pixel electrodes included in the pixel-forming portions driven by a same scanning signal line, being assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions; the column electrode driving circuit comprising:
an output circuit outputting and thereby feeding the data signal lines with the data signals so that a polarity of voltage applied to the pixel electrode is the same for the simultaneously-selected pixel electrodes and is altered for each horizontal scanning period; and
a delaying circuit delaying the feeding of the data signal to part of the plurality of data signal lines;
wherein the simultaneously-selected pixel electrodes are assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions, and in a horizontally periodical pattern having a cycle of \u201cup, down, up\u201d or \u201cdown, up, down\u201d as to which of the up row and down row is selected in the assignment of three pixel electrodes;
the delaying circuit delaying the feeding of the signal to the data signal lines feeding the pixel-forming portions including the simultaneously-selected pixel electrodes assigned to the up row of the two rows, by a single cycle of the horizontal scanning period.
6. The column electrode driving circuit according to claim 5, further comprising a holding circuit holding image data of an image to be displayed in the liquid crystal panel, sequentially, line by line, for a single cycle of the horizontal scanning period, and outputting an internal image signal carrying the line of the image data held within;
wherein the output circuit outputs the data signals based on the internal image signal so that a polarity of voltage applied to the pixel electrode is the same for the simultaneously-selected pixel electrodes and is altered for each horizontal scanning period;
the delaying circuit being placed between the holding circuit and the outputting circuit, and selectively delaying the internal image signal for the output of the data signal from the output circuit to the data signal lines related to the pixel-forming portions including the simultaneously-selected pixel electrodes assigned to the up row of the two rows, by a single cycle of the horizontal scanning period.
7. A method of driving a liquid crystal panel, based on color image data, the liquid crystal panel including: a plurality of data signal lines; a plurality of scanning signal lines intersecting the data signal lines; and a plurality of pixel-forming portions each related to one of the intersections made by the data signal lines and the scanning lines, and disposed in a matrix pattern; simultaneously-selected pixel electrodes that are a group of the pixel electrodes included in the pixel-forming portions driven by a same scanning signal line, being assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions; the method comprising:
a scan driving step of feeding the scanning signal lines with scanning signals for alternate and sequential selection of one from the scanning signal lines for each horizontal scanning period;
a data driving step of feeding the data signal lines with data signals for displaying an image represented by the color image data so that a polarity of voltage applied to the pixel electrode is the same for the simultaneously-selected pixel electrodes and is altered for each horizontal scanning period; and
a selection delaying step of selectively delaying the feeding of the data signal to the data signal lines feeding the pixel-forming portions including the simultaneously-selected pixel electrodes assigned to the up row of the two rows, by a single cycle of the horizontal scanning period;
wherein the pixel-forming portions having their respective pixel electrodes assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions and in a horizontally periodical pattern having a cycle of \u201cup, down, up\u201d or \u201cdown, up, down\u201d as to which of the up row and the down row is selected in the assignment of three pixel electrodes are driven by a same scanning signal line in the scan driving step.
8. A method of driving a liquid crystal panel, based on color image data, the liquid crystal panel including: a plurality of data signal lines; a plurality of scanning signal lines intersecting the data signal lines; and a plurality of pixel-forming portions each related to one of the intersections made by the data signal lines and the scanning lines, and disposed in a matrix pattern; simultaneously-selected pixel electrodes that are a group of the pixel electrodes included in the pixel-forming portions driven by a same scanning signal line, being assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions; the method comprising:
a scan driving step of feeding the scanning signal lines with scanning signals for alternate and sequential selection of one from the scanning signal lines for each horizontal scanning period;
a data driving step of feeding the data signal lines with data signals for displaying an image represented by the color image data so that a polarity of voltage applied to the pixel electrode is the same for the simultaneously-selected pixel electrodes and is altered for each horizontal scanning period; and
a selection delaying step of selectively delaying the feeding of the data signal to the data signal lines feeding the pixel-forming portions including the simultaneously-selected pixel electrodes assigned to the up row of the two rows, by a single cycle of the horizontal scanning period;
wherein the pixel-forming portions having their respective pixel electrodes assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions and in a horizontally periodical pattern having a cycle of \u201cup, down, up, down, up, down, down, up, down, up, down, up\u201d or \u201cdown, up, down, up, down, up, up, down, up, down, up, down\u201d as to which of the up row and the down row is selected in the assignment of twelve pixel electrodes are driven by a same scanning signal line in the scan driving step.
9. A column electrode driving circuit supplying data signals for displaying an image in a liquid crystal panel including: a plurality of data signal lines; a plurality of scanning signal lines intersecting the data signal lines; and a plurality of pixel-forming portions each related to one of the intersections made by the data signal lines and the scanning lines, and disposed in a matrix pattern; simultaneously-selected pixel electrodes that are a group of the pixel electrodes included in the pixel-forming portions driven by a same scanning signal line, being assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions; the column electrode driving circuit comprising:
an output circuit outputting and thereby feeding the data signal lines with the data signals so that a polarity of voltage applied to the pixel electrode is the same for the simultaneously-selected pixel electrodes and is altered for each horizontal scanning period; and
a delaying circuit delaying the feeding of the data signal to part of the plurality of data signal lines;
wherein the simultaneously-selected pixel electrodes are assigned dispersedly to two mutually adjacent up and down rows of the matrix of pixel-forming portions, and in a horizontally periodical pattern having a cycle of \u201cup, down, up, down, up, down, down, up, down, up, down, up\u201d or \u201cdown, up, down, up, down, up, up, down, up, down, up, down\u201d as to which of the up row and down row is selected in the assignment of twelve pixel electrodes;
the delaying circuit delaying the feeding of the signal to the data signal lines feeding the pixel-forming portions including the simultaneously-selected pixel electrodes assigned to the up row of the two rows, by a single cycle of the horizontal scanning period.
10. The column electrode driving circuit according to claim 9, further comprising a holding circuit holding image data of an image to be displayed in the liquid crystal panel, sequentially, line by line, for a single cycle of the horizontal scanning period, and outputting an internal image signal carrying the line of the image data held within;
wherein the output circuit outputs the data signals based on the internal image signal so that a polarity of voltage applied to the pixel electrode is the same for the simultaneously-selected pixel electrodes and is altered for each horizontal scanning period;
the delaying circuit being placed between the holding circuit and the outputting circuit, and selectively delaying the internal image signal for the output of the data signal from the output circuit to the data signal lines related to the pixel-forming portions including the simultaneously-selected pixel electrodes assigned to the up row of the two rows, by a single cycle of the horizontal scanning period.