Author: claimsbot

1. A method for treating a diabetic vascular complication comprising administering to a subject in need thereof a therapeutically effective amount of an extract product of a Dioscorea species.
2. The method according to claim 1, wherein the extract product of the Dioscorea species is administered orally.
3. The method according to claim 1, wherein the Dioscorea species is Dioscorea alata L. cv. Phyto characterized by a randomly amplified polymorphic DNA (RAPD) fingerprint comprising the following 14 DNA bands when the genomic DNA of the Dioscorea species is amplified with a primer of SEQ ID NO: 9: 428 bp, 452 bp, 537 bp, 602 bp, 723 bp, 817 bp, 934 bp, 1140 bp, 1242 bp, 1478 bp, 1641 bp, 1904 bp, 2151 bp and 2918 bp, when genomic DNA of the Dioscorea species is amplified with a primer of SEQ ID NO: 9.
4. The method according to claim 1, wherein the extract product of the Dioscorea species is prepared by a process comprising the steps of:
(a) mixing a tuber of the Dioscorea species with an alcohol-based solvent in the presence of acetic acid to obtain an extract composition;
(b) subjecting the extract composition obtained in step (a) to a separating treatment to obtain a soluble fraction; and
(c) removing the solvent from the soluble fraction obtained in step (b) to obtain the extract product of the Dioscorea species.
5. The method according to claim 4, wherein the alcohol-based solvent is a methanol-based solvent, an ethanol-based solvent, or a mixture thereof.
6. The method according to claim 1, wherein the extract product of the Dioscorea species is prepared by a process comprising the steps of:
(a) immersing a tuber of the Dioscorea species in a 1% acetic acid solution;
(b) grinding the acetic acid-treated tuber of the Dioscorea species;
(c) lyophilizing the ground and acetic acid-treated tuber of the Dioscorea species; to produce a ground, lyophilized and, acetic acid-treated tuber of the Dioscorea species;
(d) mixing at least a portion of the ground, lyophilized and acetic acid-treated tuber of the Dioscorea species of step (c) with an alcohol-based solvent in a presence of an about 1% acetic acid solution to obtain an extract composition;
(e) subjecting the extract composition obtained in step (d) to a separating treatment to obtain a soluble fraction; and
(f) removing the solvent from the soluble fraction obtained in step (e) to obtain the extract product of the Dioscorea species.
7. The method according to claim 6, wherein the alcohol-based solvent is a methanol-based solvent, an ethanol-based solvent, or a mixture thereof.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate, the method comprising:
etching the electronic chips;
detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure; and
adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.
2. The method according to claim 1, wherein detecting information comprises analyzing volatile matter in an environment of the electronic chips which volatile matter is impacted by an etching product generated by removing material of the indicator structure from the electronic chips by the etching.
3. The method according to claim 2, wherein the analyzed volatile matter is plasma used for plasma etching and being modified by the at least partial removal of the indicator structure.
4. The method according to claim 3, wherein analyzing the plasma is performed by at least one of the group consisting of Optical Emission Spectroscopy, and Coherent Anti Stokes Raman Scattering.
5. The method according to claim 2, wherein the analyzed volatile matter is effluent gas generated when removing material of the indicator structure by plasma etching.
6. The method according to claim 5, wherein analyzing the effluent gas is performed by at least one of the group consisting of Optical Emission Spectroscopy, and Mass Spectroscopy.
7. The method according to claim 1, wherein the indicator structure comprises one of the group consisting of dopant, implanted material, and a deposited layer.
8. The method according to claim 1, wherein the etching is a selective etching so that an etching rate of material of the indicator structure is different from an etching rate of material next to the indicator structure.
9. The method according to claim 1, wherein the plurality of packaged electronic chips being connected to one another in the common substrate comprise a semiconductor wafer being divided into the electronic chips by mold structures as package.
10. The method according to claim 1, wherein adjusting the processing comprises at least one of the group consisting of stopping the etching, modifying an etching rate, modifying an etch parameter, modifying the etch process, and continuing the etching with the same etch conditions or with modified etch conditions for a predefined additional etching time interval.
11. The method according to claim 1, wherein the indicator structure is a continuous or discontinuous indicator layer embedded at a constant depth level within all electronic chips.
12. The method according to claim 1, comprising:
stopping the etching;
subsequently singularizing the electronic chips.
13. A method of processing a plurality of electronic chips being connected to one another by a common substrate, the method comprising:
plasma etching the electronic chips simultaneously;
detecting volatile matter in an environment of the plasma-etched electronic chips to thereby derive information indicative of an exposure of an indicator layer embedded within the electronic chips and being exposed after the etching has removed chip material above the indicator layer, wherein the volatile matter is impacted by the exposure of the indicator layer; and
adjusting the plasma etching upon detecting the exposure of the indicator layer.
14. The method according to claim 13, wherein processing the plurality of electronic chips comprises processing a plurality of electronic chips being packaged by a mold structure.
15. A device for processing a plurality of packaged electronic chips being connected to one another in a common substrate, the device comprising:
etching means configured for etching the electronic chips;
detection means configured for detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure; and
control means being supplied with the detected information and being configured for adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.
16. The device according to claim 15, wherein the detection means are configured for detecting the information by analyzing volatile matter in an environment of the electronic chips which volatile matter is impacted by an etching product generated by removing material of the indicator structure from the electronic chips by the etching.
17. The device according to claim 16, wherein the analyzed volatile matter is plasma used for plasma etching and being modified by the least partial removal of the indicator structure.
18. The device according to claim 16, wherein the analyzed volatile matter is effluent gas generated when removing material of the indicator structure by plasma etching.
19. A device for processing a plurality of electronic chips being connected to one another by a common substrate, the device comprising:
a plasma etching unit configured for plasma etching the electronic chips simultaneously;
a detection unit configured for detecting volatile matter in an environment of the plasma-etched electronic chips to thereby derive information indicative of an exposure of an indicator layer embedded within the electronic chips and being exposed after the etching has removed chip material above the indicator layer, wherein the volatile matter is impacted by the exposure of the indicator layer; and
a control unit being supplied with the information and being configured for adapting the processing upon detecting the exposure of the indicator layer.
20. An article, comprising:
a substrate;
a plurality of electronic chips being connected to one another within the substrate;
an indicator layer embedded within the electronic chips;
wherein the indicator layer is configured to be at least partially removable from the electronic chips by plasma etching so that its plasma etching product impacts volatile matter in an environment of the electronic chips so that the exposure of the indicator layer is detectable by analyzing the volatile matter.
21. The article according to claim 20, comprising a mold structure by which the plurality of electronic chips are packaged.
22. The article according to claim 20, wherein the substrate comprises a plate-shaped wafer comprising the plurality of electronic chips as sections of the wafer.
23. The article according to claim 20, wherein the substrate is a plate-shaped mold structure comprising a plurality of recesses each accommodating a respective one of the plurality of electronic chips.
24. The article according to claim 20, wherein the substrate is a plate-shaped mold structure comprising a recess accommodating a wafer comprising the plurality of electronic chips as sections of the wafer.
25. An electronic chip, comprising:
a semiconductor substrate;
at least one integrated circuit component being integrated in the semiconductor substrate;
an indicator layer forming an exterior surface portion of the semiconductor substrate, wherein the indicator layer is configured to be at least partially removable by plasma etching so that its plasma etching product impacts volatile matter in an environment of the semiconductor substrate so that the exposure of the indicator layer is detectable by analyzing the volatile matter;
a mold structure covering at least a part of the semiconductor substrate.

What is claimed is:

1. An electric apparatus comprising:
a power supply unit that has terminals to supply power to a circuit board; and
a circuit board that can be mounted to said power supply unit using at least two different mounting orientations and can change the current path depending on the orientation with which it is mounted.
2. An electric apparatus according to claim 1, wherein the power consumed by said circuit board can be changed depending on the direction in which it is mounted to said power supply unit.
3. An electric apparatus according to claim 1, wherein the power consumed by said circuit board can be maintained at a constant level by changing the orientation in which said circuit board is mounted to said power supply unit based on the voltage impressed by said power supply unit to said circuit board.
4. An electric apparatus according to claim 1, wherein said circuit board includes a plurality of connection points at which said circuit board is connected to said power supply unit, and two circuit elements that are installed between the connection points, such that the connection between the two circuit elements may be switched between series connection and parallel connection by changing the orientation in which said circuit board is mounted to said power supply unit.
5. An electric apparatus according to claim 4, wherein said circuit elements include a heating resistor.
6. An electric apparatus according to claim 4, wherein said circuit elements include an electromagnetic induction coil
7. An electric apparatus according to claim 1, wherein said circuit board is mountable to said power supply unit in two different orientations whereby one such orientation has a 180 rotational relationship to the other orientation, such orientation being obtained by rotating the circuit board relative to an axis perpendicular to the surface thereof.
8. An electric apparatus according to claim 1, wherein said circuit board is mountable to said power supply unit in two different orientations whereby one such orientation has a 180 rotational relationship to the other orientation, such orientation being obtained by rotating the circuit board relative to an axis parallel to the surface thereof.
9. A heating device comprising:
a power supply unit that has terminals for supplying power to a circuit board; and
a circuit board that has a heater and that can be mounted to the power supply unit in at least two different orientations such that the current path to the heater can be changed depending on the mounting orientation.
10. A heating device according to claim 9, wherein the output of the heater can be changed depending on the direction in which it is mounted to said power supply unit.
11. A heating device according to claim 9, wherein the output of the heater can be maintained at a constant level by changing the orientation in which said circuit board is mounted to said power supply unit based on the voltage impressed by said power supply unit to said circuit board.
12. A heating device according to claim 9, wherein said heater includes two heating elements, such that the connection between the two heating elements may be switched between series connection and parallel connection by changing the orientation in which said circuit board is mounted to said power supply unit.
13. An image forming apparatus comprising:
an image forming system that forms toner images on recording sheets; and
a fixing device that heats and fuses each toner image formed on a sheet by the image forming system,
wherein the fixing device includes a power supply unit that has terminals for supplying power to a circuit board, and a circuit board that has a heater and that can be mounted to the power supply unit in at least two different orientations such that the current path to the heater can be changed depending on the mounting orientation.
14. An image forming apparatus according to claim 13, wherein the output of the heater can be changed depending on the direction in which it is mounted to said power supply unit.
15. An image forming apparatus according to claim 13, wherein the output of the heater can be maintained at a constant level by changing the orientation in which said circuit board is mounted to said power supply unit based on the voltage impressed by said power supply unit to said circuit board.
16. An image forming apparatus according to claim 13, wherein said heater includes two heating elements, such that the connection between the two heating elements may be switched between series connection and parallel connection by changing the orientation in which said circuit board is mounted to said power supply unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming a contact on a semiconductor device, comprising;
providing a substrate;
providing a plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction over the substrate, wherein the gate structures located underneath the word lines and isolated by the diffusion regions;
forming an etching stop layer, wherein the etching stop layer and the first dielectric layer have different etching selectivity;
forming a second dielectric layer over the substrate; and
forming a plurality of contact holes to the diffusion regions between the word lines by using the etching stop layer as a self-aligned mask.
2. The method of claim 1, wherein the first dielectric layer has a height greater than the gate structures.
3. The method of claim 1, wherein the contact covers a portion of the etching stop layer.
4. The method of claim 1, wherein the material constituting the etching stop layer comprises silicon nitride or silicon oxynitride.
5. The method of claim 1, wherein the material constituting the first dielectric layer comprises silicon oxide.
6. The method of claim 1, wherein after the step of forming the gate structures, further comprises forming a mask strip layer over the gate structures.
7. The method of claim 6, wherein the step of forming the first dielectric layer comprises:
forming a dielectric material layer over the substrate;
removing a portion of the dielectric material layer above the mask strip layer until a portion of the mask strip layer is exposed and the dielectric material layer between the gate structures is retained; and
removing the mask strip layer.
8. The method of claim 7, wherein the step of forming the dielectric material layer comprises performing a high-density plasma chemical vapor deposition (HDPCVD) process.
9. The method of claim 7, wherein the step of removing a portion of the dielectric material layer comprises etching with hot phosphoric acid until the top corners of the mask strip layer are exposed.
10. The method of claim 1, wherein the step of forming the etching stop layer comprises:
forming an etching stop material layer over the substrate to cover the word lines and the dielectric strips and fill openings between the word lines; and
performing an anisotropic etching operation to remove a portion of the etching stop material layer.
11. The method of claim 1, wherein each of the gate structures comprises a bottom dielectric layer, a charge storage layer and a top dielectric layer.
12. The method of claim 11, wherein the bottom dielectric layer comprises a tunneling layer, the charge storage layer comprises a charge trapping layer, and the top dielectric layer comprises a charge barrier layer.
13. The method of claim 11, wherein the bottom dielectric layer comprises a tunneling layer, the charge storage layer comprises a floating gate layer, and the top dielectric layer comprises an inter-gate dielectric layer.