Author: claimsbot

1. A flash memory array, comprising:
a matrix of a plurality of flash cell units arranged in a plurality of rows and columns, each of said flash cell units having a drain node and every two adjacent flash cell units in a column having a common source node;
a plurality of word lines, each word line associated with a row of said flash cell units;
a plurality of bit lines laid out perpendicular to said word lines, each bit line associated with a column of said flash cell units and connected to the drains of the flash cell units in the associated column; and
a plurality of source lines laid out in parallel with said word lines, each source line associated with two adjacent rows of said flash cell units having common source nodes and connected to each common source node in the associated rows respectively through a diode;
wherein each flash cell unit is a two-transistor two-bit NAND-based NOR flash cell formed on a triple P-type well, and each row of said flash cell units is associated with two word lines.
2. The flash memory array according to claim 1, wherein each transistor of the flash cell unit comprises:
a gate made of a poly2 conduction layer;
an oxide-nitride-oxide layer underneath said gate;
a floating gate underneath said oxide-nitride-oxide layer; and
a tunneling oxide underneath said floating gate.
3. The flash memory array according to claim 1, wherein an erase operation for selected word lines of said flash memory array is based on a Fowler-Norheim tunneling scheme and accomplished by the following bias condition:
applying a first voltage to said triple P-type well;
applying a second voltage to each of said selected word lines, said first voltage having a voltage level approximately 20V greater than the voltage level of said second voltage;
keeping each bit line as floating; and
keeping each source line as floating.
4. The flash memory array according to claim 1, wherein a program operation in a selected word line of said flash memory array is based on a Fowler-Norheim tunneling scheme and accomplished by the following bias condition:
applying a program voltage to the selected word line, said program voltage being a step-wise pulse voltage in a range from 15V to 20V;
applying a pass voltage of approximately 10V to the other word line in the row associated with the selected word line;
applying a bit-program voltage of 0V to bit lines selected for programming;
applying a bit-inhibit voltage approximately in a range from 8V to 10V to bit lines selected but not to be programmed;
applying an inhibit voltage having a voltage level approximately one half of said bit-inhibit voltage to unselected word lines;
applying a voltage of 0V to the source line in the row associated with the selected word line; and
applying a voltage of 0V to said triple P-type well.
5. The flash memory array according to claim 1, wherein a read operation in a selected word line of said flash memory array is accomplished by the following bias condition:
applying a read voltage to the selected word line, said read voltage being approximately 1.5V to 2V greater than a highest threshold voltage of an erased flash cell unit of said flash memory array;
applying a pass voltage to the other word line in the row associated with the selected word line, said pass voltage being approximately 2greater than a highest threshold voltage of a programmed flash cell unit of said flash memory array;
applying a voltage of approximately 1.5V to the source line in the row associated with the selected word line;
applying a voltage of 0V to unselected word lines; and
applying a voltage of 0V to said triple P-type well.
6. The flash memory array according to claim 1, wherein each source line is made of a metal layer and directly in contact with each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+doped.
7. The flash memory array according to claim 1, wherein each source line is made of a first metal layer and connected through a respective ohmic contact to each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of a second metal layer and connected through a first via between said second metal layer and said first metal layer, said first metal layer, and a second via between said first metal layer and each drain node respectively to the drain node which is heavily N+ doped.
8. The flash memory array according to claim 1, wherein each source line is made of a metal layer and connected respectively through a pillar-structured polysilicon diode and a conduction layer to each common source node which is heavily N+ doped, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+doped.
9. The flash memory array according to claim 1, wherein each source line is made of a polysilicon layer and connected respectively through a pillar-structured polysilicon diode and a conduction layer to each common source node which is heavily N+ doped, and each bit line is made of a metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
10. The flash memory array according to claim 1, wherein each source line is made of a first metal layer and connected through a respective ohmic contact to each common source node which is heavily N+ doped with a PN+ junction diode enclosed therein, and each bit line is made of a second metal layer and connected through a first via between said second metal layer and said first metal layer, said first metal layer, and a second via between said first metal layer and each drain node respectively to the drain node which is heavily N+ doped.
11. The flash memory array according to claim 1, wherein each source line is made of a metal layer and directly in contact with each common source node which is heavily N+ doped with a PN+ junction diode enclosed therein, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
12. The flash memory array according to claim 1, wherein each source line is made of a metal layer and directly in contact with each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is lightly N\u2212doped with a heavily doped N+ junction region enclosed therein.
13. A flash memory array, comprising:
a matrix of a plurality of flash cell units arranged in a plurality of rows and columns, each of said flash cell units having a drain node and every two adjacent flash cell units in a column having a common source node;
a plurality of word lines, each word line associated with a row of said flash cell units;
a plurality of bit lines laid out perpendicular to said word lines, each bit line associated with a column of said flash cell units and connected to the drains of the flash cell units in the associated column; and
a plurality of source lines laid out in parallel with said word lines, each source line associated with two adjacent rows of said flash cell units having common source nodes and connected to each common source node in the associated rows respectively through a diode;
wherein each flash cell unit is an N transistor NAND-based NOR flash cell formed on a triple P-type well with N being greater than 2, and each row of said flash cell units is associated with N of said word lines.
14. The flash memory array according to claim 13, wherein each transistor of the flash cell unit comprises:
a gate made of a poly2 conduction layer;
an oxide-nitride-oxide layer underneath said gate;
a floating gate underneath said oxide-nitride-oxide layer; and
a tunneling oxide underneath said floating gate.
15. The flash memory array according to claim 13, wherein an erase operation for selected word lines of said flash memory array is based on a Fowler-Norheim tunneling scheme and accomplished by the following bias condition:
applying a first voltage to said triple P-type well;
applying a second voltage to each of said selected word lines, said first voltage having a voltage level approximately 20V greater than the voltage level of said second voltage;
keeping each bit line as floating; and
keeping each source line as floating.
16. The flash memory array according to claim 13, wherein a program operation in a selected word line of said flash memory array is based on a Fowler-Norheim tunneling scheme and accomplished by the following bias condition:
applying a program voltage to the selected word line, said program voltage being a step-wise pulse voltage in a range from 15V to 20V;
applying a pass voltage of approximately 10V to the other word lines in the row associated with the selected word line;
applying a bit-program voltage of 0V to bit lines selected for programming;
applying a bit-inhibit voltage approximately in a range from 8V to 10V to bit lines selected but not to be programmed;
applying an inhibit voltage having a voltage level approximately one half of said bit-inhibit voltage to unselected word lines;
applying a voltage of 0V to the source line in the row associated with the selected word line; and
applying a voltage of 0V to said triple P-type well.
17. The flash memory array according to claim 13, wherein a read operation in a selected word line of said flash memory array is accomplished by the following bias condition:
applying a read voltage to the selected word line, said read voltage being approximately 1.5V to 2V greater than a highest threshold voltage of an erased flash cell unit of said flash memory array;
applying a pass voltage to the other word lines in the row associated with the selected word line, said pass voltage being approximately 2V greater than a highest threshold voltage of a programmed flash cell unit of said flash memory array;
applying a voltage of approximately 1.5V to the source line in the row associated with the selected word line;
applying a voltage of 0V to unselected word lines; and
applying a voltage of 0V to said triple P-type well.
18. The flash memory array according to claim 13, wherein each source line is made of a metal layer and directly in contact with each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
19. The flash memory array according to claim 13, wherein each source line is made of a first metal layer and connected through a respective ohmic contact to each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of a second metal layer and connected through a first via between said second metal layer and said first metal layer, said first metal layer, and a second via between said first metal layer and each drain node respectively to the drain node which is heavily N+ doped.
20. The flash memory array according to claim 13, wherein each source line is made of a metal layer and connected respectively through a pillar-structured polysilicon diode and a conduction layer to each common source node which is heavily N+ doped, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
21. The flash memory array according to claim 13, wherein each source line is made of a polysilicon layer and connected respectively through a pillar-structured polysilicon diode and a conduction layer to each common source node which is heavily N+ doped, and each bit line is made of a metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
22. The flash memory array according to claim 13, wherein each source line is made of a first metal layer and connected through a respective ohmic contact to each common source node which is heavily N+ doped with a PN+ junction diode enclosed therein, and each bit line is made of a second metal layer and connected through a first via between said second metal layer and said first metal layer, said first metal layer, and a second via between said first metal layer and each drain node respectively to the drain node which is heavily N+ doped.
23. The flash memory array according to claim 13, wherein each source line is made of a metal layer and directly in contact with each common source node which is heavily N+ doped with a PN+ junction diode enclosed therein, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
24. The flash memory array according to claim 13, wherein each source line is made of a metal layer and directly in contact with each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is lightly N\u2212 doped with a heavily doped N+ junction region enclosed therein.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A wafer container including a container body for supporting a plurality of wafers therein with an opening formed on a sidewall of said container body for importing and exporting said plurality of wafers, a door with an outer surface and an inner surface, said door joining with said opening of said container body via said inner surface, the characteristic of said wafer container in that:
a magnetic member is disposed at inner edge of said opening of said container body and a magnet is disposed on said inner surface of said door corresponding to said magnetic member, said magnet being disposed in a magnetic yoke with recessed cross section; with said magnet of said door attracting said magnetic member at opening of said container body, said door and said container body being lock-fastened to each other.
2. The wafer container according to claim 1, wherein said magnetic member of said container body is selected from the group consisting of: metal material, ceramic material, and polymer material.
3. The wafer container according to claim 1, wherein a first lid is further disposed on said magnetic member of said container body.
4. The wafer container according to claim 1, wherein said magnetic yoke is made of metal material.
5. The wafer container according to claim 1, wherein said magnet of said door includes one outer surface that is not covered by said magnetic yoke, and said outer surface is covered by a pair of lids, a gap being included between said pair of lids for a seal element to be accommodated therein.
6. The wafer container according to claim 1, wherein a recess is disposed on said inner surface by being integrated with said door for separating said inner surface into two platforms, and a restraint module is respectively formed on each of said two platforms, each of said restraint module including a base and a plurality of notches arranged at interval being disposed on said base for contacting said plurality of wafers in said container body.
7. The wafer container according to claim 1, wherein a recess is disposed on said inner surface of said door for separating said inner surface into two platforms and a restraint module is fixedly connected on each of said two platforms respectively, said restraint module including a base and extension of one longer side of said base forming a plurality of suspended arms, a semicircle-like protruding portion being formed between each of said suspended arms and its free end, and a central guide notch being disposed on said protruding portion for contacting said plurality of wafers in said container body.
8. The wafer container according to claim 1, wherein a restriction module is disposed in central area of said inner surface of said door, said restriction module including a base, a plurality of restraint components arranged at interval extending from center of said base to two sides, each of said restraint components including a curve portion and a guide notch being formed at free end of said curve portion for contacting wafer.
9. A wafer container including a container body for supporting a plurality of wafers therein with an opening formed on a sidewall of said container body for importing and exporting said plurality of wafers, a door with an outer surface and an inner surface, said door joining with said opening of said container body via said inner surface, the characteristic of said wafer container in that:
a magnetic yoke with recessed cross section is disposed at inner edge of said opening of said container body, a magnet being disposed in said magnetic yoke and a magnetic member being disposed on said inner surface of said door corresponding to said magnet; with said magnet of said container body attracting said magnetic member of said door, said door and said container body being lock-fastened to each other.
10. The wafer container according to claim 9, wherein said magnetic member of said door is selected from the group consisting of: metal material, ceramic material, and polymer material.
11. The wafer container according to claim 9, wherein said magnetic member of said door corresponds to said magnet with an outer surface and said outer surface is covered by a lid.
12. The wafer container according to claim 9, wherein said magnetic yoke is made of metal material.
13. The wafer container according to claim 9, wherein said magnet of said container body includes one outer surface that is not covered by said magnetic yoke, and said outer surface is covered by a pair of lids, a gap being included between said pair of lids for a seal element to be accommodated therein.
14. The wafer container according to claim 9, wherein a recess is disposed on said inner surface by being integrated with said door for separating said inner surface into two platforms, and a restraint module is respectively formed on each of said two platforms, each of said restraint module including a base and a plurality of notches arranged at interval being disposed on said base for contacting said plurality of wafers in said container body.
15. The wafer container according to claim 9, wherein a recess is disposed on said inner surface of said door for separating said inner surface into two platforms and a restraint module is fixedly connected on each of said two platforms respectively, said restraint module including a base and extension of one longer side of said base forming a plurality of suspended arms, a semicircle-like protruding portion being formed between each of said suspended arms and its free end, and a central guide notch being disposed on said protruding portion for contacting said plurality of wafers in said container body.
16. The wafer container according to claim 9, wherein a restriction module is disposed in central area of said inner surface of said door, said restriction module including a base, a plurality of restraint components arranged at interval extending from center of said base to two sides, each of said restraint components including a curve portion and a guide notch being formed at free end of said curve portion for contacting wafer.
17. A wafer container including a container body for supporting a plurality of wafers therein with an opening formed on a sidewall of said container body for importing and exporting said plurality of wafers, a door with an outer surface and an inner surface, said door joining with said opening of said container body via said inner surface, the characteristic of said wafer container in that:
a magnetic member is disposed at inner edge of said opening of said container body and a magnet is disposed on said inner surface of said door corresponding to said magnetic member, said magnet being disposed in a magnetic yoke with recessed cross section and said door being mixed with metal particles; with design of which said magnet of said door attracting said magnetic member at opening of said container body for said door and said container body to be lock-fastened to each other.
18. The wafer container according to claim 17, wherein said magnetic member of said door is selected from the group consisting of: metal material, ceramic material, and polymer material.
19. The wafer container according to claim 17, wherein said magnetic member of said container body corresponds to said magnet with an outer surface and said outer surface is covered by a lid.
20. The wafer container according to claim 17, wherein said magnetic yoke is made of metal material.

1. A microporous crystalline material of zeolitic nature with a X-ray diffraction pattern concordant with that established in tables I and II for the material as synthesized and after calcination, respectively, and with a chemical composition in calcinated and anhydrous state which may be represented by the following empirical formula
x(M1nXO2):yYO2:SiO2
wherein x has a value lower than 0.1 whereby it may be equal to zero; y has a value lower than 0.1 and may as well be equal to zero; M is H or an inorganic cation of a charge n; X is a chemical element with oxidation state 3 (as for example Al, Ga, B, Cr) and Y is a chemical element with oxidation state 4 (as for example Ti, Ge, V).
2. A zeolite according to claim 1, the chemical composition of which, in calcinated and anhydrous state, may be represented by the empirical formula
x(HXO2):yYO2:SiO2
wherein X is a trivalent element (Al, B, Ga, Cr, . . . ), Y is a tetravalent element other than Si (Ti, Ge, V, . . . ), x has a value lower than 0.1 whereby it may be equal to zero; y has a value lower than 0.1 and may also be equal to zero.
3. A zeolite according to claim 1 the composition of which in calcinated and anhydrous state may be represented as SiO2.
4. A method for synthesizing zeolites, wherein a reaction mixture containing a source of SiO2, 1,4-diquinuclidinium butane, a source of fluorine F, a source of one or several tetravalent elements Y other than Si, a source of one or several trivalent elements X and water, is subjected to heating with or without agitation to a temperature between 80 and 200 C., preferably between 130 and 200 C. until achieving crystallization, and wherein the reaction mixture has a composition in terms of molar oxide ratios, comprised between the ranges
R(OH)2SiO20.01-1.0, preferably 0.1-1.0
HFSiO20.01-1.0, preferably 0.1-1.0
X2O3SiO20-0.05
YO2SiO20-0.1
H2OSiO20-100, preferably 1-50, more preferably 1-15.
5. A method for synthesizing the zeolite of the previous claims, wherein a reaction mixture containing a source of SiO2, 1,4-diquinuclidinium butane organic cation, a source of fluoride anions, a source of one or several trivalent elements X and water, is subjected to heating with or without agitation to a temperature between 80 and 200 C., preferably between 130 and 200 C. until achieving crystallization, and wherein the reaction mixture has a composition in terms of molar oxide ratios, comprised between the ranges
R(OH)2SiO20.01-1.0, preferably 0.1-1.0
FSiO20.01-1.0, preferably 0.1-1.0
X2O3SiO20-0.05
H2OSiO20-100, preferably 1-50, more preferably 1-15.
6. A method for synthesizing the zeolite of claims 1 and 2, wherein a reaction mixture containing a source of SiO2, 1,4-diquinuclidinium butane organic cation, a source of fluoride anions, a source of Al and water, is subjected to heating with or without agitation to a temperature between 80 and 200 C., preferably between 130 and 200 C. until achieving crystallization, and wherein the reaction mixture has a composition in terms of molar oxide ratios, comprised between the ranges
RF(OH)2SiO20.01-1.0, preferably 0.1-1.0
FSiO20-1.0, preferably 0.1-1.0
Al2O3SiO20-0.05
H2OSiO20-100, preferably 1-50, more preferably 1-15.
7. A method for synthesizing the zeolite of claims 1 and 3, wherein a reaction mixture containing a source of SiO2, 1,4-diquinuclidinium butane organic cation, a source of fluoride anions and water, is subjected to heating with our without agitation to a temperature between 80 and 200 C., preferably between 130 and 200 C. until achieving crystallization, and wherein the reaction mixture has a composition in terms of molar oxide ratios, comprised between the ranges
R(OH)2SiO20.01-1.0, preferably 0.1-1.0
FSiO20.01-1.0, preferably 0.1-1.0
H2OSiO20-100, preferably 1-50, more preferably 1-15.
8. A method for synthesizing zeolites of claims 1 and 2, wherein a reaction mixture containing a source of SiO2, 1,4-diquinuclidinium butane, a source of fluoride anion, a source of one or several tetravalent elements Y other than Si and water, is subjected to heating with or without agitation to a temperature between 80 and 200 C., preferably between 130 and 200 C. until achieving crystallization, and wherein the reaction mixture has a composition in terms of molar oxide ratios, comprised between the ranges
R(OH)2SiO20.01-1.0, preferably 0.1-1.0
HFSiO20.01-1.0, preferably 0.1-1.0
YO2SiO20-0.1
H2OSiO20-100, preferably 1-50, more preferably 1-15.
9. A method of synthesizing a microporous crystalline material according to claims 4-8, of synthesizing the zeolite of claims 1 and 3, wherein the 1,4-diquinuclidinium butane organic cation is added in hydroxide form or in the form of a mixture of hydroxide and another salt, preferably a halide and the fluoride anion is added in the form of hydrofluoric acid or of a salt, preferably ammonium fluoride, in such manner that the pH of the mixture is equal to or lower than 12, preferably lower than 11, and it may be even neutral or slightly acid.
10. A method of synthesizing a microporous crystalline material according to claim 9 and previous ones, wherein such crystalline material has a X-ray diffraction pattern substantially concordant with that established in tables I and II for the material as synthesized and after calcination, respectively, and with a chemical composition in calcinated and anhydrous state which may be represented by the following empirical formula
x(M1nXO2):yYO2:zR:wH2O
wherein x has a value lower than 0.1 whereby it may be equal to zero; y has a value lower than 0.1 and may as well be equal to zero; M is H or an inorganic cation of a charge n; X is a chemical element with oxidation state 3 (as for example Al, Ga, B, Cr) and Y is a chemical element with oxidation state 4 (as for example Ti, Ge, V).
11. A method for synthesizing the zeolite according to claims 1-3 and 10 in accordance with the process of claims 4-9 and 11, wherein an amount of crystalline material (preferably with the characteristics of the material of claims 1-4 and 11) is added to the reaction mixture as crystallization promoter, said amount being comprised in the range 0.01 to 15% by weight with respect to the whole of added silica, preferably 0.05 to 5%.
12. A method for synthesizing the zeolite according to claims 1-3 and 10 in accordance with the process of claims 4-9, wherein no alkaline cations are added to the reaction mixture.
13. A method for synthesizing the zeolite according to claims 1, 2 and 10 in accordance with the process of claims 4, 5, 6, 8, 9 and 11, wherein a source of a tetravalent element other than Si, or of a trivalent element, is added during an intermediate step during heating of the reaction mixture.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An oral composition comprising a polymer attached to a sweetening agent via a cleavable linker, wherein the polymer is capable of attaching to a surface in an oral cavity, and the cleavable linker is cleavable in the oral cavity to release the sweetening agent.
2. The oral composition according to claim 1, wherein the polymer is capable of attaching to the surface in the oral cavity selected from teeth, mucous membrane, gingival, cheek, tongue and lips.
3. The oral composition according to claim 1, wherein the polymer comprises a muco-adhesive polymer.
4. The oral composition according to claim 1, wherein the polymer is selected from a copolymer of maleic anhydride and methyl vinyl ether.
5. The oral composition according to claim 1, wherein the polymer is present in an amount of between 0.001% and 10%.
6. The oral composition according to claim 1, wherein the cleavable linker comprises a covalent bond.
7. The oral composition according to claim 6, wherein the linker comprises an ester bond or an amide bond.
8. The oral composition according to claim 1, wherein the cleavable linker is cleavable by hydrolysis.
9. The oral composition according to claim 1, wherein the cleavable linker is cleavable by an enzyme.
10. The oral composition according to claim 1, wherein the sweetening agent is selected from dextrose, polydextrose, sucrose, maltose, dextrin, dried invert sugar, mannose, xylose, ribose, fructose, levulose, galactose, corn syrup, partially hydrolyzed starch, hydrogenated starch hydrolysate, sorbitol, mannitol, xylitol, maltitol, isomalt, aspartame, neotame, saccharin and salts thereof, sucralose, dipeptide-based sweeteners, cyclamates, dihydrochalcones, and mixtures thereof.
11. The oral composition according to claim 1, wherein the sweetening agent is present in an amount from 0.005% to 5%.
12. The oral composition according to claim 1, wherein oral composition is adapted to release the sweetening agent from the polymer at a rate which provides enhancement of flavour sensation in the oral cavity for at least five minutes.
13. The oral composition according to claim 1, wherein the composition comprises an orally acceptable carrier for a toothpaste, a dental cream, a mouthwash, a chewing gum or a denture adhesive.
14. The oral composition according to claim 1, wherein the composition comprises one or more further agents selected from an anti-plaque agent, a whitening agent, antibacterial agent and a cleaning agent.
15. The oral composition according to claim 1, which further comprises a flavouring agent.
16. A portable dose article comprising the oral composition according to claim 1, wherein the portable dose article is selected from a lozenge, a mint, a bead, a wafer, a small portable nebulizer containing said composition in liquid formulated for oral application as a spray, a small portable bottle containing said composition in liquid formulated for oral application as a drop, and a soft pliable tablet.
17. A method for making the oral composition of claim 1, the method including attaching the polymer to the sweetening agent via the cleavable linker.
18. The method according to claim 17, wherein the polymer is attached to the sweetening agent by esterification.
19. A method for controlling the release of a sweetening agent in an oral cavity, comprising applying to the oral cavity the oral composition of claim 1.
20. Use of a polymer for enhancing andor sustaining the sensation of flavour in an oral cavity, wherein the polymer is attached to a sweetening agent via a cleavable linker, wherein the polymer is capable of attaching to a surface in the oral cavity and the cleavable linker is cleavable in the oral cavity to release the sweetening agent, so that the sensation of flavour is enhanced andor sustained.
21. Use according to claim 20, wherein the polymer is capable of attaching to the surface in the oral cavity selected from teeth, mucous membrane, gingival, cheek, tongue and lips.
22. Use according to claim 20, wherein the polymer is administered to the oral cavity in the oral composition comprising an orally acceptable carrier for a toothpaste, a dental cream, a mouthwash, a chewing gum or a denture adhesive.
23. A method for enhancing andor sustaining the sensation of flavour in an oral cavity, comprising applying to the oral cavity the oral composition of claim 1.
24. A method for controlling the release of a sweetening agent in an oral cavity, comprising applying to the oral cavity the oral composition the portable dose article of claim 16, wherein the cleavable linker is cleaved in the oral cavity to release the sweetening agent.
25. A method for enhancing andor sustaining the sensation of flavour in an oral cavity, comprising applying to the oral cavity the portable dose article of claim 16.