Author: claimsbot

1. A heat radiator having a thermo-electric cooler and multiple heat radiation modules, comprising:
a first heat radiation module having a first heat radiating fin set and a first heat conducting pipe connected to each fin of said first heat radiating fin set, said first heat conducting pipe having one end extended close to a heat source;
a thermo-electric cooler attached to said heat source for delivering heat from a contact surface with said heat source to an opposite upper surface; and
a second heat radiation module having a second heat radiating fin set and a second heat conducting pipe connected to each fin of said second heat radiating fin set, said second heat conducting pipe having one end extended close to said thermo-electric cooler.
2. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 1 wherein a first end of said first heat conducting pipe is embedded in a base that is in turn connected with said heat source.
3. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 1 wherein a second end of said first heat conducting pipe is extended to a place of good ventilation.
4. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 1 wherein a first end of said second heat conducting pipe is extended close to said upper surface of said thermo-electric cooler wherein heat is released.
5. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 1 wherein a second end of said second heat conducting pipe is extended to a place of good ventilation.
6. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 1 wherein said thermo-electric cooler is enclosed within a heat conducting component for absorbing heat from said thermo-electric cooler; said second heat conducting pipe delivering heat from said thermo-electric cooler to said second heat radiating fin set.
7. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 1 wherein a fan is installed on a lateral side of any of said first and second heat radiating fin sets.
8. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 1 wherein said first heat radiation module is provided with at least an extra heat conducting pipe with one end attached to one face of said thermo-electric cooler and another end going through said first heat radiating fin set for enhancing heat dissipation.
9. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 1 wherein said second heat radiation module is provided with at least an extra heat conducting pipe with one end attached to one face of said thermo-electric cooler and another end going through said second heat radiating fin set for enhancing heat dissipation.
10. A heat radiation method using said heat radiator of claim 1, comprising the steps of:
(1) said thermo-electric cooler attached to said heat source delivering heat from a contact surface with said heat source up to an opposite upper surface thereon;
(2) said first heat conducting pipe conducting heat from said thermo-electric cooler and said heat source to said first heat radiating fin set;
(3) said second heat conducting pipe conducting heat from said thermo-electric cooler to said second heat radiating fin set; and
(4) producing a cold airflow onward said first heat radiating fin set and second heat radiating fin set to achieve heat dissipation through heat exchange.
11. The heat radiation method of claim 10 wherein a space accommodating said heat radiation modules further includes a wind exit, enhancing air convection.
12. The heat radiation method of claim 10 further including the step of using at least a fan located aside a heat radiating fin set to facilitate a cold airflow passing through said fins.
13. The heat radiation method of claim 12 further including the step of using second fan to work with a first fan so as to produce an effect of airflow convection.
14. The heat radiation method of claim 10 wherein said heat source is an electronic circuit element.
15. The heat radiation method of claim 14 wherein said electronic circuit element is a central processing unit.
16. A heat radiator having a thermo-electric cooler and multiple heat radiation modules, comprising:
a first heat radiation module having a first heat radiating fin set and a heat sink connected to said first heat radiating fin set, said heat sink having one end extended close to a heat source;
a thermo-electric cooler attached to said heat source for delivering heat from a contact surface with said heat source to an opposite upper surface; and
a second heat radiation module having a second heat radiating fin set and a heat sink connected to said second heat radiating fin set, said heat sink having one end connected to said said upper surface of said thermo-electric cooler.
17. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 16 further including a fan installed on a lateral side of any of said first and second heat radiating fin sets.
18. The heat radiator having a thermo-electric cooler and multiple heat radiation modules of claim 16 wherein said first heat radiation module, said heat sink of said second heat radiation module and said heat radiating sets are directly connected.
19. A heat radiation method using said heat radiator of claim 16, comprising the steps of:
(1) said thermo-electric cooler attached to said heat source delivering heat from a contact surface with said heat source up to an opposite upper surface thereon;
(2) said first heat sink conducting heat from said thermo-electric cooler and said heat source to said first heat radiating fin set; and
(3) said second heat sink conducting heat from said thermo-electric cooler to said second heat radiating fin set.
20. The heat radiation method of claim 19 further including the step of driving a cold airflow onward said first heat radiating fin set and second heat radiating fin set to achieve heat dissipation through heat exchange.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system comprising:
an emitting device and a frequency splitter, wherein:
the frequency splitter includes:
at least one component with a Mach-Zehnder topology, and, in a case of plural components, the plural components are daisy chained, wherein
the at least one component with the Mach-Zehnder topology comprising:
an input port to receive an input signal;
an extracting port to output a band of the input signal corresponding to a nominal wavelength of the at least one component;
an output port to output the input signal except for the outputted band, the output port being connected to the input port of a next component if any or being unused for a last component of the daisy chain or an only component;
an add port which is unused; and
all unused ports of the at least one component with the Mach-Zehnder topology of the frequency splitter include a reflecting member;
the emitting device configured to use one operating level or a set of operating levels for transmitting signals to a receiving device via the frequency splitter, and
the emitting device is connected to the input port or the extracting port of one of the plural components with the Mach-Zehnder topology or the at least one component with the Mach-Zehnder topology, and the emitting device is configured to determine at least one operating level by measuring a signal reflected by the frequency splitter.
2. A method for coupling an emitting device to a frequency splitter, the emitting device using one operating level or a set of operating levels for transmitting signals to a receiving device via the frequency splitter, the frequency splitter comprising:
at least one component with a Mach-Zehnder topology, and, in a case of plural components, the plural components are daisy chained, wherein
the at least one component with the Mach-Zehnder topology comprising:
an input port to receive an input signal;
an extracting port to output a band of the input signal corresponding to a nominal wavelength of the at least one component;
an output port to output the input signal except for the outputted band, the output port being connected to the input port of a next component if any or being unused for a last component of the daisy chain or an only component;
an add port which is unused;
all unused ports of the at least one component with a the Mach-Zehnder topology of the frequency splitter include a reflecting member in order to reflect all incoming signals; and
the emitting device is connected to the input port or the extracting port of one of the plural components with the Mach-Zehnder topology or the at least one component with the Mach-Zehnder topology, the emitting device being further configured to determine at least one operating level by measuring a signal reflected by the frequency splitter.
3. The method according to claim 2, wherein:
the emitting device performs a first set of operations including:
initializing an operating level to a first wavelength;
sending a signature signal toward the receiving device using the operating level; and
measuring power of a signal received in response to the signature signal, to estimate a presence of a signal reflected by the frequency splitter, the first set of operations being repeated over a band of operating levels; and

the emitting device further performs:
determining the operating level, or the set of operating levels, for which the power of the received signal is minimum; and
setting the operating level, or the set of operating levels, to the determined operating level, or operating levels, for which the power of the received signal is minimum.
4. The method according to claim 3, wherein the measuring the power of the received signal is performed by modulation and filtering.
5. The method according to claim 3, wherein the measuring the power of the received signal is performed by synchronous detection.
6. The method according to claim 3, wherein the measuring the power of the received signal comprises:
defining a temporal sliding window;
measuring the power of the received signal over the temporal sliding window; and
moving the temporal sliding window in a range from an origin to a maximum corresponding to a round trip time of a total transmission path between the emitting device and the receiving device, the moving of the temporal sliding window being coupled with an automatic gain control in order to get the signal reflected by the frequency splitter.
7. The method according to claim 6, wherein a width of the temporal sliding window is chosen to be equal to a duration of the sent signature signal.
8. The method according to claim 6, wherein a power splitter is placed between the frequency splitter and the emitting device, and a gain corresponding to an attenuation due to the power splitter is applied for a position of the sliding window corresponding to a reflection point behind the power splitter relatively to a position of the emitting device on the total transmission path.
9. A method for tracking over time variation of at least one nominal wavelength of at least one respective component with a Mach-Zehnder topology in a frequency splitter, wherein a coupling method according to claim 2 is applied on a regular basis.

1. A memory device comprising:
a hardware interface to receive information for accessing a memory array including a cell-contiguous set of memory cells comprising first memory cells to operate as multi-level cells (MLCs) and second memory cells at least partially interleaved with the first memory cells, the second memory cells to operate as single-level cells (SLCs), wherein bits of the cell-contiguous set of memory cells belong to respective pages of a plurality of logical pages;
a sequencer coupled to the hardware interface, the sequencer including circuit logic to generate, based on the received information, signals to order accesses to the cell-contiguous set of memory cells according to a sequence of page rounds to avoid an occurrence of an access event in which a bit of a first MLC is accessed during a first page round and a bit of a second MLC is accessed during a second page round immediately succeeding the first page round in the sequence of page rounds, and wherein the first MLC and the second MLC are cell-adjacent to one another in a direction of a cell activation line.
2. The memory device of claim 1, the cell-contiguous set of memory cells having an average of one and a half bits per cell.
3. The memory device of claim 1, wherein the direction of the cell activation line is a direction of a word line of the memory array.
4. The memory device of claim 1, wherein the direction of the cell activation line is a direction of a bit line of the memory array.
5. The memory device of claim 1, wherein a distribution of the first memory cells and a distribution of the second memory cells form a checkered distribution pattern.
6. The memory device of claim 1, the memory array further including a first word line, wherein a first logical page includes first bits of the first memory cells which are to be accessed with the first word line, wherein a second logical page includes second bits of the first memory cells which are to be accessed with the first word line, wherein a third logical page includes exclusive bits of the second memory cells which are to be accessed with the first word line.
7. The memory device of claim 6, wherein the first logical page corresponds to first bits of MLCs, wherein the second logical page corresponds to second bits of MLCs, and wherein the third logical page corresponds to exclusive bits of SLCs.
8. The memory device of claim 1, the memory array including a plurality of word lines, each word line corresponding to a different respective set of logical pages.
9. The memory device of claim 8, wherein, for each of the plurality of word lines, each logical page of the set of logical pages corresponding to the word line corresponds to a different respective one of:
first bits of MLCs which are to be accessed with the word line;
second bits of MLCs which are to be accessed with the word line; and
exclusive bits of SLCs which are to be accessed with the word line.
10. A method comprising:
receiving information for accessing a memory array including a cell-contiguous set of memory cells comprising first memory cells to operate as multi-level cells (MLCs) and second memory cells at least partially interleaved with the first memory cells, the second memory cells to operate as single-level cells (SLCs), wherein bits of the cell-contiguous set of memory cells belong to respective pages of a plurality of logical pages; and
generating, based on the received information, signals to order accesses to the cell-contiguous set of memory cells according to a sequence of page rounds to avoid an occurrence of an access event in which a bit of a first MLC is accessed during a first page round and a bit of a second MLC is accessed during a second page round immediately succeeding the first page round in the sequence of page rounds, and wherein the first MLC and the second MLC are cell-adjacent to one another in a direction of a cell activation line.
11. The method of claim 10, the cell-contiguous set of memory cells having an average of one and a half bits per cell.
12. The method of claim 10, wherein the direction of the cell activation line is a direction of a word line of the memory array.
13. The method of claim 10, wherein the direction of the cell activation line is a direction of a bit line of the memory array.
14. The method of claim 10, wherein a distribution of the first memory cells and a distribution of the second memory cells form a checkered distribution pattern.
15. The method of claim 10, the memory array further including a first word line, wherein a first logical page includes first bits of the first memory cells which are to be accessed with the first word line, wherein a second logical page includes second bits of the first memory cells which are to be accessed with the first word line, wherein a third logical page includes exclusive bits of the second memory cells which are to be accessed with the first word line.
16. The method of claim 15, wherein the first logical page corresponds to first bits of MLCs, wherein the second logical page corresponds to second bits of MLCs, and wherein the third logical page corresponds to exclusive bits of SLCs.
17. The method of claim 10, the memory array including a plurality of word lines, each word line corresponding to a different respective set of logical pages.
18. The method of claim 17, wherein, for each of the plurality of word lines, each logical page of the set of logical pages corresponding to the word line corresponds to a different respective one of:
first bits of MLCs which are to be accessed with the word line;
second bits of MLCs which are to be accessed with the word line; and
exclusive bits of SLCs which are to be accessed with the word line.
19. A computer platform comprising:
a processor;
a memory device coupled to the processor, the memory device including:
a hardware interface to receive from the processor information for accessing a memory array of the computer platform, the memory array including a cell-contiguous set of memory cells comprising first memory cells to operate as multi-level cells (MLCs) and second memory cells at least partially interleaved with the first memory cells, the second memory cells to operate as single-level cells (SLCs), wherein bits of the cell-contiguous set of memory cells belong to respective pages of a plurality of logical pages; and
a sequencer coupled to the hardware interface, the sequencer including circuit logic to generate, based on the received information, signals to order accesses to the cell-contiguous set of memory cells according to a sequence of page rounds to avoid an occurrence of an access event in which a bit of a first MLC is accessed during a first page round and a bit of a second MLC is accessed during a second page round immediately succeeding the first page round in the sequence of page rounds, and wherein the first MLC and the second MLC are cell-adjacent to one another in a direction of a cell activation line; and

a network interface coupled to the processor and the memory device, the network interface to connect the computer platform to a network.
20. The computer platform of claim 19, the cell-contiguous set of memory cells having an average of one and a half bits per cell.
21. The computer platform of claim 19, wherein the direction of the cell activation line is a direction of a word line of the memory array.
22. The computer platform of claim 19, wherein the direction of the cell activation line is a direction of a bit line of the memory array.
23. The computer platform of claim 19, wherein a distribution of the first memory cells and a distribution of the second memory cells form a checkered distribution pattern.
24. The computer platform of claim 19, the memory array further including a first word line, wherein a first logical page includes first bits of the first memory cells which are to be accessed with the first word line, wherein a second logical page includes second bits of the first memory cells which are to be accessed with the first word line, wherein a third logical page includes exclusive bits of the second memory cells which are to be accessed with the first word line.
25. The computer platform of claim 24, wherein the first logical page corresponds to first bits of MLCs, wherein the second logical page corresponds to second bits of MLCs, and wherein the third logical page corresponds to exclusive bits of SLCs.
26. The computer platform of claim 19, the memory array including a plurality of word lines, each word line corresponding to a different respective set of logical pages.
27. The computer platform of claim 26, wherein, for each of the plurality of word lines, each logical page of the set of logical pages corresponding to the word line corresponds to a different respective one of:
first bits of MLCs which are to be accessed with the word line;
second bits of MLCs which are to be accessed with the word line; and
exclusive bits of SLCs which are to be accessed with the word line.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus comprising:
a multiplexer to store multiplexed audio data and video data in a memory device; and
a data scrambler to read the multiplexed data from the memory device, scramble the multiplexed data to generate scrambled data and store the scrambled data in the memory device, the scrambled data having a bit sequence that is different from the multiplexed data, in which the multiplexer and the data scrambler access the memory device using a common memory controller.
2. The apparatus of claim 1, further comprising an error correction code (ECC) encoder to generate error correction data based on the scrambled data, the error correction data allowing correction of one or more errors in the scrambled data.
3. The apparatus of claim 2, further comprising a channel code generator to generate channel codes based on the error correction data and the scrambled data, the channel codes being compatible with an optical storage standard.
4. The apparatus of claim 3 in which the optical storage standard comprises at least one of DVD+RW, DVD\u2212RW, DVD+R, DVD\u2212R, and high density DVD (HD\u2212DVD) standard.
5. The apparatus of claim 2 in which the error correction data are compatible with DVD standard.
6. The apparatus of claim 1 in which the scrambled data are compatible with DVD standard.
7. The apparatus of claim 1 in which the apparatus comprises an integrated circuit that comprises the multiplexer and the data scrambler.
8. The apparatus of claim 1, further comprising an audiovideo processor to process an audio signal and a video signal according to a compression process to generate the audio data and the video data.
9. The apparatus of claim 8 in which a portion of the compression process for processing the video data is compatible with a Moving Picture Experts Group (MPEG) standard.
10. The apparatus of claim 9 in which the MPEG standard comprises at least one of MPEG 2 and MPEG 4 standard.
11. The apparatus of claim 8 in which the apparatus comprises an integrated circuit that comprises the multiplexer, the data scrambler, and the audiovideo processor.
12. The apparatus of claim 1 in which the multiplexed data are not transferred to the data scrambler through an integrated device electronics (IDE) interface.
13. The apparatus of claim 1, further comprising an identification error detection (IED) encoder that generates an error detection code for an identification code associated with each sector of the multiplexed data.
14. The apparatus of claim 13, further comprising an error detection code (EDC) encoder that generates error detection data for each sector of the multiplexed data, the EDC allowing detection of one or more errors in a sector of the multiplexed data.
15. The apparatus of claim 14, further comprising an error correction code (ECC) encoder to generate error correction data for a predetermined number of sectors of the multiplexed data, the error correction data allowing correction of one or more errors in the predetermined number of sectors of the multiplexed data.
16. The apparatus of claim 15 in which the ECC encoder generates the error correction data based on the multiplexed data and their associated identification code and error detection data, the error correction data allowing correction of one or more errors in the multiplexed data and their associated identification data and error detection data.
17. The apparatus of claim 14 in which the data scrambler and the IED encoder scrambles the multiplexed data and generates the error detection code without storing information in the memory device.
18. A digital versatile disc (DVD) recorder comprising:
an audiovideo encoder to encode audio data according to an audio compression standard and encode video data according to an MPEG standard to generate encoded audio data and encoded video data, multiplex the encoded audio data and encoded video data to generate multiplexed data, and save the multiplexed data to a memory device;
a DVD encoder to read the multiplexed data from the memory device, scramble the multiplexed data to generate scrambled data, generate error detection code to allow detection of an error in the scrambled data, and save the scrambled data and the error detection code to the memory device,
the DVD encoder to also read the scrambled data and the error detection code from the memory device, generate error correction code based on the scrambled data and the error detection code, and save the error correction code, the error detection code, and the scrambled data in the memory device,
in which the audiovideo encoder and the DVD encoder access the memory device using a common memory controller.
19. The DVD recorder of claim 18 in which the DVD encoder also generates channel codes based on the error correction code, the error detection code, and the scrambled data according to DVD standard.
20. The DVD recorder of claim 18 in which the DVD recorder comprises an integrated circuit that comprises the audiovideo encoder and the DVD encoder.
21. The DVD recorder of claim 18 in which the DVD encoder comprises an identification error detection encoder that generates an error detection code for an identification code associated with each sector of the multiplexed data.
22. An apparatus comprising:
a memory having a first region and a second region;
a multiplexer to store multiplexed audio data and video data in the first region of the memory; and
an encoder to read the multiplexed data from the first region of the memory, to process the multiplexed data to generate code that includes error correction information and having a format that is compatible with a recording standard for recording the code to an optical storage medium, the encoder storing the code in the second region of the memory, the encoder reading the multiplexed data from the first region and storing the code in the second region of the memory without using an integrated drive electronics (IDE) interface.
23. The apparatus of claim 22 in which the encoder comprises a data scrambler to scramble the multiplexed data to generate scrambled data.
24. The apparatus of claim 23 in which the encoder comprises an error detection code (EDC) encoder to generate error detection data based on the scrambled data to allow detection of one or more errors in the scrambled data, the EDC encoder storing the error detection data and the scrambled data in a third region of the memory.
25. The apparatus of claim 24 in which the encoder comprises an error correction code encoder to read the scrambled data and the error detection data from the third region of the memory, and process the scrambled data and the error detection data to generate the code that includes error correction information.
26. The apparatus of claim 22 in which the optical storage medium is compatible with DVD standard.
27. An apparatus comprising:
first data processing means for storing multiplexed audio data and video data in a memory device; and
second data processing means for
reading the multiplexed data from the memory device,
scrambling the multiplexed data to generate scrambled data, and
storing the scrambled data in the memory device,

in which the first and second data processing means access the memory device using a common memory controller.
28. The apparatus of claim 27 in which the second data processing means access the memory device not more than twice for each sector of multiplexed data that is scrambled, the first access to the memory to read a sector of the multiplexed data from the memory, and the second access to the memory to write the scrambled data to the memory device.
29. The apparatus of claim 28, further comprising a third data processing means for generating error correction codes based on the scrambled data.
30. The apparatus of claim 29, further comprising a fourth data processing means for generating channel codes based on the error correction codes and the scrambled data, the channel codes being compatible with an optical storage standard.
31. The apparatus of claim 30 in which the optical storage standard comprises DVD standard.
32. A method comprising:
storing multiplexed audio data and video data in a memory device;
scrambling the multiplexed data to generate scrambled data, the scrambled data having a bit sequence that is different from the multiplexed data; and
storing the scrambled data in the memory device, in which storing the multiplexed data to the memory and storing the scrambled data to the memory are performed using a common memory controller.
33. The method of claim 32, further comprising generating error correction data based on the scrambled data, the error correction data allowing correction of one or more errors in the scrambled data.
34. The method of claim 33, further comprising generating channel codes based on the error correction data and the scrambled data, the channel codes being compatible with an optical storage standard.
35. The method of claim 34 in which the optical storage standard comprises at least one of DVD+RW, DVD\u2212RW, DVD+R, DVD\u2212R, and high density DVD (HD\u2212DVD) standard.
36. The method of claim 33 in which the error correction data are compatible with DVD standard.
37. The method of claim 32 in which the scrambled data are compatible with DVD standard.
38. The method of claim 32, further comprising processing an audio signal and a video signal according to compression processes to generate the audio data and the video data.
39. The method of claim 38 in which the compression process for processing the video signal is compatible with MPEG standard.
40. The method of claim 39 in which the MPEG standard comprises at least one of MPEG 2 and MPEG 4 standard.
41. The method of claim 32 in which scrambling the multiplexed data comprises reading the multiplexed data from the memory device, the reading performed without using an integrated device electronics (IDE) interface.
42. The method of claim 32, further comprising generating identification data for each sector of the multiplexed data.
43. The method of claim 42, further comprising generating error detection data for each sector of the multiplexed data, the error detection data allowing detection of one or more errors in the multiplexed data.
44. The method of claim 43, further comprising generating error correction data for a predetermined number of sectors of the multiplexed data and their associated identification data and error detection data, the error correction data allowing correction of one or more errors in the predetermined number of sectors of the multiplexed data and their associated identification data and error detection data.
45. The method of claim 42 in which generating the identification data and scrambling the multiplexed data are performed without storing information to the memory device.