Author: claimsbot

1. A printhead module having a plurality of rows of nozzles configured to extend, in use, across at least part of a printable pagewidth, each row including an offset row portion disposed at only one end of the printhead module, the nozzles in each row being logically grouped into at least first and second fire groups, the nozzles of each offset row portion being misaligned with respect to the other nozzles of that row, the printhead module being configured to sequentially fire, for each row, the nozzles of each fire group, such that each nozzle in the sequence from each fire group is fired simultaneously with respective corresponding nozzles in the sequence in the other fire groups, wherein:
the rows are disposed in pairs extending generally transverse to a direction media is to be moved relative to the printhead module, the rows in each pair of rows being configured to print the same color ink as each other;
the nozzles are fired row by row such that, for a first print line, the nozzles of one row of each pair of rows are fired, and for a sequential second print line, the nozzles of the other row of each pair of rows are fired; and
the offset row portions of at least some of the rows are different in length than the offset row portions of at least some of the other rows.
2. A printhead module according to claim 1, wherein the rows in each pair of rows share an ink supply.
3. A printhead module according to claim 1, wherein the rows in each pair of rows are offset with respect to each other.
4. A printhead module according to claim 1, configured to fire the nozzles such that at least some ink dots from one row land on top of dots previously deposited by one or more of the other rows.
5. A printhead module according to claim 1, operable in at least two fire modes, wherein at least some of the at least two fire modes define relatively different numbers of nozzles in each of the fire groups.
6. A printhead module according to claim 5, wherein at least some of the at least two fire groups define relatively different fire group sequences.
7. A printhead comprising a plurality of printhead modules according to claim 1.
8. A printhead according to claim 7, wherein the printhead is a pagewidth printhead.
9. A printhead module according to claim 1, in communication with a printer controller for receiving first data and manipulating the first data to produce dot data to be printed, the printer controller including at least two serial outputs for supplying the dot data to at least one printhead.
10. A printhead module according to claim 1 being capable of printing a maximum of n channels of print data, the printhead module being configurable into:
a first mode, in which the printhead module is configured to receive print data for a first number of the channels; and
a second mode, in which the printhead module is configured to receive print data for a second number of the channels, wherein the first number is greater than the second number.
11. A printhead module according to claim 1, for receiving dot data to be printed using at least two different inks and control data for controlling printing of the dot data, the printhead module including a communication input for receiving the dot data for the at least two colors and the control data.
12. A printhead module according to claim 1, including a plurality of pairs of the rows, each pair of rows including an odd row and an even row, the odd and even rows in each pair being offset from each other in both x and y directions relative to an intended direction of print media movement relative to the printhead, the printhead module being configured to cause firing of at least a plurality of the odd rows prior to firing any of the even rows, or vice versa.
13. A printhead module according to claim 12 wherein all the odd rows are fired before any of the even rows are fired, or vice versa.
14. A printhead module according to claim 12 wherein all the odd rows, or the even rows, or both, are fired in a predetermined order.
15. A printhead module according to claim 14 configurable such that the predetermined order is selectable from a plurality of predetermined available orders.
16. A printhead module according to claim 12 wherein the predetermined order is sequential.
17. A printhead module according to claim 16 configurable such that the predetermined order can commence at any of a plurality of the rows.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An electric cable comprising:
a support body having an axial length and a cross sectional length, said axial length being larger than said cross-sectional length, said support body having an exterior surface and defining a hollow interior;
a plurality of conductors arranged axially along said exterior surface of said support body, each of said plurality of conductors including a metal conducting portion circumferentially surrounded by an insulating layer;
another insulating layer circumferentially surrounding all of said plurality of conductors and said support body;
a connector post arranged at an axial end of said support body, all of said metal conducting portions of said plurality of conductors being electrically connected to said connector post.
2. A cable as claimed in claim 1, wherein said support body is a round hollow pipe, wherein said conductors are in an axial direction along an axial direction of the round hollow pipe so as to be arranged in order outside said round hollow pipe.
3. An electric cable in accordance with claim 1, wherein:
said metal conducting portions of said plurality of conductor extend beyond said axial end of said support body.
4. An electric cable in accordance with claim 1, wherein:
each of said plurality of conductors lie flat on said exterior surface and are not twisted about another one of said plurality of conductors.
5. An electric cable in accordance with claim 1, wherein:
said plurality of conductors lie directly adjacent said exterior surface of said support body for an entire said axial length of said support body.
6. An electric cable in accordance with claim 1, wherein:
each of said plurality of conductors are directly adjacent a same two of said plurality of conductors over said entire axial length of said support body.
7. An electric cable in accordance with claim 1, wherein:
said support body has a circular cross sectional shape.
8. An electric cable in accordance with claim 1, wherein:
said support body has an overall general polygonal cross sectional shape;
a first group of said plurality of conductors being arranged in a plane along a first side of said support body, a second group of said plurality of conductors being arranged in a plane along a second side of said support body.
9. An electric cable in accordance with claim 8, wherein:
said support body defines a plurality of sinking grooves to receive said plurality of conductors.
10. An electric cable in accordance with claim 1, wherein:
said hollow interior of said support body is a passage for removing heat generated in said metal conducting portions of said plurality of conductors.
11. An electric cable in accordance with claim 1, wherein:
said support body is flexible.
12. An electric cable in accordance with claim 1, further comprising:
insulating material completely filling a spaced between said support body and said plurality of conductors.
13. An electric cable comprising:
a support body having an axial length and a cross sectional length, said axial length being larger than said cross-sectional length, said support body having an exterior surface and defining a hollow interior;
a plurality of conductors arranged axially along said exterior surface of said support body, each of said plurality of conductors including a metal conducting portion circumferentially surrounded by an insulating layer, said plurality of conductors lying directly adjacent said exterior surface for an entire said axial length of said support body;
another insulating layer circumferentially surrounding all of said plurality of conductors and said support body.
14. An electric cable in accordance with claim 13, further comprising:
a connector post arranged at an axial end of said support body, all of said metal conducting portions of said plurality of conductors being electrically connected to said connector post.
15. An electric cable in accordance with claim 14, wherein:
said metal conducting portions of said plurality of conductor extend beyond said axial end of said support body.
16. An electric cable in accordance with claim 14, wherein:
each of said plurality of conductors lie flat on said exterior surface of said support body and are not twisted about another one of said plurality of conductors.
17. An electric cable in accordance with claim 14, wherein:
said metal conducting portions of said plurality of conductor extend beyond said axial end of said support body;
each of said plurality of conductors lie flat on said exterior surface of said support body and are not twisted about another one of said plurality of conductors;
each of said plurality of conductors are directly adjacent a same two of said plurality of conductors over said entire axial length of said support body
said hollow interior of said support body is a gas passage for removing heat generated in said metal conducting portions of said plurality of conductors
said support body is flexible;
insulating material completely fills a spaced between said support body and said plurality of conductors.
18. An electric cable in accordance with claim 13, wherein:
each of said plurality of conductors are directly adjacent a same two of said plurality of conductors over said entire axial length of said support body.
19. An electric cable in accordance with claim 13, wherein:
said hollow interior of said support body is a passage for removing heat generated in said metal conducting portions of said plurality of conductors.
20. An electric cable in accordance with claim 13, wherein:
said support body is flexible.

1. A memory device, comprising:
an array of memory cells, each memory cell comprising a memory element programmable between a first memory state and a second memory state;
a decoder electrically coupled to one or more word lines comprised in the array of memory cells, the decoder configured to decode an address input to select a word line of the one or more word lines comprised in the array of memory cells;
a binarizer electrically coupled to the array of memory cells and configured to receive a plurality of memory cell outputs from the array of memory cells and generate a plurality of binary weighted memory cell outputs in response to the decoder selecting a word line of the one or more word lines of the array of memory cells, wherein each binary weighted memory cell output corresponds with one memory cell;
a summer electrically coupled to the binarizer and configured to sum the binary weighted memory cell outputs into an analog signal; and
a quantizer electrically coupled to the summer and configured to convert the analog signal into a digital output.
2. The device of claim 1, wherein the binarizer comprises a voltage clamping transistor and at least one pair of load transistors and the pair of load transistors is configured to binarily weight and amplify, through a current mirror, a current corresponding with a memory cell.
3. The device of claim 1, wherein the digital output is a plurality of data bits corresponding with data stored on memory cells of a word line of the one or more word lines of the array of memory cells.
4. The device of claim 1, wherein a read data path of the memory device comprises a (4+m)n bit data path which comprises (4+m)n memory cells, (4+m)n clamp transistors, (4+m)n weighted current mirrors, a (4+m)n input summer and a (4+m)n bit quantizer, and wherein the memory device is configured to resolve (4+m)n bits of stored data simultaneously, wherein m is an integer and n is a positive integer.
5. The device of claim 1, further comprising a plurality of arrays of memory cells and a plurality of bit line select blocks, each array of memory cells forming a macro portion, each macro portion electrically coupled to one of the bit line select blocks and further coupled to a first decoder through word lines, where the first decoder is configured to decode one of a first and second address input to select a word line, and wherein each bit line select block is coupled to a second decoder configured to decode a third address input to select one of the bit line select blocks.
6. The device of claim 1, wherein a plurality of arrays of memory cells form a plurality of identical parallel (4+m) bit read data paths to generate (4+m)n output data bits, where m is an integer and n is a positive integer corresponding with the number of identical parallel (4+m) bit read data paths.
7. The device of claim 1, wherein the memory device comprises: four 4\xd74 arrays of memory cells; four bit line select blocks, each bit line select block electrically coupled to one 4\xd74 array of memory cells; two binarizers, each binarizer electrically coupled to two bit line select blocks; two summers, each summer electrically coupled to one binarizer; and two 4-bit current quantizers, each 4-bit current quantizer coupled to one summer.
8. The device of claim 1, wherein the memory elements each comprise an isolation transistor.
9. The device of claim 1, wherein the memory elements each include a magnetic tunnel junction.
10. A method of using a memory device, comprising:
decoding a word line address of an array of memory cells through a decoder and selecting the decoded word line, each memory cell comprising memory element programmable between a first memory state and a second memory state;
applying a control voltage to clamp transistors coupled to memory cells of the selected word line;
assigning binary weights to bit line currents to form binary weighted bit line currents;
summing the binary weighted bit line currents to generate an analog output current; and
quantizing the analog output current into a 4n bit digital code through a current quantizer, where n is a positive integer.
11. The method of claim 10, further comprising decoding at least one group of (4+m)n bit line addresses of the array of memory cells and selecting the decoded bit lines, and applying the control voltage to clamp transistors coupled to memory cells of the selected bit lines, wherein m is an integer and n is a positive integer.
12. The method of claim 10, wherein assigning weights to bit line currents comprises passing each bit line current through a pair of load transistors configured to binarily weight the bit line current through a current mirror.
13. The method of claim 10, further comprising amplifying the bit line currents.
14. The method of claim 10, further comprising providing a plurality of arrays of memory cells, each array of memory cells forming a macro portion, and providing a plurality of bit line select blocks and electrically coupling each macro portion to one of the bit line select blocks and further coupling each macro portion to a first decoder through word lines where the first decoder is configured to decode one of a first and second address input to select a word line, and further coupling each bit line select block to a second decoder configured to decode a third address input to enable selection of one of the bit line select blocks.
15. The method of claim 10, further comprising decoding an address associated with a bit line select block through a second decoder and selecting a bit line select block associated with that address.
16. A method of using a memory device, comprising:
decoding a word line address of an array of memory cells through a decoder and selecting the decoded word line, each memory cell comprising a memory element programmable between a first memory state and a second memory state;
applying a current to memory cells of the selected word line;
assigning binary weights to bit line voltages to form binary weighted bit line voltages;
summing the binary weighted bit line voltages to generate an analog output voltage; and
quantizing the analog output voltage into a (4+m)n bit digital code through a quantizer, wherein m is an integer and n is a positive integer.
17. The method of claim 16, further comprising decoding at least one group of (4+m)n bit line addresses of the array of memory cells, selecting the decoded bit lines, and applying the current to clamp transistors coupled to memory cells of the selected bit lines, wherein in is an integer and n is a positive integer.
18. The method of claim 16, wherein assigning binary weights to bit line voltages comprises assigning binary weights to bit line voltages with voltage multipliers.
19. The method of claim 16, further comprising:
providing a plurality of arrays of memory cells, each array of memory cells forming a macro portion;
providing a plurality of bit line select blocks;
electrically coupling each macro portion to one of the bit line select blocks and further coupling each macro portion to a first decoder through word lines, where the first decoder is configured to decode one of a first and a second address input to select a word line; and
coupling each bit line select block to a second decoder configured to decode a third address input to enable selection one of the bit line select blocks.
20. The method of claim 16, further comprising decoding an address associated with a bit line select block through a second decoder and selecting a bit line select block associated with that address.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A storage device comprising:
a nonvolatile semiconductor memory configured to store a plurality of first correcting codes to respectively correct errors in a plurality of first data blocks, a second correcting code to correct errors in a second data block which comprises the first data blocks, and the second data block, wherein
when data is read out from the nonvolatile semiconductor memory, a first error correction processing is performed first by using the first correcting code,
if the first error correction processing is unsuccessful, a second error correction processing is performed by using the second correcting code, and
if the first error correction processing is successful, the second error correction processing is not performed.
2. The device according to claim 1, further comprising:
a first corrector configured to correct errors in the first data blocks using the first correcting codes; and
a second corrector configured to correct errors in the second data block using the second correcting code.
3. The device according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory.
4. A storage device comprising:
a nonvolatile semiconductor memory configured to store data; and
an error correction circuit configured to correct an error when reading the data stored in the nonvolatile semiconductor memory,
wherein a correction capability of data is increased due to the increase in the number of errors of the data stored in the nonvolatile semiconductor memory.
5. The device according to claim 4, further comprising:
a first correcting code generator configured to generate a first correcting code to correct error in a first data block; and
a second correcting code generator configured to generate a second correcting code to correct error in a second data block, the second data block comprising first data blocks,
wherein the nonvolatile semiconductor memory is configured to store the second data block, first correcting codes, and the second correcting code.
6. The device according to claim 5, wherein
the error correction circuit includes:
a first corrector configured to correct errors in the first data blocks using the first correcting codes; and
a second corrector configured to correct errors in the second data block using the second correcting code.
7. The device according to claim 4, wherein the nonvolatile semiconductor memory is a NAND flash memory.