Author: claimsbot

1. A test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising:
a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and
a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test.
2. The test wafer unit according to claim 1, further comprising a plurality of connection pads that are formed on the semiconductor wafer and that correspond to the pads of the devices under test, wherein
the selecting section selects which type of test circuit is electrically connected to each connection pad.
3. The test wafer unit according to claim 2, wherein
the semiconductor wafer has a shape corresponding to the wafer under test, and
in the semiconductor wafer, each circuit block corresponding respectively to a device under test includes a plurality of test circuits having the same configuration as the test circuits in other circuit blocks.
4. The test wafer unit according to claim 3, wherein
in each circuit block, connection pads having the same arrangement as the connection pads in other circuit blocks are further formed.
5. The test wafer unit according to claim 4, wherein
each circuit block has a greater number of the test circuits than of the connection pads.
6. The test wafer unit according to claim 1, further comprising:
a circuit wafer on which the plurality of test circuits are formed; and
a connection wafer that is provided between the circuit wafer and the wafer under test and that has a selecting section formed thereon.
7. The test wafer unit according to claim 6, wherein the connection wafer includes:
a plurality of connection pads that are provided on a surface of the connection wafer facing the wafer under test and that correspond to pads of the devices under test; and
a plurality of intermediate pads that are provided on the surface of the connection wafer facing the circuit wafer, that are formed at different intervals than the connection pads, and that are electrically connected to the circuit wafer.
8. The test wafer unit according to claim 7, wherein
the intermediate pads are provided to correspond to the test circuits formed on the circuit wafer, and
the selecting section selects which of the intermediate pads is electrically connected to each connection pad.
9. A test system that tests a plurality of devices under test formed on a wafer under test, the test system comprising:
a test wafer unit that is electrically connected to the wafer under test; and
a control apparatus that controls the test wafer unit, wherein the test wafer unit includes:
a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and
a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A hospital monitoring system comprising:
a database comprising an electronic medical record repository of data wherein the electronic medical record repository of data contains the data of a plurality of patients in at least one hospital; and
a processor programmed with instructions for:
searching the database for at least one complex cascade pattern within the data of the plurality of patients and to identify one or more patients generating the at least one complex cascade pattern.
2. The hospital monitoring system of claim 1, comprising an alarm processor programmed with instructions to provide an automatic alarm upon the detection of the complex cascade pattern.
3. The hospital monitoring system of claim 1, wherein the complex cascade pattern comprises a cascade of at least one of sepsis, severe sepsis, septic shock, microcirculatory failure, and shock.
4. The hospital monitoring system of claim 1, wherein the complex cascade pattern comprises at least a plurality of linked perturbations andor trends of physiologic and laboratory data creating a progressively enlarging aggregation of progressively greater numbers of perturbed physiologic and laboratory data.
5. The hospital monitoring system of claim 1, further programmed to determine at least one characteristic of the complex cascade pattern, the characteristic comprising at least one of a severity of the complex cascade pattern, a duration of the complex cascade pattern, a time of onset of the complex cascade pattern, a maturity of the complex cascade pattern, a timing relationship of the complex cascade pattern to other events or another complex cascade pattern, a cost associated with the complex cascade pattern, a global pattern of the complex cascade pattern, a time of termination of the complex cascade pattern, components of the complex cascade pattern, a state of evolution of the complex cascade pattern, a length of stay subsequent to, or in association with the complex cascade pattern, or treatments associated with the complex cascade pattern.
6. The hospital monitoring system of claim 5, wherein the at least one characteristic of the complex cascade pattern is defined by at least one of a number of perturbations andor trends which comprise the complex cascade pattern, a severity of the perturbations andor trends, a number of systems affected by the complex cascade pattern, a presence, number andor severity of failure of compensation in response to perturbations associated with the complex cascade pattern.
7. The hospital monitoring system of claim 1, wherein the processor comprises instructions for determining a rate of growth of the complex cascade pattern.
8. The hospital monitoring system of claim 1, wherein the processor comprises instructions for determining the rate of growth of the complex cascade pattern by at least one of the increase in number andor severity of new perturbations being added per unit time, the increase number of systems affected, and the increase number of perturbations present in different systems.
9. The hospital monitoring system of claim 1, wherein the processor comprises instructions for detecting events or components that are temporally andor spatially associated with the complex cascade pattern but that are not part of the complex cascade pattern.
10. The hospital monitoring system of claim 1, wherein the processor comprises instructions for converting the electronic medical records into a format favorable for searching for the complex cascade pattern.
11. The hospital monitoring system of claim 10, wherein the format comprises sequential and timed variations comprised of at least positive variations and negative variations of the data.
12. The hospital monitoring system of claim 10, wherein the electronic medical record repository of data comprises data from a plurality hospitals, and wherein the processor is programmed comprises instructions for identifying the patients that are generating complex cascade patterns and the hospital in which they are located.
13. A patient data processing system comprising a processor programmed to:
convert the electronic medical records of at least one hospital into sequential and timed trends comprised of at least positive trends and negative trends of both the physiologic parameters and the laboratory data,
detect relational trends comprised of a combination of positive andor negative trends,
detect complex cascade patterns comprised of a plurality of combinations of relational trends,
automatically output a display of the image of the detected complex cascade,
automatically output a warning indicating the detection of the complex cascade and the identification of the patient generating the complex cascade,
track the growth or decline of the complex cascade and output an indication indicative of growth or decline.
14. The patient data processing system of claim 13, wherein the complex cascade pattern is indicative of physiologic failure.
15. The patient data processing system of claim 13, wherein the physiologic failure is at least one of sepsis, severe sepsis, septic shock, and microcirculatory failure, a shock cascade, and a septic shock cascade.
16. The patient data processing system of claim 13, wherein the processor comprises instructions for to determining and outputting an indication of the type of the cascade detected.
17. The patient data processing system of claim 13, wherein the processor comprises instructions for to determining and outputting at least an indication of the timing and type of the trends along the cascade.
18. The patient data processing system of claim 13, wherein the processor comprises instructions for to determining and outputting at least an indication of the length of the cascade.
19. The patient data processing system of claim 13, wherein the processor comprises instructions for to detecting the onset of therapy determining and outputting at least an indication of timing of therapy in relation to the cascade.
20. A patient data processing system for processing electronic medical records of a hospital, comprising a processor programmed to:
generate a time-series of data of at least a portion of a plurality of patients in the hospital, including at least data relating to the physiologic state andor care of each patient;
convert the datasets, including at least the monitored datasets and laboratory datasets into parallel and overlapping time series;
identify occurrences comprising inflammatory occurrences, metabolic occurrences, volumetric occurrences, hemodynamic occurrences, therapy occurrences, hematologic occurrences, or respiratory occurrences;
identify the timing of the occurrences;
identify at least one relational pattern of occurrences along a plurality of time series that is indicative of failure cascade of at least one of a sepsis cascade, a pulmonary embolism cascade, a metabolic cascade, or a microcirculatory failure cascade; and
output an alarm when the failure cascade is detected.

What is claimed is:

1. A light emitting diode (LED) with nanoparticles, which comprises:
a first electrode for electric conduction;
a substrate for said LED to be grown thereon;
a luminescent nanoparticles layer for emitting light; and
a second electrode for electric conduction;
wherein current flowing through said luminescent nanoparticles layer by said first electrode and said second electrode for emitting light.
2. The LED of claim 1, wherein said luminescent nanoparticles layer substantially is an oxide luminescent nanoparticles layer.
3. The LED of claim 1, wherein said luminescent nanoparticles layer substantially is a semiconductor luminescent nanoparticles layer.
4. The LED of claim 1, wherein said luminescent nanoparticles layer substantially is a macromolecule luminescent nanoparticles layer.
5. The LED of claim 3, wherein said luminescent nanoparticles layer substantially is a CdS nanoparticles layer.
6. The LED of claim 1, each luminescent nanoparticle of said luminescent nanoparticles layer substantially has a specific diameter between 5 nm to 500 nm.
7. The LED of claim 1, each luminescent nanoparticle of said luminescent nanoparticles layer substantially is spreading uniformly for having high performance of emitting light.
8. The LED of claim 1, wherein said substrate substantially is a semiconductor substrate.
9. The LED of claim 1, wherein said substrate substantially is an insulator substrate.
10. The LED of claim 8, wherein said substrate substantially is a silicon substrate.
11. The LED of claim 1, wherein said first electrode is comprised of a material selected from a group consisting of Au, Ag, Al, and Mg.
12. The LED of claim 1, wherein said second electrode is comprised of a material selected from a group consisting of Au, Ag, Al, and Mg.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A switch apparatus, comprising:
a first connector arranged on a motherboard;
a platform controller hub (PCH) chip arranged on the motherboard and coupled to the first connector through a low pin count (LPC) bus, the PCH chip comprising a first trapping pin and a second trapping pin;
a first basic input output system (BIOS) chip arranged on the motherboard, and coupled to the PCH chip through a serial peripheral interface (SPI) bus;
a switch circuit arranged on the motherboard; and
a diagnostic card, comprising:
a second connector being detachably plugged into the first connector; and
a second BIOS chip coupled to the second connector, to output a high level control signal through the second connector;

wherein the switch circuit receives the high level control signal from the second BIOS chip through the first connector in response to the second connector being plugged into the first connector, the switch circuit outputs high level switch signals to the first and second trapping pins of the PCH chip, to select the second BIOS chip to bootstrap the motherboard; wherein the switch circuit does not receive the high level control signal in response to the second connector not being plugged into the first connector, the switch circuit outputs low level signals to the first and second trapping pins of the PCH chip, to select the first BIOS chip to bootstrap the motherboard.
2. The switch apparatus of claim 1, wherein first to eighth pins of the second connector are coupled to first to eighth pins of the second BIOS chip, respectively, ninth and eleventh pins of the second BIOS chip are grounded, a tenth pin of the second BIOS chip is coupled to a power terminal, the eighth pin of the second BIOS chip is coupled to the power terminal through a first resistor, to output the high level control signal.
3. The switch apparatus of claim 1, wherein first to seventh pins of the first connector are coupled to first to seventh pins of the PCH chip, respectively, eighth and eleventh pins of the first connector are grounded, a tenth pin of the first connector is coupled to a power terminal, a ninth pin of the first connector receives the high level control signal from the second BIOS chip in response to the second connector being plugged into the first connector, eighth to eleventh pins of the PCH chip are coupled to first to fourth pins of the first BIOS chip, respectively.
4. The switch apparatus of claim 3, wherein the switch circuit comprises a switch chip, a first pin of the switch chip is coupled to the first trapping pin of the PCH chip, a second pin of the switch chip is grounded, third and fourth pins of the switch chip are coupled to the ninth pin of the first connector, a fifth pin of the switch chip is grounded, a sixth pin of the switch chip is coupled to the second trapping pin of the PCH chip, the first and sixth pins of the switch chip are also coupled to the power terminal through first and second resistors, respectively; when the third pin of the switch chip receives a high level signal, the first pin of the switch chip is connected to the second pin of the switch chip to output the low level switch signal to the first trapping pin; when the fourth pin of the switch chip receives a high level signal, the sixth pin of the switch chip is connected to the fifth pin of the switch chip to output the low level switch signal to the second trapping pin of the PCH chip.
5. The switch apparatus of claim 4, wherein the second pin of the switch chip is grounded through a third resistor.
6. The switch apparatus of claim 5, wherein the third pin of the switch chip is grounded through a fourth resistor and a fifth resistor in that order, and a node between the fourth resistor and the fifth resistor is coupled to the ninth pin of the first connector.
7. The switch apparatus of claim 6, wherein the fifth pin of the switch chip is grounded through a sixth resistor.
8. The switch apparatus of claim 7, wherein the fourth pin of the switch chip is coupled to the ninth pin of the first connector through a seventh resistor.