Author: claimsbot

1. A micro-electro-mechanical system (MEMS) device comprising:
a first plate;
a second plate disposed over the first plate;
a first moveable plate disposed between the first plate and the second plate; and
a second moveable plate disposed between the first moveable plate and the second plate, wherein the MEMS device comprises a first inputoutput node coupled to the first plate, a second inputoutput node coupled to the second plate, a third inputoutput node coupled to the first moveable plate, and a fourth inputoutput node coupled to the second moveable plate, wherein the first inputoutput node is a different inputoutput node from the second inputoutput node, and wherein the third inputoutput node is a different inputoutput node from the fourth inputoutput node, wherein the first moveable plate is rigidly coupled to the second moveable plate, and wherein the first moveable plate is configured to be shielded from capacitive coupling with the second moveable plate.
2. The device of claim 1, further comprising:
a bottom cavity disposed under the first plate;
a first cavity disposed between the first plate and the first moveable plate; and
a second cavity disposed between the second plate and the second moveable plate.
3. The device of claim 1, wherein the first moveable plate is configured to be coupled to a different potential node than the second moveable plate.
4. The device of claim 1, wherein the first moveable plate is configured to be coupled to a voltage source through a first filter, and wherein the second moveable plate is configured to be coupled to the voltage source through a second filter.
5. The device of claim 4, wherein the first filter and the second filter comprise different RC filters.
6. The device of claim 1, wherein the first plate is a first fixed plate and wherein the second plate is a second fixed plate.
7. The device of claim 6, wherein the first fixed plate is configured to be coupled to a voltage source through a first filter, and wherein the second fixed plate is configured to be coupled to the voltage source through a second filter.
8. The device of claim 6, further comprising:
a third moveable plate and a fourth moveable plate; and
a third fixed plate and a fourth fixed plate, wherein the third moveable plate is capacitively coupled to the third fixed plate, wherein the fourth moveable plate is capacitively coupled to the fourth fixed plate.
9. The device of claim 8, the first moveable plate is configured to be coupled to a first voltage source through a first filter, wherein the second moveable plate is configured to be coupled to the first voltage source through a second filter, wherein the third moveable plate is configured to be coupled to a second voltage source through a third filter, and wherein the fourth moveable plate is configured to be coupled to the second voltage source through a fourth filter.
10. The device of claim 9, wherein the first filter and the second filter comprise different RC filters, and wherein the third filter and the fourth filter comprise different RC filters.
11. A sensor circuit comprising:
a micro-electro-mechanical system (MEMS) structure forming a four terminal capacitive sensor, the MEMS structure comprising a first plate of a first type, a second plate of the first type, a first plate of a second type, and a second plate of the second type;
a first filter circuit coupled between a voltage source and a first input bias node configured to be coupled to the first plate of a first type of the four terminal capacitive sensor; and
a second filter circuit coupled between the voltage source and a second input bias node configured to be coupled to the second plate of the first type of the capacitive sensor, wherein the second filter circuit is a different circuit from the first filter circuit, wherein the capacitive sensor comprises the first plate of the first type capacitively coupled to the first plate of the second type and the second plate of the first type capacitively coupled to the second plate of the second type, wherein the first plate of the first type is rigidly coupled to the second plate of the first type, and wherein the first plate of the first type is configured to be shielded from capacitive coupling with the second plate of the first type.
12. The circuit of claim 11, wherein the first filter circuit comprises a first resistor coupled between the voltage source and the first input bias node and a first capacitor coupled between a fixed potential and the first input bias node, and wherein the second filter circuit comprises a second resistor coupled between the voltage source and the second input bias node and a second capacitor coupled between the fixed potential and the second input bias node.
13. The circuit of claim 12, wherein the first resistor comprises a diode or a metal insulator semiconductor transistor, wherein the first capacitor comprises a metal insulator semiconductor capacitor.
14. The circuit of claim 11, wherein the capacitive sensor comprises a MEMS microphone.
15. The circuit of claim 11, wherein the first plate of the first type is a first moveable plate, wherein the second plate of the first type is a second moveable plate, wherein the first plate of the second type is a first fixed plate, and wherein the second plate of the second type is a second fixed plate.
16. The circuit of claim 15, further comprising:
a first amplifier comprising an input node coupled to a first output bias node configured to be coupled to the first fixed plate of the capacitive sensor; and
a second amplifier comprising an input node coupled to a second output bias node configured to be coupled to the second fixed plate of the capacitive sensor.
17. The circuit of claim 16, further comprising:
a first feed-back capacitor coupled between the first input bias node and an output node of the first amplifier; and
a second feed-back capacitor coupled between the second input bias node and an output node of the second amplifier.
18. The circuit of claim 16, further comprising:
a first feed-back capacitor coupled between the second input bias node and an output node of the first amplifier; and
a second feed-back capacitor coupled between the first input bias node and an output node of the second amplifier.
19. The circuit of claim 11, wherein the first plate of the first type is a first fixed plate, wherein the second plate of the first type is a second fixed plate, wherein the first plate of the second type is a first moveable plate, wherein the second plate of the second type is a second moveable plate.
20. The circuit of claim 19, further comprising:
a first amplifier comprising an input node coupled to a first output bias node configured to be coupled to the first moveable plate of the capacitive sensor; and
a second amplifier comprising an input node coupled to a second output bias node configured to be coupled to the second moveable plate of the capacitive sensor.
21. The circuit of claim 20, further comprising:
a first feed-back capacitor coupled between the input node of the first amplifier and an output node of the first amplifier; and
a second feed-back capacitor coupled between the input node of the second amplifier and an output node of the second amplifier.
22. The circuit of claim 20, further comprising:
a first feed-back capacitor coupled between the input node of the second amplifier and an output node of the first amplifier; and
a second feed-back capacitor coupled between the input node of the first amplifier and an output node of the second amplifier.
23. A method of forming a micro-electro-mechanical system (MEMS) device, the method comprising:
forming a first plate in or over a substrate;
forming a second plate over the first plate;
forming a first moveable plate between the first plate and the second plate; and
forming a second moveable plate between the first moveable plate and the second plate, wherein the MEMS device comprises a first inputoutput node coupled to the first plate, a second inputoutput node coupled to the second plate, a third inputoutput node coupled to the first moveable plate, and a fourth inputoutput node coupled to the second moveable plate, wherein the first inputoutput node is a different inputoutput node from the second inputoutput node, and wherein the third inputoutput node is a different inputoutput node from the fourth inputoutput node, wherein the first moveable plate is rigidly coupled to the second moveable plate, and wherein the first moveable plate is configured to be shielded from capacitive coupling with the second moveable plate.
24. The method of claim 23, wherein the first moveable plate and the second moveable plate are formed as part of a same moveable mass, and wherein the first moveable plate is configured to be shielded from capacitive coupling with the second moveable plate.
25. The method of claim 23, further comprising:
forming a bottom cavity in the substrate under the first plate;
forming a first cavity between the first plate and the first moveable plate; and
forming a second cavity between the second plate and the second moveable plate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method, comprising:
selecting from an inverted index at least
a first item entry comprising a first listing of articles that are associated with a first item and
a second item entry comprising a second listing of articles that are associated with a second item, wherein the second item differs from the first item;

determining whether to compress the second item entry into the first item entry; and
compressing the second item entry into the first item entry based on the determination.
2. The method of claim 1, wherein determining whether to compress the second item entry into the first item entry comprises:
determining a cost-benefit ratio for compressing the second item entry into the first item entry; and
comparing the cost-benefit ratio with a value to determine if the cost-benefit ratio is acceptable.
3. The method of claim 1, wherein:
the first item entry further comprises an item value for each article in the first listing; and
the second item entry further comprises an item value for each article in the second listing.
4. The method of claim 3, wherein the item values comprise representations of strengths of the items in the articles.
5. The method of claim 3, wherein the item values comprise representations of whether the items appear in the articles.
6. The method of claim 2, wherein a cost in the cost-benefit ratio comprises a representation of:
a loss in precision caused by compressing the first item entry and the second item entry; or
additional processing time required when utilizing a compressed entry.
7. The method of claim 2, wherein determining the cost-benefit ratio comprises determining how much the first item entry and the second item entry change with the second item entry compressed into the first item entry.
8. The method of claim 2, wherein a benefit in the cost-benefit ratio comprises a representation of an amount of memory saved by compression of the first item entry and the second item entry.
9. The method of claim 1, wherein the items comprise one or more of words, concepts, or images.
10. The method of claim 2, wherein the value is predetermined.
11. A method, comprising:
selecting from an inverted index at least
a first item entry comprising a first listing of articles that are associated with a first item and an item value for each article in the first listing, and
a second item entry comprising a second listing of articles that are associated with a second item and an item value for each article in the second listing, wherein the second item differs from the first item;

determining a cost-benefit ratio for compressing the second item entry into the first item entry;
comparing the cost-benefit ratio with a value to determine if the cost-benefit ratio is acceptable; and
if the cost-benefit ratio is acceptable, compressing the second item entry into the first item entry.
12. The method of claim 11, wherein determining the cost-benefit ratio comprises determining how much the first item entry and the second item entry change with the second item entry compressed into the first item entry.
13. The method of claim 11, wherein a benefit in the cost-benefit ratio comprises a representation of an amount of memory saved by compression of the first item entry and the second item entry.
14. The method of claim 11, wherein the value is predetermined.
15. The method of claim 11, wherein the items comprise one or more of words, concepts, or images.
16. A method, comprising:
selecting from an inverted index a plurality of item entries, each item entry different from the other selected item entries and each item entry comprising a listing of associated articles;
determining whether to compress the plurality of item entries; and
compressing the item entries based on the determination.
17. The method of claim 16, wherein the plurality of item entries comprises three or more item entries.
18. An article comprising one or more computer-readable media containing program code operable to cause one or more machines to perform operations, the operations comprising:
program code for selecting from an inverted index at least
a first item entry comprising a first listing of articles that are associated with a first item, and
a second item entry comprising a second listing of articles that are associated with a second item, wherein the second item differs from the first item;

determining whether to compress the second item entry into the first item entry; and
compressing the second item entry into the first item entry based on the determination.
19. The article of claim 18, wherein determining whether to compress the second item entry into the first item entry comprises:
determining a cost-benefit ratio for compressing the second item entry into the first item entry; and
comparing the cost-benefit ratio with a value to determine if the cost-benefit ratio is acceptable.
20. The article of claim 18, wherein:
the first item entry further comprises an item value for each article in the first listing; and
the second item entry further comprises an item value for each article in the second listing.
21. The article of claim 20, wherein the item values comprise representations of strengths of the items in the articles.
22. The article of claim 20, herein the item values comprise representations of whether the items appear in the articles.
23. The article of claim 19, wherein a cost in the cost-benefit ratio comprises a representation of:
a loss in precision caused by compressing the first item entry and the second entry; or
additional processing be required when utilizing a compressed entry.
24. The article of claim 19, wherein determining the cost-benefit ratio comprises determining how much a first item entry and a second item entry change with the second item entry compressed into the first item entry.
25. The article of claim 19, wherein a benefit for the cost-benefit ratio comprises a representation of an amount of memory saved by compression of the first item entry and the second item entry.
26. The article of claim 18, wherein the items comprise one or more of words, concepts, or images.
27. The article of claim 19, wherein the value is predetermined.
28. An article comprising one or more computer-readable media containing program code operable to cause one or more machines to perform operations, the operations comprising:
selecting from an inverted index a plurality of item entries, each item entry different from the other selected item entries and each item entry comprising a listing of associated articles;
determining whether to compress the plurality of item entries; and
compressing the item entries based on the determination.
29. The article of claim 28, wherein the plurality of item entries comprises three or more item entries.
30. The method of claim 1, wherein:
the first item comprises a first word;
the articles in the first listing are associated with the first item by virtue of the first word appearing, in the articles in the first listing; and
the first word does not appear in the second item.
31. The method of claim 1, wherein:
the first item comprises a first concept;
the second item comprises a second concept;
the articles in the first listing are associated with the first item by virtue of the first concept appearing in the articles in the first listing;
the articles in the second listing are associated with the second item by virtue of the second concept appearing in the articles in the second listing; and
determining whether to compress the second item entry into the first item entry comprises determining whether the first concept is related to the second concept.
32. The method of claim 31, wherein determining whether the first concept is related to the second concept comprises accessing a semantic network that stores relationships between concepts.
33. The article of claim 18, wherein:
the first item comprises a first word;
the articles in the first listing are associated with the first item by virtue of the first word appearing in the articles in the first listing; and
the first word does not appear in the second item.
34. The article of claim 18, wherein:
the first item comprises a first concept;
the second item comprises a second concept;
the articles in the first listing are associated with the first item by virtue of the first concept appearing in the articles in the first listing;
the articles in the second listing are associated with the second item by virtue of the second concept appearing in the articles in the second listing; and
determining whether to compress the second item entry into the first item entry comprises determining whether the first concept is related to the second concept.
35. The article of claim 34, wherein determining whether the first concept is related to the second concept comprises accessing a semantic network that stores relationships between concepts.

1. A semiconductor device comprising:
a semiconductor substrate on which a predetermined layer is formed;
a first pattern extending in plan view in a first direction in the predetermined layer;
a second pattern extending in the plan view in parallel with the first pattern in the predetermined layer; and
a third pattern between the first and second patterns extending in the plan view in parallel with the first and second patterns in the predetermined layer,
wherein the first, second and third patterns have first, second and third enlarged end portions in the first direction, respectively,
wherein the first and third enlarged end portions are arranged in different positions staggered from each other in the plan view in the first direction,
wherein the first and the second enlarged end portions are substantially aligned along a second direction orthogonal to the first direction,
wherein an area established in the predetermined layer between the first, second and third enlarged end portions is free of other pattern, and
wherein the third enlarged portion is at least partially overlapped with the first and second enlarged portions in the second direction.
2. The semiconductor device as claimed in claim 1, wherein the first and second end portions are arranged in substantially the same position as each other in the first direction.
3. The semiconductor device as claimed in claim 1, wherein the first to third patterns have substantially the same width as each other.
4. The semiconductor device as claimed in claim 1, wherein the first, second and third patterns have first, second and third body portions connected to the first, second and third end portions, respectively, and the first, second and third end portions are greater in width than the first, second and third body portions, respectively.
5. The semiconductor device as claimed in claim 1, wherein a space between the first and third patterns is substantially equal to a space between the second and third patterns.
6. The semiconductor device as claimed in claim 1, wherein the first to third patterns comprise a conductive material.
7. The semiconductor device as claimed in claim 1, wherein a distance between the first and third end portions in the first direction is greater than a space between the first and third patterns.
8. The semiconductor device as claimed in claim 7, wherein a distance between the first and second end portions in the first direction is shorter than the space between the first and third patterns.
9. The semiconductor device as claimed in claim 1, further comprising a fourth pattern extending in a second direction different from the first direction.
10. The semiconductor device as claimed in claim 9, wherein the fourth pattern is formed on the predetermined layer.
11. The semiconductor device as claimed in claim 1, wherein a lower width of each of the first to third patterns is narrower than an upper width thereof.
12. The semiconductor device as claimed in claim 1, further comprising a fourth pattern extending in the first direction, wherein a width of the fourth pattern is greater than that of each of the first to third patterns.
13. The semiconductor device as claimed in claim 12, wherein the fourth pattern is formed on the predetermined layer.
14. The semiconductor device as claimed in claim 6, wherein the first to third patterns are insulated with each other by an insulating film.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A new additive for inhibiting high temperature naphthenic acid corrosion comprising polymeric thiophosphate ester having low phosphorous content, high thermal stability and low acidity, which is reaction product of reaction of hydroxyl terminated polyisobutylene or polybutene succinate ester with phosphorous pentasulphide.
2. A new additive, as claimed in claim 1, wherein said polymeric thiophosphate ester is further reacted with ethylene oxide to form ethylene oxide derivative of said polymeric thiophosphate ester.
3. A new additive, as claimed in claim 1, wherein said polymer compound has from 40 to 2000 carbon atoms.
4. A new additive, as claimed in claim 1, wherein said polymer compound has molecular weight of from 500 to 10000 dalton.
5. A new additive, as claimed in claim 1, wherein mole ratio of said phosphorous pentasulphide to said polymer compound which is hydroxyl-terminated is 0.01 to 4 moles to 1 mole respectively.
6. A new additive, as claimed in claim 1, wherein said polyisobutylene is normal or high reactive.
7. A new additive, as claimed in claim 1, wherein the effective dosage of said additive is from 1 ppm to 2000 ppm.
8. A method of making a new additive for inhibiting high temperature naphthenic acid corrosion, wherein said additive comprises polymeric hydroxyl terminated polyisobutylene thiophosphate ester having low phosphorous content, high thermal stability and low acidity, and is prepared by a process comprising the steps of:
(a) reacting high reactive polyisobutylene with maleic anhydride to form polyisobutylene succinic anhydride;
(b) reacting said polyisobutylene succinic anhydride of step (a) with a compound selected from glycols or polyols or polymeric alcohols to form hydroxyl-terminated polyisobutenyl succinate ester;
(c) reacting resultant reaction compound of step (b) with phosphorous pentasulphide, with various mole ratios of said hydroxyl-terminated polyisobutenyl succinic ester and phosphorous pentasulphide to form thiophosphate ester of polyisobutylene succinate ester, which is high temperature naphthenic acid corrosion inhibiting additive.
9. A method of using an additive for inhibiting high temperature naphthenic acid corrosion, comprising the step of:
a. heating the hydrocarbon containing naphthenic acid to vaporize a portion of said hydrocarbon;
b. allowing the hydrocarbon vapors to rise in a distillation column;
c. condensing a portion of said hydrocarbon vapors passing through the distillation column to produce a distillate
d. adding to the distillate from 1 to 2000 ppm of polyisobutylene thiophosphate ester as claimed in claim 1;
e. allowing the resultant mixture of step d to contact substantially the entire metal surfaces of said distillation column capably forming protective film on said surface whereby such surfaces are inhibited against corrosion.
10. An additive as claimed in claim 1, wherein said polymeric thiophosphate ester is further reacted with an oxide selected from group consisting of butylene oxide or propylene oxide or such other oxide to form oxide derivative of said polymeric thiophosphate ester.
11. An additive as claimed in claim 4, wherein said polymer compound has molecular weight of from 800 to 1600 dalton.
12. An additive as claimed in claim 11, wherein said polymer compound has molecular weight of from 950 to 1300 dalton.
13. An additive as claimed in claim 7, wherein the effective dosage of said additive is from 2 ppm to 200 ppm.
14. A method of making a new additive for inhibiting high temperature naphthenic acid corrosion, wherein said additive comprises polymeric ethylene oxide treated derivative of polyisobutylene thiophosphate ester having low phosphorous content, high thermal stability and low acidity, and is produced by a process comprising the steps of:
(a) reacting high reactive polyisobutylene with maleic anhydride to form polyisobutylene succinic anhydride;
(b) reacting said polyisobutylene succinic anhydride of step (a) with a compound selected from glycols or polyols or polymeric alcohols to form hydroxyl-terminated polyisobutenyl succinate ester;
(c) reacting resultant reaction compound of step (b) with phosphorous pentasulphide, with various mole ratios of said hydroxyl-terminated polyisobutenyl succinic ester and phosphorous pentasulphide to form thiophosphate ester of polyisobutylene succinate ester;
(d) reacting resultant reaction compound of step (c) with ethylene oxide to form ethylene oxide treated derivative of polyisobutylene thiophosphate ester, which is high temperature naphthenic acid corrosion inhibiting additive.
15. A method as claimed in claim 8, wherein said polyisobutylene succinic anhydride of step (a) is reacted with a compound selected from group comprising propylene glycol, butane diol, butylene glycol, butene diol, glycerin, trimethylol propane, polyethylene glycol, polypropylene glycol and polytetramethylene glycol.
16. A method as claimed in claim 8, wherein said polyisobutylene succinic anhydride of step (a) is reacted with ethylene glycol.
17. A method as claimed in claim 8, wherein said resultant reaction compound of step (c) is reacted with an oxide selected from group consisting of butylene oxide or propylene oxide or such other oxide to form oxide derivative of said polymeric thiophosphate ester.
18. A method as claimed in claim 14, wherein said polyisobutylene succinic anhydride of step (a) is reacted with a compound selected from group comprising propylene glycol, butane diol, butylene glycol, butene diol, glycerin, trimethylol propane, polyethylene glycol, polypropylene glycol and polytetramethylene glycol.
19. A method as claimed in claim 14, wherein said polyisobutylene succinic anhydride of step (a) is reacted with ethylene glycol.
20. A method as claimed in claim 14, wherein said resultant reaction compound of step (c) is reacted with an oxide selected from group consisting of butylene oxide or propylene oxide or such other oxide to form oxide derivative of said polymeric thiophosphate ester.
21. A method of using a additive for inhibiting high temperature naphthenic acid corrosion, comprising the step of:
a. heating the hydrocarbon containing naphthenic acid to vaporize a portion of said hydrocarbon;
b. allowing the hydrocarbon vapors to rise in a distillation column;
c. condensing a portion of said hydrocarbon vapors passing through the distillation column to produce a distillate
d. adding to the distillate from 1 to 2000 ppm of ethylene oxide treated compound of said polymeric thiophosphate ester as claimed in claim 2;
e. allowing the resultant mixture of step d to contact substantially the entire metal surfaces of said distillation column capably forming protective film on said surface whereby such surfaces are inhibited against corrosion.