Author: claimsbot

1. An apparatus, comprising:
a flexible line extending along a length, the flexible line including:
a first charge carrier-transporting body extending along at least a part of the length of the flexible line;
a photosensitive body over the first charge carrier-transporting body and extending along at least a part of the length of the flexible line, the photosensitive body capable of near-infrared light-induced or visible light-induced generation of charge carrier pairs; and
a second charge carrier-transporting body over the photosensitive body and extending along at least a part of the length of the flexible line, the second charge carrier-transporting body being at least semi-transparent to near-infrared light or visible light; and
wherein the photosensitive body includes a conductive polymer having dispersed quantum dots or rods, the quantum dots or rods being photosensitive to visible or near-infrared light.
2. The apparatus of claim 1, wherein the flexible line includes a flexible fiber extending along at least a part of the length of the flexible line, and the first charge carrier-transporting body is an inner charge carrier-transporting layer over the fiber and extending along at least a part of the length of the flexible line.
3. The apparatus of claim 2, wherein the photosensitive body is a photosensitive layer over the inner charge carrier-transporting layer and extending along at least a part of the length of the flexible line.
4. The apparatus of claim 3, wherein the second charge carrier-transporting body is an outer charge carrier-transporting layer over the photosensitive layer and extending along at least a part of the length of the flexible line.
5. The apparatus of claim 4, wherein the fiber has a circumference at a selected point along the length of the flexible line, and the inner charge carrier-transporting layer, the photosensitive layer, and the outer charge carrier-transporting layer each are over only a part of the circumference at the point.
6. The apparatus of claim 1, wherein the first charge carrier-transporting body and the second charge carrier-transporting body each include a p-doped semiconductor or an n-doped semiconductor.
7. The apparatus of claim 6, wherein the photosensitive body is an intrinsic body, and wherein the flexible line includes a junction selected from a group consisting of a p-i-n junction, an n-i-n junction, and a p-i-p junction, the junction including the first and second charge carrier-transporting bodies and the photosensitive body.
8. The apparatus of claim 1, wherein the photosensitive body has a composition including a photosensitive organic polymer capable of near-infrared light-induced or visible light-induced generation of charge carrier pairs.
9. The apparatus of claim 8, wherein the photosensitive organic polymer includes a moiety selected from a group consisting of a paraphenylene vinylene, a fluorene, and a thiophene.
10. The apparatus of claim 1, wherein the conductive polymer includes a member selected from a group consisting of poly(aniline), poly(acetylene), poly(pyrrole), and poly(3,4-ethylene dioxythiophene):poly(styrene sulfonate).
11. A fabric including the apparatus of claim 1.
12. A method, comprising:
providing a flexible line extending along a length, the flexible line including a first charge carrier-transporting body, a photosensitive body over the first charge carrier-transporting body, and a second charge carrier-transporting body over the photosensitive body, each of the first and second charge carrier-transporting bodies and the photosensitive body extending along at least a part of the length of the flexible line, the photosensitive body being capable of near-infrared light-induced or visible light-induced generation of charge carrier pairs, and the second charge carrier-transporting body being at least semi-transparent to near-infrared light or visible photosensitive body including a conductive polymer having dispersed quantum dots or rods, the quantum dots or rods being photosensitive to visible or near-infrared light;
providing an electrical circuit including the first and second charge carrier-transporting bodies and the photosensitive body, and a current detector; and
detecting current generated by exposure of the flexible line to near-infrared light or visible light.
13. The method of claim 12, wherein providing the flexible line includes providing a flexible fiber extending along at least a part of the length of the flexible line, and includes providing, as the first charge carrier-transporting body, an inner charge carrier-transporting layer over the fiber and extending along at least a part of the length of the flexible line.
14. The method of claim 13, wherein providing the flexible line includes providing, as the photosensitive body, a photosensitive layer over the inner charge carrier-transporting layer and extending along at least a part of the length of the flexible line.
15. The method of claim 14, wherein providing the flexible line includes providing, as the second charge carrier-transporting body, an outer charge carrier-transporting layer over the photosensitive layer and extending along at least a part of the length of the flexible line.
16. The method of claim 12, wherein providing the flexible line includes providing, as each of the first and second charge carrier-transporting bodies, a p-doped semiconductor or an n-doped semiconductor.
17. The method of claim 12, wherein providing the flexible line includes providing a junction selected from a group consisting of a p-i-n junction, an n-i-n junction, and a p-i-p junction, the junction including the first and second charge carrier-transporting bodies and the photosensitive body.
18. The method of claim 12, wherein the photosensitive body has a composition including a photosensitive organic polymer capable of near-infrared light-induced or visible light-induced generation of charge carrier pairs.
19. The method of claim 12, wherein the photosensitive organic polymer includes a moiety selected from a group consisting of a paraphenylene vinylene, a fluorene, and a thiophene.
20. The method of claim 12, wherein the conductive polymer includes a member selected from a group consisting of poly(aniline), poly(acetylene), poly(pyrrole), and poly(3,4-ethylene dioxythiophene):poly(styrene sulfonate).

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A computer-implemented method comprising:
receiving a request to perform an operation on a mapped object, wherein mapping data defines a mapping between said mapped object and a base object, said base object associated with content data;
wherein said mapped object and said base object reside in a volatile memory cache;
wherein the mapping data includes an indication of a first mapping type of a plurality of mapping types;
wherein the mapping is only retained as long as said mapped object resides in said cache;
responding to said request by examining the mapping data to determine that the mapping type of the first mapping is said first mapping type; and
to complete the requested operation, performing a first sequence of one or more actions based on determining that the mapping type of the first mapping is said first mapping type;
wherein the method is performed by one or more computing devices.
2. The method of claim 1, further comprising:
receiving a second request to perform said operation on a second mapped object that is mapped to said base object, wherein second mapping data includes a second mapping type, wherein the first mapping type and second mapping type are different; and
responding to said second request by performing a second sequence of one or more actions, wherein the second sequence of one or more actions is different from the first sequence of one or more actions
3. The method of claim 1, wherein the plurality of mapping types includes:
at least one of the following types for sharing content associated with the base object:
a) shared-readexclusive write; or
b) shared-write; and

at least one of the following relationship types:
c) ownership;
d) dependency;
e) semantic relation;
f) syntactic relation;

wherein a mapping type of shared-readexclusive write causes the content associated with the base object to be provided in response to a read operation of the mapped object, and in response to a write operation, a new copy of the content associated with the base object is created and the mapped object becomes a base object associated with content that is the new copy;
wherein a mapping type of shared write causes the content associated with the base object to be provided in response to a read operation of the mapped object, and in response to a write operation, the content associated with the base object is overwritten;
wherein an ownership mapping type expresses that the mapped object owns the base object;
wherein a dependency mapping type expresses that the mapped object depends on the base object;
wherein a syntactic relation indicates:
that the mapped object and base object represent expressions;
the content associated with the base object is the result of evaluating the expression represented by the base object;
and based on a set of rules, the expression represented by the mapped object can be re-written as the expression represented by the base object; and

wherein a semantic relation indicates:
that the mapped object and base object represent expressions;
the content associated with the base object is the result of evaluating the expression represented by the base object;
and the expression represented by the mapped object and the expression represented by the base object both evaluate to the same results.
4. The method of claim 3, wherein the relationship mapping type is ownership.
5. The method of claim 3, wherein the relationship mapping type is dependency.
6. The method of claim 3, wherein the relationship mapping type is syntactic relation.
7. The method of claim 3, wherein the relationship mapping type is semantic relation.
8. The method of claim 1, wherein said mapping type changes between the mapped object and the base object.
9. The method of claim 3, wherein:
the mapping type is semantic or syntactic;
base object represents a database query; and
the content associated with the base object is a database cursor.
10. The method of claim 3, wherein:
the mapping type is a sharing type of shared-readexclusive write;
the contents associated with the base object is a particular version of a file; and
updating the mapped object causes a new version of the file to be created without changing the contents of the particular version.

What is claimed is

1. A carrier for optical semiconductor device having a device mounting face on which at least one optical semiconductor device is to be mounted and at least one positioning face slanted by a predetermined angle with respect to the device mounting face and disposed below a position at which the optical semiconductor device is mounted.
2. The carrier in accordance with claim 1, wherein at least one electrode, which is to be connected to the optical semiconductor device, is serially formed on the device mounting face and the positioning face.
3. The carrier in accordance with claim 1, wherein at least one convex or concave portion which will be used for positioning the carrier on another substrate is formed on the positioning face.
4. The carrier in accordance with claim 1, wherein the device mounting face corresponds to 110 surface or 100 surface equivalent to (110) surface or (100) surface of a single crystalline silicon and the positioning face corresponds to 111 surface equivalent to (111) surface of the single crystalline silicon.
5. The carrier in accordance with claim 1, wherein two positioning faces are formed symmetrically in a section perpendicular to the device mounting face.
6. A mounting structure of an optical semiconductor device comprising a carrier on which at least one optical semiconductor device is mounted and a substrate on which the carrier with the optical semiconductor device and another optical device are mounted, wherein
the carrier has a device mounting face on which at least one optical semiconductor device is to be mounted and at least one first positioning face slanted by a first predetermined angle with respect to the device mounting face and disposed below a position at which the optical semiconductor device is mounted; and
the substrate has at least one second positioning face slanted by a second predetermined angle with respect to a top face of the substrate to which the positioning face of the carrier is contacted.
7. The mounting structure in accordance with claim 6, wherein at least one first electrode to which the optical semiconductor device is connected is serially formed on the device mounting face and the first positioning face of the carrier, and at least one second electrode to which the first electrode is contacted is serially formed on the top face and the second positioning face of the substrate.
8. The mounting structure in accordance with claim 6, wherein at least one first convex or concave portion is formed on the first positioning face of the carrier and at least one second concave or convex portion engaged with the first convex or concave portion is formed on the second positioning face of the substrate.
9. The mounting structure in accordance with claim 6, wherein the device mounting face of the carrier corresponds to 110 surface or 100 surface equivalent to (110) surface or (100) surface of a single crystalline silicon, the first positioning face of the carrier corresponds to 111 surface equivalent to (111) surface of the single crystalline silicon, the top face of the substrate corresponds to 110 surface or 100 surface of a single crystalline silicon, and the second positioning face of the substrate corresponds to 111 surface of the single crystalline silicon.
10. The mounting structure in accordance with claim 6, wherein the device mounting face of the carrier is perpendicular to the top face of the substrate.
11. The mounting structure in accordance with claim 6, wherein the substrate has a cavity having a trapezoidal section in which the carrier is mounted, two slanted faces of the cavity serve as the second positioning faces, and the first positioning faces of the carrier are formed symmetrically in a section perpendicular to the device mounting face.
12. An optical module comprising a carrier, a substrate respectively having the above-mentioned configurations, at least one optical semiconductor device mounted on the carrier and at least one optical fiber mounted on the substrate so as to be optically coupled with the optical semiconductor device, wherein
the carrier has a device mounting face on which the optical semiconductor device is to be mounted and at least one first positioning face slanted by a first predetermined angle with respect to the device mounting face and disposed below a position at which the optical semiconductor device is mounted; and
the substrate has at least one second positioning face slanted by a second predetermined angle with respect to a top face of the substrate to which the positioning face of the carrier is contacted and at least one positioning groove in which the optical fiber is mounted in a manner so that an end face of the optical fiber face a functional face of the optical semiconductor device.
13. The optical module in accordance with claim 12, wherein a light emitting device and a photo sensing device are mounted on the same carrier, and the end face of the optical fiber is slanted for reflecting a part of a light beam emitted from the light emitting device toward the photo sensing device.
14. The optical module in accordance with claim 12, wherein a light emitting device and a photo sensing device are mounted on the same carrier, and a reflection face is formed on the substrate for reflecting a part of a light beam emitted from the light emitting device toward the photo sensing device.
15. The optical module in accordance with claim 12, wherein at least one first electrode to which the optical semiconductor device is connected is serially formed on the device mounting face and the first positioning face of the carrier, and at least one second electrode to which the first electrode is contacted is serially formed on the top face and the second positioning face of the substrate.
16. The optical module in accordance with claim 12, wherein at least one first convex or concave portion is formed on the first positioning face of the carrier and at least one second concave or convex portion engaged with the first convex or concave portion is formed on the second positioning face of the substrate.
17. The optical module in accordance with claim 12, wherein the device mounting face of the carrier corresponds to 110 surface or 100 surface equivalent to (110) surface or (100) surface of a single crystalline silicon, the first positioning face of the carrier corresponds to 111 surface equivalent to (111) surface of the single crystalline silicon, the top face of the substrate corresponds to 110 surface or 100 surface of a single crystalline silicon, and the second positioning face of the substrate corresponds to 111 surface of the single crystalline silicon.
18. The optical module in accordance with claim 12, wherein the device mounting face of the carrier is perpendicular to the top face of the substrate.
19. The optical module in accordance with claim 12, wherein the substrate has a cavity having a trapezoidal section in which the carrier is mounted, two slanted faces of the cavity serve as the second positioning faces, and the first positioning faces of the carrier are formed symmetrically in a section perpendicular to the device mounting face.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for manufacturing a stacked semiconductor memory device comprising:
testing a plurality of memory chips to detect first defective addresses;
programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses;
stacking the plurality of memory chips;
testing the stacked memory chips to detect second defective addresses; and
programming electrical fuses with second defective address information.
2. The method as claimed in claim 1 wherein an interface chip is stacked with the plurality of memory chips.
3. The method as claimed in claim 2 wherein the electrical fuses are located on the interface chip.
4. The method as claimed in claim 1 wherein the testing to detect the first defective addresses is performed while the plurality of memory chips are on one or more wafers and the one or more wafers are diced to provide the plurality of memory chips in singulated form prior to stacking.
5. The method as claimed in claim 1 further comprising packaging the plurality of memory chips in resin after stacking.
6. The method as claimed in claim 1 further comprising subjecting the plurality of memory chips to a burn-in test after stacking.
7. The method as claimed in claim 1 wherein the first defective addresses are row addresses.
8. The method as claimed in claim 7 wherein the second defective addresses are row addresses.
9. The method as claimed in claim 7 wherein the second defective addresses are column addresses.
10. The method as claimed in claim 1 wherein the first defective addresses are column addresses.
11. The method as claimed in claim 10 wherein the second defective addresses are row addresses.
12. The method as claimed in claim 10 wherein the second defective addresses are column addresses.
13. The method as claimed in claim 1 wherein the second defective addresses are row addresses.
14. The method as claimed in claim 1 wherein the second defective addresses are column addresses.
15. The method as claimed in claim 1 wherein the plurality of memory chips are, at least at completion of the manufacturing of the stacked semiconductor memory device, connected by a plurality of through silicon vias.
16. The method as claimed in claim 1 wherein the plurality of memory chips are synchronous dynamic random access memories.
17. The method as claimed in claim 16 wherein the plurality of memory chips are double date rate synchronous dynamic random access memories.