Author: claimsbot

1. A method for determining an optical axis vector of an eye in a three-axis coordinate system comprising X, Y and Z axes, comprising:
determining an ellipse equation defining an iris disc corresponding to the eye, on an XY plane of the three-axis coordinate system;
deriving a set of equations based on the ellipse equation corresponding to a plurality of edge points of the iris disc in the three-axis coordinate system; and
iteratively calculating an estimated iris diameter until a difference between the estimated iris diameter and a predetermined iris diameter is less than a threshold, comprising:
estimating a ray length from a spatial origin of the three-axis coordinate system to a first edge point of the plurality of edge points;
solving the set of equations based on the estimated ray length to calculate a plurality of solutions;
calculating the estimated iris diameter based on the solutions; and
calculating an optical axis vector of the eye in the three-axis coordinate system based on the solutions,

wherein the solutions comprise a first solution and a second solution based on two sets of the edge points, respectively, and
wherein calculating the optical axis vector comprises:
calculating a first optical axis vector based on the first solution,
calculating a second optical axis vector based on the second solution; and
generating a composite optical axis vector based on the first optical axis vector and the second optical axis vector.
2. The method of claim 1, wherein the set of equations corresponds to a center point of the iris disc and at least three edge points of the plurality of edge points including the first edge point.
3. The method of claim 2, wherein the at least three edge points comprise end points of a major axis and at least one end point of a minor axis of the iris disc.
4. The method of claim 1,
wherein the first solution corresponds to end points of a major axis of the iris disc and a first end point of a minor axis of the iris disc; and
wherein the second solution corresponds to the end points of the major axis and a second end point of the minor axis.
5. The method of claim 4,
wherein the end points of the major axis correspond to a first point (x1, y1, z1) and a second point (x2, y2, z2) in the three-axis coordinate system, respectively,
wherein the first or second end point of the minor axis corresponds to a third point (x3, y3, z3) in the three-axis coordinate system, and
wherein the set of equations comprises:
2ir2=(Ax1M1\u2212Ax3M3)2+(Ay1M1\u2212Ay3M3)2+(Az1M1\u2212Az3M3)2,
2ir2=(Ax2M2\u2212Ax3M3)2+(Ay2M2\u2212Ay3M3)2+(Az2M2\u2212Az3M3)2,
4ir2=(Ax1M1\u2212Ax2M2)2+(Ay1M1\u2212Ay2M2)2+(Az1M1\u2212Az2M2)2,
where
ir=iris radius,
x1=M1 sin \u03c61 cos \u03b8a1=Ax1M1,
y1=M1 sin \u03c61 sin \u03b8a1=Ay1M1,
z1=M1 cos \u03c61=Az1M1,
M1 is a ray length between the spatial origin and the first point (x1, y1, z1),
\u03c61 and \u03b8a1 are angles associated with the first point (x1, y1, z1) and the ray length M1 in the three-axis coordinate system;
x2=M2 sin \u03c62 cos \u03b8a2=Ax2M2,
y2=M2 sin \u03c62 sin \u03b8a2=Ay2M2,
z2=M2 cos \u03c62=Az2M2,
M2 is a ray length between the spatial origin and the second point (x2, y2, z2),
\u03c62 and \u03b8a2 are angles associated with the second point (x2, y2, z2) and the ray length M2 in the three-axis coordinate system; and
x3=M3 sin \u03c63 cos \u03b8b1=Ax3M3,
y3=M3 sin \u03c63 sin \u03b8b1=Ay3M3,
z3=M3 cos \u03c63=Az3M3,
M3 is a ray length between the spatial origin and the third point (x3, y3, z3),
\u03c63 and \u03b8a3 are angles associated with the third point (x3, y3, z3) and the ray length M3 in the three-axis coordinate system.
6. The method of claim 5,
wherein estimating a ray length comprises estimating two values of the ray length M3, and
wherein solving the set of equations comprises:
calculating the plurality of solutions based on the estimated values of the ray length M3; and
determining a slope for a plurality of solution curves corresponding to the plurality of solutions.
7. The method of claim 6,
wherein calculating the iris diameter comprises calculating a spatial distance between the first point and the second point based on the solutions, and
wherein iteratively calculating an estimated iris diameter further comprises adjusting the estimated values of the ray length M3 based on a difference between the estimated iris diameter and the predetermined iris diameter.
8. The method of claim 1,
wherein the plurality of edge points comprise a first end point and a second end point of a major axis of the iris disc, and
the method further comprising:
determining spatial coordinates of the first and second end points in the three-axis coordinate system based on the solution; and
determining spatial coordinates of a center point of the iris disc in the ellipse based on the solution.
9. The method of claim 8, wherein calculating an optical axis vector of the eye comprises:
calculating a first vector involving the center point and the first end point;
calculating a second vector involving the center point and the second end point; and
calculating the optical axis vector as a cross product between the first vector and the second vector.
10. The method of claim 1,
wherein determining the ellipse equation comprises:
fitting a plurality of first edge points of the iris disc to a first ellipse;
generating a plurality of second edge points based on ellipse parameters of the first ellipse;
correcting the second edge points for at least one of image distortion or out-of-round iris; and
fitting the corrected second edge points to a second ellipse, and

wherein calculating the optical axis vector comprises utilizing ellipse parameters of the second ellipse to calculate the optical axis vector of the eye.
11. The method of claim 10, wherein correcting the second edge points comprises applying a distortion function on the second edge points.
12. The method of claim 10, wherein correcting the second edge points comprises:
adjusting each point of the second edge points in a direction \u03b1+\u03c02 by a value corresponding to a ratio of a major axis and a minor axis of the iris disc,
wherein \u03b1 is measured with respect to a line drawn in the iris disc between left and right iris center points, and ae is the major axis and be is a minor axis of the iris disc, and
wherein \u03b1 and aebe are the out-of-round constants for the eye.
13. A computing device, comprising:
a digital camera; and
a processor coupled to the camera and configured with processor-executable instructions to perform operations comprising:
obtaining a digital image of an eye with the digital camera;
processing the digital image to determine an optical axis vector of the eye in a three-axis coordinate system comprising X, Y and Z axes, wherein the processing comprises:
determining an ellipse equation defining an iris disc corresponding to the eye, on an XY plane of the three-axis coordinate system;
deriving a set of equations based on the ellipse equation corresponding to a plurality of edge points of the iris disc in the three-axis coordinate system; and
iteratively calculating an estimated iris diameter until a difference between the estimated iris diameter and a predetermined iris diameter is less than a threshold, comprising:
estimating a ray length from a spatial origin of the three-axis coordinate system to a first edge point of the plurality of edge points;
solving the set of equations based on the estimated ray length to calculate a plurality of solutions;
calculating the estimated iris diameter based on the solutions; and
calculating an optical axis vector of the eye in the three-axis coordinate system based on the solutions,

wherein the solutions comprise a first solution and a second solution based on two sets of the edge points, respectively, and
wherein calculating the optical axis vector comprises:
calculating a first optical axis vector based on the first solution, calculating a second optical axis vector based on the second solution; and
generating a composite optical axis vector based on the first optical axis vector and the second optical axis vector.
14. The computing device of claim 13,
wherein determining the ellipse equation comprises:
fitting a plurality of first edge points of the iris disc to a first ellipse;
generating a plurality of second edge points based on ellipse parameters of the first ellipse;
correcting the second edge points for at least one of image distortion or out-of-round iris; and
fitting the corrected second edge points to a second ellipse, and

wherein calculating the optical axis vector comprises utilizing ellipse parameters of the second ellipse to calculate the optical axis vector of the eye.
15. The computing device of claim 14, wherein correcting the second edge points comprises applying a distortion function on the second edge points.
16. The computing device of claim 14, wherein correcting the second edge points comprises:
adjusting each point of the second edge points in a direction \u03b1+\u03c02 by a value corresponding to a ratio of a major axis and a minor axis of the iris disc,
wherein \u03b1 is measured with respect to a line drawn in the iris disc between left and right iris center points, and ae is the major axis and be is a minor axis of the iris disc, and
wherein \u03b1 and aebe are the out-of-round constants for the eye.
17. A computing device, comprising:
means for obtaining a digital image of an eye; and
means for processing the digital image to determine an optical axis vector of the eye in a three-axis coordinate system comprising X, Y and Z axes, wherein the means for processing comprises:
means for determining an ellipse equation defining an iris disc corresponding to the eye, on an XY plane of the three-axis coordinate system;
mean for deriving a set of equations based on the ellipse equation corresponding to a plurality of edge points of the iris disc in the three-axis coordinate system; and
means for iteratively calculating an estimated iris diameter until a difference between the estimated iris diameter and a predetermined iris diameter is less than a threshold, comprising:
means for estimating a ray length from a spatial origin of the three-axis coordinate system to a first edge point of the plurality of edge points;
means for solving the set of equations based on the estimated ray length to calculate a plurality of solutions;
means for calculating the estimated iris diameter based on the solutions; and
means for calculating an optical axis vector of the eye in the three-axis coordinate system based on the solutions,
wherein the solutions comprise a first solution and a second solution based on two sets of the edge points, respectively, and
wherein the means for calculating the optical axis vector comprises:
means for calculating a first optical axis vector based on the first solution,
means for calculating a second optical axis vector based on the second solution; and
means for generating a composite optical axis vector based on the first optical axis vector and the second optical axis vector.
18. The computing device of claim 17,
wherein the means for determining the ellipse comprises:
means for fitting a plurality of first edge points of the iris disc to a first ellipse;
means for generating a plurality of second edge points based on ellipse parameters of the first ellipse;
means for correcting the second edge points for at least one of image distortion or out-of-round iris; and
means for fitting the corrected second edge points to a second ellipse, and

wherein the means for calculating the optical axis vector comprises means for utilizing ellipse parameters of the second ellipse to calculate the optical axis vector of the eye.
19. The computing device of claim 18, wherein means for correcting the second edge points comprises means for applying a distortion function on the second edge points.
20. The computing device of claim 18, wherein means for correcting the second edge points comprises:
means for adjusting each point of the second edge points in a direction \u03b1+\u03c02 by a value corresponding to a ratio of a major axis and a minor axis of the iris disc,
wherein \u03b1 is measured with respect to a line drawn in the iris disc between left and right iris center points, and ae is the major axis and be is a minor axis of the iris disc, and
wherein \u03b1 and aebe are the out-of-round constants for the eye.
21. A non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processor of a computing device including a digital camera to perform operations comprising:
obtaining a digital image of an eye with the digital camera; and
processing the digital image to determine an optical axis vector of the eye in a three-axis coordinate system comprising X, Y and Z axes, wherein the processing comprises:
determining an ellipse equation defining an iris disc corresponding to the eye, on an XY plane of the three-axis coordinate system;
deriving a set of equations based on the ellipse equation corresponding to a plurality of edge points of the iris disc in the three-axis coordinate system; and
iteratively calculating an estimated iris diameter until a difference between the estimated iris diameter and a predetermined iris diameter is less than a threshold, comprising:
estimating a ray length from a spatial origin of the three-axis coordinate system to a first edge point of the plurality of edge points;
solving the set of equations based on the estimated ray length to calculate a plurality of solutions;
calculating the estimated iris diameter based on the solutions; and
calculating an optical axis vector of the eye in the three-axis coordinate system based on the solutions,
wherein the solutions comprise a first solution and a second solution based on two sets of the edge points, respectively, and
wherein calculating the optical axis vector comprises:
calculating a first optical axis vector based on the first solution,
calculating a second optical axis vector based on the second solution; and
generating a composite optical axis vector based on the first optical axis vector and the second optical axis vector.
22. The non-transitory processor-readable storage medium of claim 21,
wherein determining the ellipse equation comprises:
fitting a plurality of first edge points of the iris disc to a first ellipse;
generating a plurality of second edge points based on ellipse parameters of the first ellipse;
correcting the second edge points for at least one of image distortion or out-of-round iris; and
fitting the corrected second edge points to a second ellipse, and

wherein calculating the optical axis vector comprises utilizing ellipse parameters of the second ellipse to calculate the optical axis vector of the eye.
23. The non-transitory processor-readable storage medium of claim 22, wherein correcting the second edge points comprises applying a distortion function on the second edge points.
24. The non-transitory processor-readable storage medium of claim 22, wherein correcting the second edge points comprises:
adjusting each point of the second edge points in a direction \u03b1+\u03c02 by a value corresponding to a ratio of a major axis and a minor axis of the iris disc,
wherein \u03b1 is measured with respect to a line drawn in the iris disc between left and right iris center points, and ae is the major axis and be is a minor axis of the iris disc, and
wherein \u03b1 and aebe are the out-of-round constants for the eye.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor memory device, comprising:
a plurality of memory banks that each comprise a plurality of memory cell arrays;
a plurality of sense amplification units corresponding to the memory banks and configured to sense data corresponding to a selected memory cell and amplify the sensed data; and
a common delay unit commonly coupled to the memory banks and configured to receive a plurality of bank active signals, delay a selected one of the plurality of bank active signals by a predetermined time using a common delay path, and generate the delayed bank active signal as an operation control signal for controlling one of the sense amplification units, wherein each of the plurality of bank active signals activates a corresponding one of the memory banks,
wherein the common delay unit comprises:
a common input unit configured to receive the bank active signals; and
a delay configured to delay an output signal of the common input unit by the predetermined time to output a delayed signal as the operation control signal, wherein an output node of the delay is coupled to inputs of all of the sense amplification units to supply the operation control signal.
2. The semiconductor memory device of claim 1, wherein the common delay unit comprises a transfer unit configured to transfer the delayed signal to a corresponding one of the sense amplification units as the operation control signal in response to the bank active signals.
3. The semiconductor memory device of claim 1, further comprising a delay control unit configured to generate a delay control signal for controlling the predetermined time of the common delay unit.
4. The semiconductor memory device of claim 1, wherein the memory banks and the sense amplification units are disposed in a core region, and the common delay unit is disposed in a peripheral region.
5. The semiconductor memory device of claim 1, wherein the operation control signal comprises a first operation control signal for controlling a first operation point of a respective one of the sense amplification units, and a second operation control signal for controlling a second operation point of the sense amplification unit.
6. The semiconductor memory device of claim 5, wherein the first operation control signal indicates a start point of an over-driving operation of the respective sense amplification unit, and the second operation control signal indicates an end point of the over-driving operation.
7. The semiconductor memory device of claim 5 wherein the first operation control signal indicates a start point of an over-driving operation of the respective sense amplification unit, and the second operation control signal indicates a start point of a normal-driving operation of the respective sense amplification unit.
8. A semiconductor memory device, comprising:
first and second memory banks that each comprise a plurality of memory cell arrays and are each configured to be activated in response to first and second bank active signals;
a common sense amplification unit commonly coupled to the memory banks and configured to sense data corresponding to a memory cell selected from the first and second memory banks and amplify the sensed data; and
a common delay unit commonly coupled to the memory banks and configured to receive the first and second bank active signals, delay a selected one of the first and second bank active signals by a predetermined time using a common delay path, and generate the delayed bank active signal as an operation control signal for controlling the common sense amplification unit,
wherein the common delay unit comprises:
a common input unit configured to receive the first and second bank active signals; and
a delay configured to delay an output signal of the common input unit by the predetermined time to output the operation control signal wherein an output node of the delay is coupled to an input of the common sense amplification unit to supply the operation control signal.
9. The semiconductor memory device of claim 8, further comprising a delay control unit configured to generate a delay control signal for controlling the predetermined time of the common delay unit.
10. The semiconductor memory device of claim 8, wherein the first and second memory banks are disposed in a core region, and the common sense amplification unit and the common delay unit are disposed in a peripheral region.
11. The semiconductor memory device of claim 8, wherein the operation control signal comprises a first operation control signal for controlling a first operation point of the common sense amplification unit, and a second operation control signal for controlling a second operation point of the common sense amplification unit.
12. The semiconductor memory device of claim 11, wherein the first operation control signal indicates a start point of an over-driving operation of the common sense amplification unit, and the second operation control signal indicates an end point of the over-driving operation.
13. The semiconductor memory device of claim 11, wherein the first operation control signal indicates a start point of an over-driving operation of the common sense amplification unit, and the second operation control signal indicates a start point of a normal-driving operation of the common sense amplification unit.
14. The semiconductor memory device of claim 8, wherein the common sense amplification unit is configured to receive the data in correspondence with the first and second memory banks through a plurality of global lines.
15. A semiconductor memory device, comprising:
a plurality of memory banks disposed in a core region, wherein the memory banks each comprise a plurality of memory cell arrays;
a plurality of sense amplification units disposed in the core region and corresponding to the memory banks, respectively, wherein the sense amplification units are each configured to sense data corresponding to a selected memory cell and amplify the sensed data;
a common delay unit disposed in a peripheral region and commonly coupled to the memory banks, wherein the common delay unit is configured to receive a plurality of bank active signals, delay a selected one of the plurality of bank active signals by a common delay time using a common delay path, and generate the delayed bank active signal as a first operation control signal for controlling a first operation timing point of a respective one of the sense amplification units and wherein each of the plurality of bank active signals activates a corresponding one of the memory banks; and
a plurality of individual delay units disposed between the common delay unit and the sense amplification units, respectively, and configured to each delay the first operation control signal by an individual delay time and generate the delayed first operation control signal as a second operation control signal for controlling a second operation timing point of the respective sense amplification unit,
wherein the common delay unit comprises:
a common input unit configured to receive the bank active signals; and
a delay having an input and an output and configured to delay an output signal of the common input unit by a predetermined time to output the delayed signal as the first operation control signal, wherein an output node of the delay is coupled to inputs of all of the sense amplification units to supply the operation control signal.
16. The semiconductor memory device of claim 15, wherein the common delay unit comprises a transfer unit configured to transfer the respective delayed signal of the common delay unit to a corresponding sense amplification unit as the operation control signal in response to the bank active signals.
17. The semiconductor memory device of claim 15, further comprising a delay control unit configured to generate a delay control signal for controlling a time delayed in the common delay unit and each of the individual delay units.
18. The semiconductor memory device of claim 15, wherein the first operation control signal indicates a start point of an over-driving operation of the respective sense amplification unit and the second operation control signal indicates an end point of the over-driving operation.
19. The semiconductor memory device of claim 15, wherein the first operation control signal indicates a star point of an over-driving operation of the respective sense amplification unit and the second operation control signal indicates a start point of a normal-driving operation of the respective sense amplification unit.
20. The semiconductor memory device of claim 15, wherein the common delay unit reflects a common delay time of each of a plurality of operation control signals comprising the first and second operation control signals.

1. A single channel full duplex wireless communication system, comprising:
a processor;
a transmitter connected to the processor, the transmitter transmitting a transmission signal via a transmission path;
a receiver connected to the processor, the receiver receiving a received signal via a reception path, wherein the transmitter and the receiver utilize one channel, at the same time, to transmit and receive said transmission and received signals, wherein a portion of the transmission signal is leaked, said leakage causing self-interference in the received signal;
a secondary transmission path connected to the processor;
the processor estimating a first transfer function, wherein the input to the first transfer function is adjusted by the first transfer function so as to produce an output to reduce the self-interference in the received signal, and feeding the input of the secondary transmission path with the output from the first transfer function;
a combiner to combine the received signal with the output from the secondary transmission path, thereby removing at least a fraction of the self-interference; and
a transmission feedback path, the transmission feedback path output being modified by a second transfer function; and
a secondary transmission feedback path, the secondary transmission feedback path output being modified by a third transfer function, such that combining of the modified transmission feedback path output and the modified secondary transmission feedback path output with the reception path output reduces a remaining fraction of the self-interference.
2. The system of claim 1, wherein the transmitter and the receiver utilize one antenna to transmit and receive signals, the antenna being connected to both the transmitter and the receiver via a circulator-like device, wherein said circulator-like device isolates the transmission signal from the received signal through use of one of passive noise cancellation techniques, active noise cancellation techniques, or any combination thereof.
3. The system of claim 1, further comprising a first antenna and a second antenna, wherein the first antenna is a transmission antenna and the second antenna is a receiver antenna, the first antenna connected to the transmitter and the second antenna connected to the receiver.
4. The system of claim 1, comprising multiple transmission paths and multiple reception paths.
5. The method of claim 1, further comprising a first antenna and a second antenna, wherein the first antenna is a transmission antenna and the second antenna is a receiver antenna, the first antenna connected to the transmitter and the second antenna connected to the receiver.
6. A method of improving signal-to-interference ratio in a single channel full duplex wireless communication system, comprising:
transmitting, by a transmitter, a transmission signal via a transmission path;
receiving, by a receiver, a received signal via a reception path, the transmission path and the reception path utilizing one channel, at the same time, to transmit and receive the transmission and received signals, wherein a portion of the transmission signal is leaked, said leakage causing self-interference in the received signal;
estimating, by a processor, a first transfer function, wherein the input to the first transfer function is adjusted by the first transfer function so as to produce an output to remove at least a fraction of the self-interference in the received signal;
feeding, by the processor, the input of a secondary transmission path with the output from the first transfer function, the secondary transmission path being connected to the processor;
combining, by a combiner, the received signal with the output from the secondary transmission path, thereby removing at least a fraction of the self-interference; and
estimating, by the processor, a second transfer function;
modifying, by the processor, a transmission feedback path output signal with the second transfer function;
estimating, by the processor, a third transfer function;
modifying, by the processor, a secondary transmission feedback path output signal with the third transfer function; and
adding, by the processor, the modified transmission feedback path output and the modified secondary transmission feedback path output to the reception path output, thereby reducing the remaining fraction of the self-interference.
7. The method of claim 6, wherein the transmitter and the receiver utilize one antenna to transmit and receive signals, the antenna being connected to both the transmitter and the receiver via a circulator-like device, wherein said circulator-like device isolates the transmission signal from the received signal through use of one of passive noise cancellation techniques, active noise cancellation techniques, or any combination thereof.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method comprising:
forming a thin metal-organic layer on a copper structure, wherein the thin metal-organic layer prevents corrosion of the copper structure, and wherein the thin metal-organic layer comprises an organo-copper compound comprising an alkyl group and a thiol group.
2. The method of claim 1 wherein the thin metal-organic layer substantially covers the copper structure.
3. The method of claim 1 wherein forming the thin metal-organic layer comprises cleaning the copper structure with a cleaning solution, wherein the cleaning solution comprises a corrosion inhibitor that reacts with the copper structure to form the thin metal-organic layer.
4. The method of claim 3 wherein the corrosion inhibitor comprises at least one of hexanethiol, heptanethiol, octanethiol, and dodecanethiol.
5. The method of claim 3 wherein the corrosion inhibitor comprises an organic molecule comprising a thiol group.
6. The method of claim 3 wherein the cleaning solution comprises a mixture of water and solvent with a high pH value to remove at least one of resist, SLAM and polymer material.
7. The method of claim 1 wherein forming the thin metal-organic layer prevents the formation of pinholes in the copper structure.
8. The method of claim 4 wherein the corrosion inhibitor comprises a concentration of less than 1 percent by weight of at least one of hexanethiol, heptanethiol, octanethiol, and dodecanethiol.
9. The method of claim 3 wherein the cleaning solution comprises at least one of an alkaline aqueous, solvent, or aqueous-solvent chemistry.
10. The method of claim 3 wherein the pH of the cleaning solution comprises above about 7.
11. The method of claim 3 wherein the copper etch rate of the corrosion inhibitor is about 1 nm per hour or less.
12. The method of claim 1 wherein the thin metal-organic layer comprises a thickness of about 2 nm or less.
13. A method comprising:
cleaning a microelectronic device surface with a cleaning solution, wherein the cleaning solution comprises a surfactant comprising a sulfonate functional group, and wherein a contact angle between the surfactant and the microelectronic device surface comprises about 40 degrees or below.
14. The method of claim 13 further comprising wherein the microelectronic device surface comprises a portion of a microelectronic device structure, wherein the aspect ratio of the microelectronic device structure is greater than about 3:1.
15. The method of claim 13 further comprising wherein an initial foaming of the surfactant is less than about 200 ml.
16. The method of claim 13 further comprising wherein the cleaning solution comprises a pH above about 7.
17. The method of claim 13 wherein the cleaning solution comprises a mixture of water and solvent to remove at least one of resist, SLAM and etch-polymer material.
18. The method of claim 13 further comprising wherein the microelectronic device surface comprises a hydrophobic CDO material.
19. The method of claim 13 further comprising wherein the surfactant comprises an anionic organic material comprising at least one of an alkanol polyethoxylate chain and an alkanol aromatic ring, alkano polyethylene oxide sulfopropyl ether and alkyl benzene sulfonate
20. The method of claim 19 further comprising at least one of potassium salt and glycol.
21. A cleaning solution comprising:
a mixture of water and solvent;
a corrosion inhibitor, wherein the corrosion inhibitor comprises an organic molecule comprising a thiol group; and
a surfactant, wherein the surfactant comprises an anionic organic material.
22. The cleaning solution of claim 21 wherein the cleaning solution is capable of removing at least one of resist, SLAM and polymer material.
23. The cleaning solution of claim 21 wherein the surfactant comprises a concentration of about 0.1 to about 1.0 percent by weight.
24. The cleaning solution of claim 21 wherein the pH of the cleaning solution comprises above about 7.
25. The cleaning solution of claim 21 wherein the corrosion inhibitor comprises a concentration of less than 1 percent by weight of at least one of hexanethiol, heptanethiol, octanethiol, and dodecanethiol.
26. The cleaning solution of claim 21 wherein the copper etch rate of the corrosion inhibitor is about 0.2 nm per hour or less.
27. The cleaning solution of claim 21 wherein the surfactant comprises at least one of an alkanol polyethoxylate chain and an alkanol aromatic ring, alkano polyethylene oxide sulfopropyl ether and alkyl benzene sulfonate, a potassium salt and glycol.