Author: claimsbot

1. A method for detecting an error in an interaction between a plurality of software systems, comprising:
providing information about at least one of at least first and second software systems, and a mapping between at least a portion of said at least first and second software systems;
automatically generating a check based upon the information and the mapping;
inserting said check into at least one of said first and second software systems; and
examining said at least one of said first and second software systems and said mapping to determine an error in an interaction between said at least first and second software systems based upon said check.
2. The method of claim 1, wherein said information provided about at least one software system of said at least first and second software systems includes at least one of:
an XML schema of said at least one software system;
integrity constraints of said at least one software system, said integrity constraints of said at least first and second software systems being represented in a common constraint model;
a specification of said at least one software system;
a unified modeling language (UML) model of said at least one software system; and
code of said at least one software system.
3. The method of claim 1, wherein said information provided about at least one software system of said at least first and second software systems includes at least one of:
information about a sub-component of said at least one software system; and information about less than an entirety of said at least one software system.
4. The method of claim 1, wherein one of said first and second software systems comprises at least one of a database, an application, an extensible markup language (XML) repository and an XML database,
wherein said information provided about said at least one software system of said at least first and second software systems includes at least one of schema information of said database and information about values in said database, and programming language types.
5. The method of claim 1, wherein said mapping is provided one of explicitly and inferred from said information about said at least first and second software systems.
6. The method of claim 1, wherein said error comprises one of an integrity constraint violation, a potential error representing a warning that an error may occur, and a definite error representing one of that an error will occur and that an error has occurred, wherein said error is found prior to said interaction between the at least first and second software systems.
7. The method of claim 1, wherein said error is found one of during said run time of the at least first and second software systems and prior to any of said interaction between the at least first and second software systems.
8. The method of claim 1, wherein said check is one of:
inserted at a location directed by a programmer;
performed after an interaction between said at least first and second software systems;
performed before an interaction between said at least first and second software systems; and
performed prior to an end of a transaction.
9. The method of claim 2, further comprising:
performing static analysis of said at least first and second software systems to at least one of simplify, eliminate, and approximate said check;
analyzing said integrity constraints in said common constraint model; and
based on said analyzing, if an inconsistency is detected, then outputting an error.
10. The method of claim 2, further comprising one of:
modifying said integrity constraints in said common constraint model; and
generating a check from said integrity constraints.
11. The method of claim 1, further comprising:
providing a shadow database in one of said at least first and second software systems,
said shadow database containing partial knowledge of the other of said at least first and second software systems and being used to perform a check,
wherein said partial knowledge includes at leaset one of:
partial knowledge of data values in said other of said at least first and second software systems; and
partial knowledge of non-existence of data values in said other of said at least first and second software systems.
12. The method of claim 1, further comprising:
reporting said error, wherein said reporting comprises one of:
notifying before running at least one of said at least first and second software systems;
notifying while running at least one of said at least first and second software systems;
allowing said one of said at least first and second software systems to address said error;
suggesting how said error may be addressed.
13. A method of detecting an error in a database interaction, comprising:
examining database code for database constraints;
examining application code for application-level constraints;
automatically generating a check based upon said database constraints and said application-level constraints;
inserting said check into at least one of said database code and said application code; and
analyzing a mapping between said database code and said application code, to determine an error in a database interaction, based upon said check.
14. The method of claim 13, further comprising:
generating a check in said application code for enforcing said database and application-level constraints.
15. The method of claim 13, further comprising:
forming a shadow database in said application code representing a portion of said database.
16. The method of claim 13, wherein said error comprises an integrity constraint violation.
17. The method of claim 13, further comprising:
inputting said database constraints and said application-level constraints, and said mapping into a common constraint model; and
before a program including said application and interacting with said database, is run and after said inputting, performing a static analysis to identify locations of where an error may arise.
18. The method of claim 13, further comprising:
after identifying said error and prior to running a program including said application, raising a notification.
19. The method of claim 13, wherein, at runtime of said program, when an error is detected as occurring, raising a notification.
20. A method of detecting an integrity constraint violation in a database interaction, comprising:
examining a database schema;
examining an application type;
automatically generating a check based upon said database schema and said application type;
inserting said check into one of said database schema and said application type; and
analyzing a mapping between said database schema and said application type, to determine whether an integrity constraint violation will occur in said database interaction with said application based upon said check,
wherein said database schema provides each of the integrated constraints defined in the database, and
wherein said application type includes application code including integrity constraints defined therein.
21. The method of claim 20, further comprising one of:
generating a check in said application code for enforcing said database and application-level constraints; and
forming a shadow database in application code representing a portion of said database.
22. The method of claim 20, further comprising:
inputting said database schema, said application type, and said mapping into a common constraint model;
before a program including said application and interacting with said database, is run and after said inputting, performing a static analysis to identify locations of where said integrity constraint violation may arise.
23. The method of claim 20, further comprising:
after determining said integrity constraint violation and prior to running a program including said application, raising a notification;
further comprising at least one of:
at runtime of said program, when an integrity constraint violation is determined to occur, raising a notification; and
analyzing a common constraint model receiving said database schema, application type, and mapping, to determine an inconsistency between said database schema and said application type, wherein if no said inconsistency is determined, then taking all of the common constraints and analyzing the application code with respect to the common constraints for an error in the application code, wherein if no said error is determined in the application code, then inserting a check into said application code to enforce the constraints at runtime.
24. A system of detecting an error in a database interaction, comprising:
a module for examining a database code for database constraints;
a module for examining an application code for application-level constraints;
a module for automatically generating a check based upon said database constraints and said application-level constraints;
a module for inserting said check into one of said database code and said application code; and
an analyzing unit for analyzing a mapping between said database code and said application code, to determine an error in a database interaction based upon said check.
25. A method for detecting an error in an interaction between a plurality of software systems, comprising:
providing information about at least one of at least first and second software systems, and a mapping between at least a portion of said at least first and second software systems; and
statically examining said at least one of said first and second software systems and said mapping to determine an error in an interaction between said at least first and second software systems.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of testing a plurality of interferometric modulators, comprising:
applying a triangular voltage waveform to the interferometric modulators; and
detecting reflectivity of light from the interferometric modulators.
2. The method of claim 1, wherein the step of applying a triangular waveform causes the interferometric modulators to vary between an actuated and a non-actuated state.
3. The method of claim 1, wherein the triangular waveform has a frequency of less than about 20 Hz.
4. The method of claim 3, wherein the triangular waveform has a frequency from about 1 Hz to about 15 Hz.
5. The method of claim 1, wherein the amplitude of the triangular waveform is greater than the voltage necessary to cause a positive or negative going actuation of the interferometric modulators.
6. The method of claim 5, wherein the amplitude of the triangular waveform is less than about 1.5 times the voltage necessary to cause a positive or negative going actuation of the interferometric modulators.
7. The method of claim 1, wherein the triangular voltage waveform is simultaneously applied to all interferometric modulators in a reflective display.
8. The method of claim 1, wherein the detecting step includes detecting reflectivity from less than all interferometric modulators in a reflective display.
9. The method of claim 1, wherein the detecting step includes measuring reflectivity with a photodetector.
10. The method of claim 1, wherein the detecting step includes measuring reflectivity through a diffuser positioned in front of the interferometric modulators.
11. The method of claim 1, wherein the detecting step includes measuring reflectivity at an angle that is substantially perpendicular to the interferometric modulators.
12. A method of determining electrical parameters for driving a plurality of inteferometric modulators, comprising:
applying a time-varying voltage stimulus to the interferometric modulators;
detecting reflectivity of light from the interferometric modulators; and
determining one or more electrical parameters from said reflectivity of light in response to said time-varying voltage stimulus, the electrical parameters indicative of electrical parameters sufficient to cause a change in state of the interferometric modulators.
13. The method of claim 12, wherein the determining step includes determining a voltage necessary to cause the interferometric modulators to change from a non-actuated to an actuated state.
14. The method of claim 12, wherein the determining step includes determining a voltage necessary to cause the interferometric modulators to change from an actuated state to a non-actuated.
15. The method of claim 12, wherein the determining step includes determining amplitude of a bias voltage in the interferometric modulators.
16. The method of claim 12, wherein the determining step includes determining amplitude of an offset voltage in the interferometric modulators.
17. The method of claim 12, wherein the determining step includes determining amplitude of a memory window in the interferometric modulators.
18. The method of claim 12, wherein the determining step includes:
normalizing the reflectivity to one or more pre-determined values; and
determining potentials where the normalized reflectivity crosses zero.
19. A method of testing a plurality of interferometric modulator structures, comprising:
applying a time-varying voltage waveform to the interferometric modulators;
detecting reflectivity of light from the interferometric modulators;
determining reflectivity of light as a function of voltage; and
identifying the plurality of interferometric modulators as of sufficient quality for use in a display based on said determining.
20. The method of claim 19, wherein the interferometric modulators are identified as of sufficient quality for use in the display if said reflectivity of light as a function of voltage displays a predefined hysteresis characteristic.
21. The method of claim 19, wherein the interferometric modulators are identified as of sufficient quality for use in the display if said reflectivity of light as a function of voltage indicates an amplitude of a memory window of the interferometric modulators is within a predefined threshold window.
22. The method of claim 19, wherein the interferometric modulators are identified as of sufficient quality for use in the display if said reflectivity of light as a function of voltage indicates an amplitude of a bias voltage of the interferometric modulators is within a predefined threshold window.
23. A system for testing a plurality of interferometric modulators, comprising:
an illumination source adapted to provide incident light to a plurality of interferometric modulators;
a voltage source adapted to apply enough voltage to the interferometric modulators so as to change their state; and
an optical detector adapted to detect light reflected from the plurality of interferometric modulators.
24. The system of claim 23, wherein the illumination source provides incident light at an angle that is substantially perpendicular to the interferometric modulators.
25. The system of claim 23, wherein the voltage source is simultaneously electrically connected to all interferometric modulators in a reflective display.
26. The system of claim 23, wherein the voltage source is adapted to apply a time-varying voltage waveform.
27. The system of claim 26, wherein the voltage source is adapted to apply a triangular voltage waveform.
28. The system of claim 23, wherein the optical detector is a photo detector.
29. The system of claim 23, wherein the optical detector is adapted to detect light from less than all interferometric modulators in a reflective display.
30. The system of claim 23, wherein the optical detector is adapted to detect light at an angle that is substantially perpendicular to the interferometric modulators.
31. The system of claim 23, wherein the optical detector is adapted to detect light through a diffuser.
32. The system of claim 23, further including a filter disposed in front of the optical detector.
33. A method of testing a plurality of inteferometric modulators, comprising:
applying a time-varying voltage waveform to the interferometric modulators;
detecting reflectivity of light from the interferometric modulators;
repeating said applying and detecting steps one or more times;
averaging at least a portion of the detected reflectivity; and
determining one or more electrical parameters from said averaged reflectivity.
34. A method of testing a color interferometric modulator display, the display comprising a plurality of sub-pixel types, each sub-pixel type corresponding to a different color, the method comprising:
applying a time-varying voltage waveform to one sub-pixel type;
detecting reflectivity of light from said sub-pixel type;
determining one or more electrical parameters from said detecting; and
repeating said applying, detecting, and determining steps for another sub-pixel type.
35. A method of testing a plurality of interferometric modulators, comprising:
a means for applying a time-varying voltage waveform to the interferometric modulators;
a means for detecting reflectivity of light from the interferometric modulators; and
a means for determining one or more parameters based on said detected reflectivity.
36. The method of claim 35, wherein the means for applying a time-varying voltage waveform is a voltage source.
37. The method of claim 35, wherein the means for detecting reflectivity is a photo detector.
38. The method of claim 35, wherein the means for determining one or more parameters is a computer.

1. A method of manufacturing a semiconductor device having a twin well structure, comprising:
ion-implanting of a first conductivity type impurity in a first region and a second region of a semiconductor substrate, the first and second regions being located adjacent to each other;
forming a first resist pattern to cover the first region of the semiconductor substrate and to expose the second region of the semiconductor substrate;
ion-implanting of a second conductivity type impurity at a higher concentration compared to the first conductivity type impurity in the second region of the semiconductor substrate, with the first resist pattern being used as a mask; and
thermal-diffusing the first conductivity type of impurity and the second conductivity type of impurity.
2. The method according to claim 1, further comprising:
forming a silicon oxide film having a first portion on the first region of the semiconductor substrate and a second portion on the second region of the semiconductor substrate, the second portion having a smaller thickness than that of the first portion;
forming a second resist pattern on the silicon oxide film exposing a part of the first portion and a part of the second portion of the silicon oxide film;
ion-implanting an impurity in a part of the second region of the semiconductor substrate, with the first part of the silicon oxide film and the second resist pattern being used as a mask;
forming a field oxide film by selectively causing the film at the portion of the silicon oxide film exposed from the second resist pattern to grow.
3. The method according to claim 2, wherein the forming of the silicon oxide film comprises:
forming a silicon oxide film on the first region and the second region of the semiconductor substrate before the forming of the first resist pattern; and
forming the second portion of the silicon oxide film, after forming the first resist pattern, by removing an upper portion of the silicon oxide film covering the second region, with the first resist pattern being used as a mask.
4. The method according to claim 2, wherein the forming of the silicon oxide layer comprises:
forming a silicon oxide film on the first region and the second region of the semiconductor substrate before the forming of the first resist pattern;
removing the portion of the silicon oxide film covering the second region, after forming the first resist pattern, with the first resist pattern being used as a mask; and
forming the second portion of the silicon oxide by thermal-oxidizing the second region of the semiconductor substrate by the thermal-diffusion.
5. The method according to claim 1,
wherein a concentration of the second conductivity type impurity is more than double a concentration of the first conductivity type impurity.
6. The method according to claim 1, further comprising performing annealing of the semiconductor substrate in a non-oxidizing atmosphere.
7. The method according to claim 1, further comprising forming an ink supply port passing through the second region of the semiconductor substrate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for testing a joystick control circuit, wherein said joystick control circuit is connected to a game port that comprises a plurality of pins addressed to a plurality of joystick buttons, comprising steps of:
providing a testing device, latching under an order signal, either shorted circuit or opened circuit in said pins of said game port addressed to said joystick buttons;
connecting said testing device to said game port;
outputting a short circuit signal to said testing device for shorting circuit in said pins addressed to said joystick buttons;
determining whether said joystick control circuit is in a state in accordance with a push-on of said joystick buttons;
outputting an open circuit signal to said testing device for opening circuit in said pins of said game port addressed to said joystick buttons; and
determining whether said joystick control circuit is in a state in accordance with a release of said joystick buttons.
2. The method of claim 1, wherein after outputting said short circuit signal to said testing device, if said joystick control circuit not in a configuration of a push-on of said joystick buttons, said joystick control circuit is evaluated as deficient with respect to a push-on of said joystick buttons.
3. The method of claim 1, wherein after outputting said open circuit signal to said testing device, if said joystick control circuit is not in a configuration of a release of said joystick buttons, said joystick control circuit is evaluated as deficient with respect to a release of said joystick buttons.
4. The method of claim 1, wherein said game port comprises a signal pin through which either said short circuit signal and said open circuit signal can be output to said testing device.
5. A method for testing a joystick control circuit, achieved in a testing device, comprising the steps of testing one of game port pins addressed to a joystick button, wherein said game port pin is connected to said test device, outputting a short circuit signal to a latch device for controlling a switching device of said testing device to be at a short-circuit state, after ascertaining said joystick control circuit which is in a state in accordance with a push-on of said joystick button, outputting an open circuit signal to open the switching device of said testing device.
6. An apparatus for testing a joystick control circuit, wherein said joystick control circuit is connected to a game port to which is connected said apparatus, said game port having a plurality of pins among which is a plurality of pins addressed to a plurality of joystick buttons, comprising:
a connector that has a plurality of pinholes corresponding to said pins of said game port, wherein said pinholes of said connector comprise a signal pinhole and a plurality of pinholes corresponding to said pins of said game port addressed to said joystick buttons;
an electric switch, connected to said pinholes of said connector; and
a latch device, connected to said electric switch and said signal pinhole of said connector, wherein said signal pinhole delivers an order signal to said latch device to command said electric switch to either shorted circuit or opened circuit said pinholes of said connector addressed to said joystick buttons.
7. The apparatus of claim 6, wherein said apparatus further comprises:
a first resistor that simulates a joystick displacement along an X direction;
a second resistor that simulates a joystick displacement along a Y direction;
a third resistor that simulates ajoystick displacement along an X direction; and
a fourth resistor that simulates a joystick displacement along a Y displacement.
8. The apparatus of claim 7, wherein said signal pinhole is connected to one of either said first resistor, said second resistor, said third resistor or said fourth resistor, and serves as an input signal pinhole when said joystick control circuit is tested.
9. The apparatus of claim 8, wherein said pinholes of said connector are:
pinhole 2, connected to said electric switch;
pinhole 3, connected to said first resistor;
pinhole 6, connected to said second resistor;
pinhole 7, connected to said electric switch;
pinhole 10, connected to said electric switch;
pinhole 11, connected to said third resistor;
pinhole 13, connected to said fourth resistor;
pinhole 14, connected to said electric switch;
pinholes 1, 8, and 9 connected to a continuous voltage source; and
pinholes 4 and 5 connected to said electric switch and a ground node.
10. The apparatus of claim 9, wherein said pinholes of said connector that are addressed to said joystick buttons are said pinholes 2, 7, 10, and 14.
11. The apparatus of claim 9, wherein said signal pinhole is said pinhole 3 or 6.
12. The apparatus of claim 6, wherein said electric switch is a transistor.
13. The apparatus of claim 6, wherein said latch device is a flip-flop device.