Author: claimsbot

1. A fork-lift reach truck having an extraction mast which is adapted to be displaced, by means of a mast drive, towards and away from a driving portion of the fork-lift truck on a horizontal guide, a load-carrying means which is mounted on a side shift, a side shift guide which is supported by the extraction mast in a height-adjustable way and is adapted to be actuated by means of a lifting and lowering drive, which guides the side shift in a laterally movable way, and a side shift drive, and an electric control and regulation device for the respective drives which is connected to operating members for the lifting and lowering modes, the mast extraction mode, and the side shift mode, characterized in that an analog sensor (30) detecting the position of the side shift (20) is provided the position signal of which is sent to the control and regulation device (34), and that the control and regulation device (34) is connected to a separate operating member for the side shift (20) or the operating member for the side shift is configured in such a way that actuating it causes the side shift (20) to be automatically moved to a predetermined position, preferably a middle position.
2. The fork-lift reach truck as claimed in claim 1, characterized in that the operating member (36) for the side shift (20) is configured as a set point transmitter which, in response to its displacement path or angle, generates a set point signal for the control and regulation device (34).
3. The fork-lift reach truck as claimed in claim 1, characterized in that the control and regulation device (34) sends a signal to the side shift drive (26) to move to the predetermined position when a signal for a retraction of the mast (12) is generated by the operating member (42) for the mast extraction andor a signal for the lowering of the load-carrying means (16) is generated by the operating member (44) for the lifting and lowering modes.
4. The fork-lift truck as claimed in claim 1, characterized in that the control and regulation device (34) is connected to an onboard computer (46) andor forms part thereof, the onboard computer (34) limits the traveling andor cornering speed of the fork-lift truck in conformity with stability criteria and the position signal of the sensor (30) is sent to the onboard computer (46) for a modification of the traveling speed of the fork-lift truck in dependence on the position of the side shift (20).

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a memory cell region including a plurality of magnetoresistive elements formed over the main surface of the semiconductor substrate, and changing in electrical resistance according to the direction of magnetization, disposed therein, the magnetoresistive element including a magnetization fixed layer fixed in direction of magnetization, a magnetization free layer made variable indirection of magnetization, and a tunneling insulation layer interposed between the magnetization fixed layer and the magnetization free layer;
an interlayer insulation film disposed at the same layer as the magnetoresistive elements;
a peripheral circuit region disposed in the periphery of the memory cell region in plan view;
a plurality of first wires formed above the magnetoresistive elements, extending in the direction along the main surface, and coupled to the top surfaces of the magnetoresistive elements; and
a multilayer structure disposed in the peripheral circuit region so as to overlap a second wire formed of the same layer as the first wire in plan view, the multilayer structure comprising a layer equal in material to the magnetization free layer forming the magnetoresistive element, a layer equal in material to the tunneling insulation layer, and a layer equal in material to the magnetization fixed layer,
wherein the multilayer structure is disposed so as not to overlap both of a pair of the adjacent second wires in plan view in the peripheral circuit region.
2. The semiconductor device according to claim 1, wherein the multilayer structure extends along the second wire in the peripheral circuit region in plan view.
3. The semiconductor device according to claim 1, wherein the multilayer structure is divided into a plurality of small multilayer structures with respect to the direction along the second wire in the peripheral circuit region in plan view.
4. The semiconductor device according to claim 3, wherein the small multilayer structure is disposed in such a manner as not to overlap a coupling wire for electrically coupling the second wire and other circuits over the main surface in plan view.
5. The semiconductor device according to claim 1, wherein the multilayer structure is disposed smaller than the second wire in plan view.
6. The semiconductor device according to claim 1, wherein the multilayer structure is disposed in such a manner as to overlap the entire surface of the second wire in plan view in the peripheral circuit region.
7. The semiconductor device according to claim 6, wherein the multilayer structure is disposed larger than the second wire in plan view.
8. The semiconductor device according to claim 1, wherein the sum of occupancy rates of regions including the multilayer structures disposed therein relative to the whole of the peripheral circuit region in plan view is larger than the sum of occupancy rates of regions including the magnetoresistive elements disposed therein in the whole of the memory cell region.
9. The semiconductor device according to claim 1, comprising an additional multilayer structure having the same configuration as that of the multilayer structure at a position at which the second wire is not disposed in the peripheral circuit region in plan view.
10. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a memory cell region including a plurality of resistance recording elements formed over the main surface of the semiconductor substrate, and changing in electrical resistance according to the application of a voltage, disposed therein;
an interlayer insulation film disposed at the same layer as the resistance recording elements; and
a peripheral circuit region disposed in the periphery of the memory cell region in plan view,
the resistance recording element including a first metal electrode, an insulation film, and a second metal electrode stacked in this order,
the semiconductor device, comprising:
above the resistance recording elements, a plurality of first wires extending in the direction along the main surface, and coupled to the top surfaces of the resistance recording elements; and
in the peripheral circuit region, a multilayer structure of lamination of a layer equal in material to the first metal electrode forming the resistance recording element, a layer equal in material to the insulation film, and a layer equal in material to the second metal electrode, disposed in such a manner as to overlap a second wire formed of the same layer as the first wire in plan view,
the multilayer structure being disposed in such a manner as not to overlap both of a pair of the adjacent second wires in plan view in the peripheral circuit region.
11. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a memory cell region including a plurality of phase change recording elements formed over the main surface of the semiconductor substrate, and changing in electrical resistance according to the phase change, disposed therein;
an interlayer insulation film disposed at the same layer as the phase change recording elements; and
a peripheral circuit region disposed in the periphery of the memory cell region in plan view,
the phase change recording element including a first metal electrode, a phase change layer, and a second metal electrode stacked in this order,
the semiconductor device, comprising:
above the phase change recording elements, a plurality of first wires extending in the direction along the main surface, and coupled to the top surfaces of the phase change recording elements; and
in the peripheral circuit region, a multilayer structure of lamination of a layer equal in material to the first metal electrode forming the phase change recording element, a layer equal in material to the phase change layer, and a layer equal in material to the second metal electrode, disposed in such a manner as to overlap a second wire formed of the same layer as the first wire in plan view,
the multilayer structure being disposed in such a manner as not to overlap both of a pair of the adjacent second wires in plan view in the peripheral circuit region.

1. A method for reducing artifacts in at least one image comprising:
defining a region in at least one first image, the defined region having at least one artifact;
tracking the defined region to at least one second image; and
applying an error diffusion function to the defined region to mask the at least one artifact in the at least one first and second images.
2. The method as in claim 1, wherein the applying step further comprises:
selecting a block size of pixels of the at least one image;
determining if at least one block is within the defined region;
adding a masking signal to the at least one block;
determining a quantization error for the at least one block in the at least one image; and
distributing the quantization error to neighboring blocks.
3. The method of claim 2, further comprising, after the distributing step, encoding the at least one first and second images with a compression function.
4. The method as in claim 3, wherein the compression function is lossy.
5. The method as in claim 2, wherein the adding a masking signal step comprises:
determining a distance of at least one pixel in the at least one block to a boundary of the defined region; and
assigning a value to a masking signal associated to the at least one pixel based on the determined distance.
6. The method as in claim 2, wherein the masking signal is a noise signal.
7. The method as in claim 2, wherein the determining the quantization error step further comprises:
truncating each pixel in the at least one block;
determining a quantization error for each pixel; and
summing the quantization error of each pixel in the at least one block.
8. The method as in claim 1, wherein the tracking step further comprises:
generating a binary mask for the defined region of the at least one first image; and
projecting the binary mask to the at least one second image to track the defined region.
9. The method as in claim 8, wherein the projecting step further comprises estimating the motion of the defined region from the at least one first image to the at least one second image.
10. The method as in claim 9, wherein the estimating step is performed by an affine motion model.
11. The method as in claim 8, wherein the generating step further comprises transforming the defined region into a larger region to capture features of the at least one first image to be tracked.
12. The method as in claim 1, wherein the defining a region step is performed manually by outlining the region or automatically by a detection function.
13. A system for reducing artifacts in at least one image, the system comprising:
a tracking module configured for tracking a defined region in at least one first image to at least one second image, the defined region having at least one artifact; and
an error diffusion module configured for applying an error diffusion function to the defined region to mask the at least one artifact in the at least one first and second images.
14. The system as in claim 13, further comprising a user interface configured for defining the region in the at least one first image.
15. The system as in claim 13, further comprising an encoder configured for encoding the at least one first and second images with a compression function.
16. The system as in claim 13, wherein the error diffusion module further comprises a signal generator configured for generating a masking signal to be applied to at least one image; wherein the error diffusion module is further configured for selecting a block size of pixels of the at least one image, determining if at least one block is within the defined region; determining a quantization error for the at least one block in the at least one image; and distributing the quantization error to neighboring blocks.
17. The system as in claim 16, wherein the signal generator is configured to generate a noise signal.
18. The system as in claim 16, wherein the error diffusion module is further configured for determining a distance of at least one pixel in the at least ones block to a boundary of the defined region; and assigning a value to a masking signal associated to the at least one pixel based on the determined distance.
19. The system as in claim 16, wherein the error diffusion module further comprises a truncation module configured to truncate each pixel in the at least one block, determine a quantization error for each pixel and sum the quantization error of each pixel in the at least one block.
20. The system as in claim 13, wherein the tracking module further comprises a mask generator configured for generating a binary mask for the defined region of the at least one first image; wherein the tracking module is further configured for projecting the binary mask to the at least one second image to track the defined region.
21. The system as in claim 20, wherein the tracking module further comprises a tracking model configured to estimate the motion of the defined region from the at least one first image to the at least one second image.
22. The system as in claim 21, wherein the tracking model is an affine motion model.
23. The system as in claim 20, wherein the tracking module is further configured for transforming the defined region into a larger region to capture features of the at least one first image to be tracked.
24. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for reducing artifacts in an image, the method comprising:
defining a region in at least one first image, the defined region having at least one artifact;
tracking the defined region to at least one second image; and
applying an error diffusion function to the defined region to mask the at least one artifact in the at least one first and second images.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for forming a casting comprising:
flowing molten metal substantially vertically into a mold by means of a feeder tube;
impeding the flow of oxides that collect at the perimeter of the head of the feeder tube by directing the molten metal through a filter disposed proximate to the end of the feeder tube, wherein said filter has a conical shape and protrudes into a mold cavity of the mold and is held in position by a counter force provided by a divider that protrudes from an opposite side of the mold cavity;
reducing inclusions in the molten metal by inducing laminar flow of the molten metal as it moves through said filter; and
allowing the molten metal to solidify.
2. The method of claim 1 wherein impeding the flow of oxides that collect at the perimeter of the head of the feeder tube comprises filtering the molten metal proximate to the perimeter of the head of the feeder tube.
3. The method of claim 1 wherein inducing laminar flow in the molten metal comprises:
restricting the flow of the molten metal to a progressively smaller cross section as the molten metal proceeds into the mold.
4. The method of claim 1 wherein impeding the flow of oxides and reducing inclusions in the molten metal is accomplished by introducing a filter proximate to the head of the feeder tube wherein the filter is made of a fiberous material that is inert relative to the molten metal and further comprising:
removing excess material that includes the filter from the casting;
smelting the excess material; and
separating the inert filter material from the smelted excess material.