Author: claimsbot

1. A transistor array panel comprising:
a substrate;
a plurality of first conductive lines and a plurality of second conductive lines arranged on one side of the substrate to cross one another at right angles;
an insulating film interposed between the plurality of first conductive lines and the plurality of second conductive lines;
a plurality of first switching elements provided in intersecting portions between the plurality of first conductive lines and the plurality of second conductive lines on said one side of the substrate, respectively;
a plurality of display electrodes connected to the first switching elements, respectively;
at least one conductive film pattern provided to be electrically insulated from the plurality of first conductive lines, the plurality of second conductive lines and the plurality of display electrodes, and to be overlapped on the display electrodes, thereby forming a storage capacitance between each of the display electrodes and the conductive film pattern;
a protection circuit electrically connected to each of the first conductive lines and the second conductive lines, and disposed in an outer peripheral portion of a display region in which the plurality of first switching elements and the plurality of display electrodes are formed on said one side of the substrate; and
a first common line insulated from the protection circuit, connected to the at least one conductive film pattern, and provided to be insulated from the protection circuit and to be at least partially overlapped on the protection circuit, in the outer peripheral portion of the display region.
2. The transistor array panel according to claim 1, wherein each of the first switching elements has a first thin-film transistor including a first semiconductor layer, a gate electrode, a drain electrode and a source electrode,
the gate electrode of each first thin-film transistor is connected to one of the plurality of first conductive lines,
one of the drain electrode and the source electrode of each first thin-film transistor is connected to one of the plurality of display electrodes, and
the other of the drain electrode and the source electrode of each first thin-film transistor which is not connected to the display electrode is connected to one of the plurality of second conductive lines.
3. The transistor array panel according to claim 2, wherein each of the plurality of first conductive lines is a gate line connected to the gate electrode of each first switching element, and
each of the plurality of second conductive lines is a data line connected to one of the drain electrode and the source electrode of each first switching element.
4. The transistor array panel according to claim 1, wherein the protection circuit includes:
at least one protective line insulated from the plurality of first conductive lines and the plurality of second conductive lines, and disposed to cross the first and second conductive lines at right angles; and
a plurality of protective elements which electrically connect the at least one protective line to the first conductive lines or the second conductive lines, respectively.
5. The transistor array panel according to claim 4, wherein each of the plurality of first switching elements includes a first semiconductor layer,
at least one of the plurality of protective elements is a second thin-film transistor including a second semiconductor layer and a gate electrode, and
said plurality of first semiconductor layers and at least one second semiconductor layer are formed in one step.
6. The transistor array panel according to claim 1, wherein said at least one conductive film pattern and the first common line are formed by patterning one conductive film.
7. A liquid crystal display panel comprising:
(a) a transistor array panel including:
one substrate;
a plurality of gate lines and a plurality of data lines arranged on one side of said one substrate to cross one another;
an insulating film interposed between the plurality of gate lines and the plurality of data lines;
a plurality of first thin-film transistors provided in intersecting portions between the plurality of gate lines and the plurality of data lines on the one side of said one substrate, respectively;
a plurality of pixel electrodes connected to the first thin-film transistors, respectively;
a gate electrode of each first thin-film transistor being connected to one of the plurality of gate lines;
one of a drain electrode and a source electrode of each first thin-film transistor being connected to one of the plurality of pixel electrodes;
the other of the drain electrode and the source electrode which is not connected to the pixel electrode being connected to one of the plurality of data lines;
at least one conductive film pattern formed to be electrically insulated from the plurality of gate lines, the plurality of data lines and the plurality of pixel electrodes, and to be overlapped on the pixel electrodes, thereby forming a storage capacitance between each of the pixel electrodes and the conductive film pattern;
a protection circuit electrically connected to the gate lines and the data lines, and disposed in an outer peripheral portion of a display region in which the plurality of first switching elements and the plurality of pixel electrodes are formed on the one side of said one substrate; and
a first common line insulated from the protection circuit, electrically connected to the at least one conductive film pattern, and provided to be insulated from the protection circuit and to be at least partially overlapped on the protection circuit, in the outer peripheral portion of the display region;
(b) a counter substrate assembly including:
another substrate; and
an electrode formed on one side of said other substrate; and
(c) a liquid crystal hermetically introduced between the transistor array panel and the counter substrate assembly arranged to face each other.
8. The liquid crystal display panel according to claim 7, wherein the protection circuit includes:
at least one protective line insulated from the plurality of gate lines and the plurality of data lines, and disposed to cross the gate lines and the data lines at right angles; and
a plurality of protective elements which connect the at least one protective line to the gate lines or the data lines, respectively.
9. The liquid crystal display panel according to claim 8, wherein each of the plurality of first switching elements includes a first semiconductor layer,
at least one of the plurality of protective elements is a second thin-film transistor including a second semiconductor layer and a gate electrode, and
the plurality of first semiconductor layers and the at least one second semiconductor layer are formed in one step.
10. The liquid crystal display panel according to claim 7, wherein the at least one conductive film pattern and the first common line are formed by patterning one conductive film.
11. A method of manufacturing a liquid crystal display panel, comprising:
preparing one substrate;
forming a plurality of first conductive lines and a plurality of second conductive lines on one side of said one substrate to cross one another at right angles, with an insulating film being sandwiched therebetween;
forming a plurality of first switching elements in intersecting portions between the plurality of first conductive lines and the plurality of second conductive lines on the one side of said one substrate, respectively, and forming a plurality of display electrodes connected to the first switching elements, respectively;
forming at least one conductive film pattern insulated from the plurality of first conductive lines, the plurality of second conductive lines and the plurality of display electrodes, and overlapped on the display electrodes to form a storage capacitance between each of the display electrodes and the conductive film pattern;
forming a protection circuit connected to the first conductive lines and the second conductive lines in an outer peripheral portion of a display region in which the plurality of first switching elements and the plurality of display electrodes are formed on the one side of said one substrate;
forming a first common line insulated from the protection circuit and connected to the at least one conductive film pattern to be insulated from the protection circuit and to be at least partially overlapped on the protection circuit, in the outer peripheral portion of the display region;
preparing another substrate;
forming an electrode on one side of said other substrate;
arranging the one substrate and the other substrate to face each other; and
hermetically introducing a liquid crystal between said one substrate and said other substrate.
12. The method of manufacturing the liquid crystal display panel according to claim 11, wherein each of the first switching elements has a first thin-film transistor including a first semiconductor layer, a gate electrode, a drain electrode and a source electrode, and
the first thin-film transistor is formed so that:
the gate electrode of each first thin-film transistor is connected to one of the plurality of first conductive lines;
one of the drain electrode and the source electrode of each first thin-film transistor is connected to one of the plurality of display electrodes; and
the other of the drain electrode and the source electrode of each first thin-film transistor which is not connected to the display electrode is connected to one of the plurality of second conductive lines.
13. The method of manufacturing the liquid crystal display panel according to claim 12, wherein the first conductive line is a gate line connected to the gate electrode of each first thin-film transistor, and
the second conductive line is a data line connected to one of the drain electrode and the source electrode of each first thin-film transistor.
14. The method of manufacturing the liquid crystal display panel according to claim 11, wherein at least one of the protective elements has a second thin-film transistor including a second semiconductor layer and a gate electrode, and
the gate electrode of the second thin-film transistor is formed to be insulated from the other members having conductivity.
15. The method of manufacturing the liquid crystal display panel according to claim 14, wherein each of the plurality of first switching elements includes a first semiconductor layer, and
the plurality of first semiconductor layers and the at least one second semiconductor layer are formed in one step.
16. The method of manufacturing the liquid crystal display panel according to claim 11, wherein at least one of the plurality of protective elements is a second thin-film transistor including a second semiconductor layer and a gate electrode, and
the gate electrode of the second thin-film transistor is formed to be connected to the gate line.
17. The method of manufacturing the liquid crystal display panel according to claim 16, wherein each of the plurality of first switching elements includes a first semiconductor layer, and
the plurality of first semiconductor layers and the at least one second semiconductor layer are formed in one step.
18. The method of manufacturing the liquid crystal display panel according to claim 11, wherein the at least one conductive film pattern and the first common line are formed by patterning one conductive film.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus, comprising:
a plurality of digital components organized as two or more autonomous power islands;
a programmable counter register associated with at least a selected two of the power islands; and
a power management unit to determine, based on a minimum wakeup wait time value for the power island to transition from a low power state to a full power state stored in the programmable counter register, whether the selected power island has been fully powered up, wherein the programmable counter register is shared by at least two of the plurality of power islands that are powered up at different times, the programmable counter register programmed with a first minimum wakeup time value associated with a first power island prior to requesting that the first power island transition from the low power state to the full power state.
2. The apparatus of claim 1, wherein:
the power management unit is further to selectively control power to at least one of the two or more power islands.
3. The apparatus of claim 1, wherein:
the contents of the programmable counter register may be modified responsive to a user-level instruction during operation of the apparatus.
4. The apparatus of claim 1, wherein:
the contents of the programmable counter register may be modified responsive to an internal microarchitectural instruction during operation of the apparatus.
5. The apparatus of claim 1, wherein: the digital components further comprise at least one execution unit.
6. The apparatus of claim 1, wherein the digital components further comprise: a first processor core and a second processor core.
7. The apparatus of claim 1, wherein the digital components further include:
a communication pathway via which the value in the programmable counter register may be modified.
8. The apparatus of claim 1, further comprising:
a plurality of programmable counter registers, each associated with a different one of the power islands.
9. The apparatus of claim 8, further comprising:
a plurality of comparators, each coupled to one of the programmable counter registers and to the power management unit.
10. The apparatus of claim 9, further comprising:
a plurality of incrementors, each coupled to at least one of the comparators.
11. The apparatus of claim 1, further comprising:
a comparator coupled to the programmable counter register and to the power management unit.
12. The apparatus of claim 11, further comprising:
an incrementor coupled to the comparator.
13. The apparatus of claim 1, wherein:
said power management unit is further to generate an indicator to specify whether the selected power island has fully powered up.
14. The apparatus of claim 1, wherein:
the contents of the programmable counter register may be modified responsive to a supervisor-level instruction during operation of the apparatus.
15. A system comprising:
an antenna; and
a plurality of components coupled to the antenna, wherein said components comprise one or more independent power islands;
at least one electrically autonomous portion of a computing device; and
a power management unit to selectively control power to the portion and to determine, based on a minimum wakeup wait time value for the power island to transition from a low power state to a full power state stored in a programmable counter register, whether the portion has transitioned into a fully-powered state, wherein the programmable counter register is shared by at least two electrically autonomous portions of the computing device that are powered up at different times, the programmable counter register programmed with a first minimum wakeup time value associated with a first portion prior to requesting that the first portion transition from the low power state to the full power state.
16. The system of claim 15, further comprising:
an analog component coupled to the antenna.
17. The system of claim 16, wherein:
said analog component further comprises a camera.
18. The system of claim 15, wherein:
said power management unit is further to generate an indicator to specify whether the portion has transitioned into the fully-powered state.
19. The system of claim 15, further comprising:
a second electrically autonomous portion of the computing device.
20. The system of claim 19, further comprising:
a chip package to include the portion and the second portion.
21. The system of claim 15, wherein:
said portion comprises a processor core.
22. The system of claim 15, further comprising:
a chip package to include the portion.
23. A method comprising:
initializing a programmable register with an initial minimum wakeup wait time value for the power island to transition from a low power state to a full power state stored for a power island;
executing a code sequence;
modifying the value for the programmable register, responsive to one or more instructions of the code sequence;
sharing the programmable register by at least two power islands that are powered up at different times;
prior to applying power to the first power island, storing a first minimum wakeup time value associated with a first power island in the programmable register;
applying power to the power island;
determining, based on the modified value of the programmable register,
whether the power island has completely powered up; and
if so, generating a transition indicator.
24. The method of claim 23, wherein said determining further comprises:
comparing the modified value of the programmable register with a current time value.
25. The method of claim 24, further comprising:
obtaining the current time value from an incrementor.
26. The method of claim 24, further comprising:
generating the indicator based on the comparison of the modified value with the current time value.
27. The method of claim 23, wherein:
the code sequence is a user-provided software sequence.
28. The method of claim 23, wherein: the code sequence is an internal microcode sequence.
29. A machine-accessible medium storing an integrated chip design, the integrated chip comprising:
a plurality of components organized to operate on one of one or more independent power grids, wherein said components are arranged as a plurality of independent power islands;
a programmable counter register associated with at least a first portion of the components; and
a power management unit to determine, based on a minimum wakeup wait time value for the power island to transition from a low power state to a full power state stored in the programmable counter register, whether the first portion has fully powered up, wherein the programmable counter register is shared by at least two of the plurality of power islands that are powered up at different times, the programmable counter register programmed with a first minimum wakeup time value associated with a first power island prior to requesting that the first power island transition from the low power state to the full power state.
30. The machine-accessible medium storing an integrated chip design as recited in claim 29, wherein:
the power unit is further to selectively control power to the first portion.
31. The machine-accessible medium storing an integrated chip design as recited in claim 29, the components further comprising, wherein:
the contents of the programmable counter register may be modified responsive to a user-level instruction during operation of the apparatus.
32. The machine-accessible medium storing an integrated chip design as recited in claim 29, the components further comprising, wherein:
the contents of the programmable counter register may be modified responsive to an internal microarchitectural instruction during operation of the apparatus.
33. The machine-accessible medium storing an integrated chip design as recited in claim 29, wherein:
the components are further designed to comprise at least one execution unit.
34. The machine-accessible medium storing an integrated chip design as recited in claim 29, wherein:
the components are further designed to comprise a first processor core and a second processor core.
35. The machine-accessible medium storing an integrated chip design as recited in claim 29, the components further comprising:
a communication pathway via which the value in the programmable counter register may be modified.
36. The machine-accessible medium storing an integrated chip design as recited in claim 29, the chip further comprising:
a comparator coupled to the programmable counter register and to the power management unit.
37. The machine-accessible medium storing an integrated chip design as recited in claim 29, wherein:
said power management unit is further to generate an indicator to specify whether the first portion has transitioned into a fully-powered state.
38. The machine-accessible medium storing an integrated chip design as recited in claim 28, the chip further comprising:
a plurality of programmable counter registers, each associated with a different one of the power islands.
39. The machine-accessible medium storing an integrated chip design as recited in claim 38, the chip further comprising:
a plurality of comparators, each coupled to one of the programmable counter registers and to the power management unit.
40. The machine-accessible medium storing an integrated chip design as recited in claim 39, the chip further comprising: a plurality of incrementors, each coupled to at least one of the comparators.

1. An operations fluid for use in operations on wells associated with hydrocarbon production, the fluid comprising:
a non-aqueous fluid; and
at least one organo-anionic surfactant.
2. The operations fluid of claim 1, wherein the operations fluid is adapted to perform as a treatment fluid for use during at least one of drilling operations, completion operations, production operations, and injection operations.
3. The operations fluid of claim 2, wherein the treatment fluid is adapted to reduce the elasticity of a NAF filter cake.
4. The operations fluid of claim 1, wherein the organo-anionic surfactant has the general formula:
{R\u2014X}\u2212 +{Y}
wherein R is selected from the group comprising linear and branched alkyl and aryl alkyl hydrocarbon chains, wherein X is an acid selected from the group comprising sulfonic acids, carboxylic acids, phosphoric acids, and mixtures thereof, and wherein Y is an organic amine selected from the group comprising monoethanol amine, diethanol amine, triethanol amine, ethylene diamine, propylene diamine, diethylene tri-amine, tri-ethylene tetra-amine, tetra ethylene pent-amine, dipropylene tri-amine, tripropylene tetra-amine, tetra propylene pentamine, and mixtures thereof.
5. The operations fluid of claim 4, wherein the organo-anionic surfactant is prepared by contacting the acid and the organic amine at temperatures in the range of about \u221250\xb0 C. to about 200\xb0 C.
6. The operations fluid of claim 4, wherein the organo-anionic surfactant is prepared by contacting a neat acid and a neat organic amine, wherein the acid is present relative to the organic amine at least at a molar equivalent.
7. The operations fluid of claim 4, wherein the organic amine is selected from one or more of monoethanol amine, diethanol amine, triethanol amine, and mixtures thereof.
8. The operations fluid of claim 4, wherein the organo-anionic surfactant is present in the non-aqueous fluid at a concentration greater than about 0.01 wt % and less than about 12.0 wt % based on non-aqueous fluid in the operations fluid.
9. The operations fluid of claim 8, wherein the organo-anionic surfactant is present in the non-aqueous fluid at a concentration greater than about 0.01 wt % and less than about 3.0 wt %.
10. The operations fluid of claim 4, wherein the organo-anionic surfactant is selected from the group comprising monoethanol ammonium alkyl aromatic sulfonic acid, monoethanol ammonium alkyl carboxylic acid, and mixtures thereof.
11. The operations fluid of claim 10, wherein the alkyl group of the acid has a length ranging from about 6 carbon atoms to about 18 carbon atoms.
12. The operations fluid of claim 10, wherein the alkyl group of the acid has a length ranging from about 10 carbon atoms to about 14 carbon atoms.
13. The operations fluid of claim 10, wherein the alkyl group of R is an alkyl chain of length at least substantially equal to a hydrocarbon chain length in a non-aqueous fluid in a filter cake formed during operation of a well.
14. A method of remediating a NAF filter cake in a well, the method comprising:
obtaining an operations fluid comprising an organo-anionic surfactant in a non-aqueous fluid;
pumping a volume of the operations fluid into a well including a NAF filter cake, wherein the volume of operations fluid is pumped to contact the NAF filter cake.
15. The method of claim 14, wherein the NAF filter cake is disposed on at least one of a fracture face, a sand screen, gravel pack components, and a wellbore wall.
16. The method of claim 14, wherein the remediation method is applied during at least one of clean-up operations and workover operations to reduce an effective skin effect caused by the NAF filter cake.
17. The method of claim 14, wherein the volume of the operations fluid is applied during at least one of drilling operations, completion operations, production operations, and injection operations.
18. The method of claim 17, wherein the well includes an open hole segment, wherein the NAF filter cake is formed on a wellbore wall in the open hole segment, and wherein the operations fluid is applied to the open hole segment.
19. The method of claim 17, wherein the well includes sand control equipment, wherein the NAF filter cake is formed on at least one component of the sand control equipment, and wherein the operations fluid is applied to contact the at least one component of the sand control equipment.
20. The method of claim 14, wherein the organo-anionic surfactant has the general formula:
{R\u2014X}\u2212 +{Y}
wherein R is selected from the group comprising linear and branched alkyl and aryl alkyl hydrocarbon chains, wherein X is an acid selected from the group comprising sulfonic acids, carboxylic acids, phosphoric acids, and mixtures thereof, and wherein Y is an organic amine selected from the group comprising monoethanol amine, diethanol amine, triethanol amine, ethylene diamine, propylene diamine, diethylene tri-amine, tri-ethylene tetra-amine, tetra ethylene pent-amine, dipropylene tri-amine, tripropylene tetra-amine, tetra propylene pentamine, and mixtures thereof.
21. The method of claim 20, wherein the organo-anionic surfactant is prepared by contacting a neat organic acid and a neat organic amine, wherein the organic acid is present relative to the organic amine at least at a molar equivalent.
22. The method of claim 20, wherein the organo-anionic surfactant is present in the non-aqueous fluid at a concentration greater than about 0.01 wt % and less than about 12.0 wt % based on non-aqueous fluid in the operations fluid.
23. The method of claim 22, wherein the organo-anionic surfactant is present at a concentration greater than about 0.01 wt % and less than about 3.0 wt %.
24. The method of claim 20, wherein the organo-anionic surfactant is selected from the group comprising monoethanol ammonium alkyl aromatic sulfonic acid, monoethanol ammonium alkyl carboxylic acid, and mixtures thereof.
25. The method of claim 24, wherein the alkyl group of R is an alkyl chain of length at least substantially equal to a hydrocarbon chain length in a non-aqueous fluid in the NAF filter cake.
26. A method of producing hydrocarbons from a well, the method comprising:
drilling through a formation using a NAF-based drilling fluid to form a well, wherein a NAF filter cake is formed on at least one component of the well;
treating the at least one component of the well with an operations fluid comprising an organo-anionic surfactant in a non-aqueous fluid to remediate the NAF filter cake; and
producing hydrocarbons through the well.
27. The method of claim 26, wherein the organo-anionic surfactant has the general formula:
{R\u2014X}\u2212 +{Y}
wherein R is selected from the group comprising linear and branched alkyl and aryl alkyl hydrocarbon chains, wherein X is an acid selected from the group comprising sulfonic acids, carboxylic acids, phosphoric acids, and mixtures thereof, and wherein Y is an organic amine selected from the group comprising monoethanol amine, diethanol amine, triethanol amine, ethylene diamine, propylene diamine, diethylene tri-amine, tri-ethylene tetra-amine, tetra ethylene pent-amine, dipropylene tri-amine, tripropylene tetra-amine, tetra propylene pentamine, and mixtures thereof.
28. The method of claim 26, wherein the operations fluid is mixed with the drilling fluid to alter one or more properties of the NAF filter cake.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An adaptive method for applying chirp to an optical signal traversing through an optical network, comprising:
applying chirp to an optical data signal at a transmitter in the optical network;
transmitting the optical data signal through the optical network, the optical data signal having error detection data embedded therein;
optimizing data recovery from the optical data signal at an egress point of the optical network prior to determining an error rate for the optical data signal;
determining the error rate for the optical data signal at the egress point of the optical network, where the error rate is based on the error detection data embedded in the optical data signal;
transmitting the error rate for the optical data signal to the transmitter; and
adjusting the chirp being applied to the optical data signal at the transmitter based on the error rate for the optical data signal.
2. The method of claim 1 wherein the step of applying chirp to an optical data signal further comprises using an external phase modulator.
3. The method of claim 1 wherein the step of applying chirp to an optical data signal further comprises dithering amplitude of the chirp applied to the optical data signal.
4. The method of claim 3 wherein the step of adjusting the chirp further comprises using feedback error control to minimize the error rate detected at the egress point.
5. The method of claim 1 wherein the step of applying chirp to an optical data signal further comprises dithering phase of the chirp applied to the optical data signal.
6. The method of claim 5 wherein the step of adjusting the chirp further comprises minimizing the error rate detected at the egress point through the use of feedback error control.
7. The method of claim 1 wherein the step of determining an error rate further comprises deriving the error rate from the number of corrected errors in a forward error correction scheme.
8. The method of claim 1 wherein the step of transmitting the error rate for the optical data signal further comprises using an optical supervisory channel to transmit the error rate.
9. An adaptive method for applying chirp to an optical signal traversing through an optical network, comprising:
applying chirp to an optical data signal at a transmitter in the optical network, the optical data signal having error detection data embedded therein;
dithering one of amplitude and phase of the chirp being applied to the optical data signal;
optimizing data recovery from the optical data signal at an egress point of the optical network;
determining an error rate for the optical data signal at the egress point of the optical network, where the error rate is based on the error detection data embedded in the optical data signal;
transmitting the error rate for the optical data signal to the transmitter; and
adjusting the chirp being applied to the optical data signal at the transmitter based on the error rate for the optical data signal
dithering the other of amplitude and phase of the chirp being applied to the optical data signal;
optimizing data recovery from the optical data signal at the egress point of the optical network;
determining an error rate for the optical data signal at the egress point of the optical network;
transmitting the error rate for the optical data signal to the transmitter; and
adjusting the chirp being applied to the optical data signal at the transmitter based on the error rate for the optical data signal.
10. The method of claim 9 wherein the step of transmitting the error rate for the optical data signal further comprises using an optical supervisory channel to transmit the error rate.
11. The method of claim 9 wherein the step of adjusting the chirp further comprises using feedback error control to minimize the error rate detected at the egress point.