Author: claimsbot

1. An information processor comprising:
a storage module configured to store a plurality of pieces of setting information of a plurality of operation modes, respectively, corresponding to a basic inputoutput system (BIOS) setup item;
a setting module configured to acquire one of the pieces of setting information of selected one of the operation modes from the storage module during power on self-test (POST) process by a BIOS, to set the one of the pieces of the setting information to the BIOS during the POST process, and to perform a process corresponding to the set one of the pieces of the setting information during the POST process; and
an input module configured to receive a save request for saving the one of the pieces of the setting information set by the setting module and a restart request for restarting the information processor, wherein
the storage module is configured to store therein, during the POST process, the one of the pieces of the setting information according to the save request so that the one of the operation modes associated with the one of the pieces of the setting information is enabled when the information processor is not in operation, and
the setting module is configured to stop performing the process during the POST process when the input module receives the restart request.
2. The information processor of claim 1, wherein
the operation modes differ from each other and are capable of operating different external devices in different states,
during the POST process by the BIOS, the setting module is configured to acquire the one of the pieces of the setting information of the selected one of the operation modes from the storage module, to set the acquired one of the pieces of the setting information to the BIOS, and to operate the external device in a state corresponding to the acquired one of the operation modes.
3. The information processor of claim 2, further comprising:
the input module configured to receive a setting request of the acquired one of the operation modes, and wherein
the setting module is configured to operate, upon receipt of the setting request of the acquired one of the operation modes by the input module, the device in a state corresponding to the acquired one of the operation modes.
4. An information processor comprising:
an executing module configured to charge one of a plurality of external devices connected to the information processor by one of a plurality of charging modes for charging the external devices, respectively, when the operating system is not in operation, wherein the charging modes comprise at least a first charging mode for charging one of the external devices configured to be charged when a predetermined voltage is applied and a second charging mode for charging other one of the external devices configured to be charged when a signal with a predetermined waveform is applied;
a charging module configured to charge one of the external devices connected to the information processor when the information processor is not in operation; and
a setting module configured to set, when an operating system is not in operation, one of the first charging mode and the second charging mode used by the executing module to the charging module so that the one of the first charging mode and the second charging mode is enabled when the information processor is not in operation, the one of the first charging mode and the second charging mode being capable of charging at least one of the external devices connected to the information processor.
5. An information processor comprising:
a storage module configured to store a plurality of charging modes capable of charging a plurality of external devices, respectively;
an input module configured to receive, when an operating system is not in operation, a selection request for selecting one of the charging modes;
an executing module configured to acquire, upon receipt of the selection request, one of the charging modes from the storage module, and to charge, when the operating system is not in operation, one of the external devices connected to the information processor by the one of the charging modes;
a charging module configured to charge, when the information processor is not in operation, one of the external devices connected to the information processor; and
a setting module configured to set the one of the charging modes used by the executing module to the charging module so that the one of the charging modes is enabled when the information processor is not in operation, wherein
the input module is further configured to receive a restart request for restarting the information processor and a save request for saving the one of the charging modes used by the executing module to charge the one of the external devices,
the storage module is configured to save the one of the charging modes in the save request when the input module receives the save request so that the saved one of the charging modes is enabled when the information processor is not in operation, and
the executing module is configured to stop charging the one of the external devices by the one of the charging modes when the input module receives the restart request while the operating system is not in operation.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method, comprising:
identifying a first plurality of memory circuits comprising at least one memory circuit of a second plurality of memory circuits that is not currently being accessed; and
in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit of the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank.
2. A sub-system, comprising:
a component in communication with a plurality of memory circuits and a system, the component operable to initiate a power saving operation in association with at least one of the plurality of memory circuits that is not accessed by the system;
wherein the plurality of memory circuits is a rank.
3. A method of managing power in an electronic system including a memory, the memory including a first plurality of memory circuits, the method comprising:
identifying the first plurality of memory circuits comprising at least one memory circuit of a second plurality of memory circuits that is not currently being accessed; and
in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit of the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank.
4. The method of claim 3, wherein the power saving operation comprises:
a power down operation.
5. The method of claim 4, wherein the power down operation comprises:
a precharge power down operation.
6. The method of claim 3, wherein the at least one memory circuit has a clock enable input, the method further comprising:
initiating the power saving operation by utilizing the clock enable input of the at least one memory circuit.
7. The method of claim 6, wherein utilizing the clock enable input comprises:
de-asserting the clock enable input of the at least one memory circuit.
8. The method of claim 6, wherein the identifying comprises:
determining whether a page is being accessed in at least one of the plurality of memory circuits.
9. The method of claim 3, wherein the system further includes a component, and wherein:
at least one of the identifying and the initiating is carried out utilizing the component.
10. The method of claim 9, wherein the component includes an advanced memory buffer (AMB).
11. The method of claim 9, wherein the component includes a circuit that is positioned on a dual in-line memory module (DIMM).
12. The method of claim 9, wherein the component includes a memory controller.
13. The method of claim 9, wherein the component includes a register.
14. The method of claim 3, wherein the memory includes a number (x) of the memory circuits, the method further comprising:
continuously subjecting a lesser number of the memory circuits to the power saving operation.
15. The method of claim 14, wherein the lesser number comprises x\u22121.
16. The method of claim 3, wherein the system further includes an interface circuit coupled to interface the plurality of memory circuits and the system, and wherein:
at least one of the identifying and the initiating is carried out utilizing the interface circuit.
17. The method of claim 3, wherein the memory circuits each includes dynamic random access memory (DRAM).
18. The method of claim 17, wherein the DRAM of each of the memory circuits each comprises a monolithic DRAM.
19. The method of claim 18, wherein the memory circuits are stacked.
20. The method of claim 18, wherein the memory circuits and the interface circuit are, stacked.
21. An apparatus for use with an electronic system, the apparatus comprising:
a first plurality of memory circuits; and
a component in communication with the first plurality of memory circuits and the system, the component operable to initiate a power savings operation in association with at least one memory circuit of a second plurality of memory circuits that is not accessed by the system, the first plurality of memory circuits including the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank.
22. A method of operating a system, the system including a memory including \u201cx\u201d memory circuits, the method comprising:
accessing \u201cp\u201d of the memory circuits;
while the \u201cp\u201d memory circuits are being accessed, performing a power saving operation on \u201cq\u201d others of the memory circuits;
wherein \u201cp\u201d+\u201cq\u201d<=\u201cx\u201d;
wherein the \u201cx\u201d memory circuits is a rank.
23. The method of claim 22, wherein performing the power saving operation comprises:
de-asserting a clock enable input of the \u201cq\u201d memory circuits.
24. The method of claim 1, wherein initiating the power saving operation utilizes a clock enable input of the at least one memory circuit.
25. A method, comprising:
identifying one or more portions of at least one of a plurality of memory circuits that is not currently being accessed, the plurality of memory circuits being at least part of a rank; and
in response to the identification of the one or more portions of the at least one memory circuit, initiating a power saving operation in association with the one or more portions of the at least one memory circuit.
26. An apparatus comprising:
a first plurality of memory circuits; and
a component in communication with the first plurality of memory circuits and a system, the component operable to initiate a power saving operation in association with at least one memory circuit of a second plurality of memory circuits that is not accessed by the system, the first plurality of memory circuits including the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank;
wherein the component includes a circuit that is positioned on a dual in-line memory module (DIMM).
27. A method of managing power in an electronic system including a memory, the memory including a first plurality of memory circuits, the method comprising:
identifying the first plurality of memory circuits comprising at least one memory circuit of a second plurality of memory circuits that is not currently being accessed; and
in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit of the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank;
wherein the system further includes a component, and at least one of the identifying and the initiating is carried out utilizing the component;
wherein the component includes a register.

1. A solid-state imaging device comprising:
an imaging element that includes a first semiconductor substrate, a first wiring layer that is formed on a surface of the first semiconductor substrate, and a first metal layer that is formed on an upper portion of the first wiring layer, in which a pixel region which is a light sensing surface is formed on a rear surface side of the first semiconductor substrate; and
a logic element that includes a second semiconductor substrate, a second wiring layer that is formed on a surface of the second semiconductor substrate, and a second metal layer that is formed on an upper portion of the second wiring layer, a signal processing circuit that processes a pixel signal obtained at the pixel region is formed in the logic element, and the logic element is laminated to the imaging element so that the first metal layer and the second metal layer are bonded to each other,
wherein the first metal layer and the second metal layer are formed on a region excluding a region in which a penetrating electrode layer penetrating a bonding surface of the imaging element and the logic element is formed.
2. The solid-state imaging device according to claim 1, further comprising:
a first insulating portion including an insulating material that is formed on a predetermined region of the same layer as the first metal layer;
a second insulating portion including an insulating material that is formed on a region which contacts the first insulating portion in a predetermined region of the same layer as the second metal layer; and
a penetrating electrode layer that penetrates the first insulating portion and the second insulating portion.
3. The solid-state imaging device according to claim 1,
wherein the first metal layer and the second metal layer are connected to ground potential.
4. The solid-state imaging device according to claim 2,
wherein the penetrating electrode layer is exposed to a light sensing surface side of the imaging element.
5. The solid-state imaging device according to claim 1,
wherein the first metal layer andor the second metal layer is a laminated structure including different metal materials.
6. The solid-state imaging device according to claim 1,
wherein the first metal layer is formed on an upper portion of the first wiring layer via a barrier metal layer including ferromagnetic.
7. The solid-state imaging device according to claim 1,
wherein the second metal layer is formed on an upper portion of the second wiring layer via a barrier metal layer including a ferromagnetic body.
8. A semiconductor device comprising:
a first semiconductor element that includes a first semiconductor substrate, a first wiring layer that is formed on a surface of the first semiconductor substrate, and a first metal layer that is formed on an upper portion of the first wiring layer, in which a first semiconductor integrated circuit is formed; and
a second semiconductor element that includes a second semiconductor substrate, a second wiring layer that is formed on a surface of the second semiconductor substrate, and a second metal layer that is formed on an upper portion of the second wiring layer, a second semiconductor integrated circuit is formed in the second semiconductor element, and the second semiconductor element is laminated to the first semiconductor element so that the first metal layer and the second metal layer are bonded to each other,
wherein the first metal layer and the second metal layer are formed on a region excluding a region in which a penetrating electrode layer penetrating a bonding surface of the first semiconductor element and the second semiconductor element is formed.
9. The semiconductor device according to claim 8, further comprising:
a first insulating portion including an insulating material that is formed on a predetermined region of the same layer as the first metal layer;
a second insulating portion including an insulating material that is formed on a region which contacts the first insulating portion in a predetermined region of the same layer as the second metal layer; and
a penetrating electrode layer that penetrates the first insulating portion and the second insulating portion.
10. A manufacturing method of a solid-state imaging device comprising:
forming a first wiring layer on a surface of a first semiconductor substrate, forming a first metal layer in which a surface is exposed on an upper portion of the first wiring layer, and forming an imaging element including a pixel region;
forming a second wiring layer on a surface of a second semiconductor substrate, forming a second metal layer in which a surface is exposed on an upper portion of the second wiring layer, and forming a logic element having a signal processing circuit which processes a signal charge generated at the pixel region; and
laminating the imaging element and the logic element so that the first metal layer and the second metal layer are bonded to each other,
wherein the first metal layer and the second metal layer are formed on a region excluding a region in which a penetrating electrode layer penetrating a bonding surface of the imaging element and the logic element is formed.
11. The manufacturing method of a solid-state imaging device according to claim 10, further comprising:
forming a convex first insulating portion on a predetermined region of an upper portion of the first wiring layer on the first semiconductor substrate before forming the first metal layer;
forming the first metal layer by embedding a metal material so as to be the same height as the surface of the first insulating portion on an upper portion of the first wiring layer in which the first insulating portion is not formed after forming the first insulating portion;
forming a convex second insulating portion on a predetermined region of an upper portion of the second wiring layer on the second semiconductor substrate before forming the second metal layer;
forming the second metal layer by embedding a metal material so as to be the same height as the surface of the second insulating portion on an upper portion of the second wiring layer in which the second insulating portion is not formed after forming the second insulating portion; and
laminating the imaging element and the logic element so that the first metal layer and the second metal layer are bonded to each other and the first insulating portion and the second insulating portion are bonded to each other when the imaging element and the logic element are laminated.
12. The manufacturing method of a solid-state imaging device according to claim 11, further comprising:
forming a penetrating electrode layer which penetrates the first insulating portion and the second insulating portion from a surface of the imaging element or the logic element after laminating the imaging element and the logic element.
13. The manufacturing method of a solid-state imaging device according to claim 11, further comprising:
forming a penetrating electrode layer which penetrates to a predetermined depth from a surface of the first insulating portion in the imaging element before laminating the imaging element and the logic element;
forming a penetrating electrode layer which penetrates to a predetermined depth from a surface of the second insulating portion in the logic element; and
connecting a penetrating electrode layer formed on the imaging element and a penetrating electrode layer formed on the logic element when laminating the imaging element and the logic element.
14. The manufacturing method of a solid-state imaging device according to claim 10,
wherein the first metal layer and the second metal layer are formed by an electrolytic plating method.
15. A manufacturing method of a semiconductor device comprising:
forming a first wiring layer on a surface of a first semiconductor substrate, forming a first metal layer in which a surface is exposed on an upper portion of the first wiring layer, and forming a first semiconductor element including a first semiconductor integrated circuit;
forming a second wiring layer on a surface of a second semiconductor substrate, forming a second metal layer in which a surface is exposed on an upper portion of the second wiring layer, and forming a second semiconductor element including a second semiconductor integrated circuit; and
laminating the first semiconductor element and the second semiconductor element so that the first metal layer and the second metal layer are bonded to each other,
wherein the first metal layer and the second metal layer are formed on a region excluding a region in which a penetrating electrode layer penetrating a bonding surface of the first semiconductor element and the second semiconductor is formed.
16. The manufacturing method of a semiconductor device according to claim 15, further comprising:
forming a convex first insulating portion on a predetermined region of an upper portion of the first wiring layer on the first semiconductor substrate before forming the first metal layer;
forming the first metal layer by embedding a metal material so as to be the same height as the surface of the first insulating portion on an upper portion of the first wiring layer in which the first insulating portion is not formed after forming the first insulating portion;
forming a convex second insulating portion on a predetermined region of an upper portion of the second wiring layer on the second semiconductor substrate before forming the second metal layer;
forming the second metal layer by embedding a metal material so as to be the same height as the surface of the second insulating portion on an upper portion of the second wiring layer in which the second insulating portion is not formed after forming the second insulating portion; and
laminating the first semiconductor element and the second semiconductor element so that the first metal layer and the second metal layer are bonded to each other and the first insulating portion and the second insulating portion are bonded to each other when the first semiconductor element and the second semiconductor element are laminated.
17. The manufacturing method of a semiconductor device according to claim 16, further comprising:
forming a penetrating electrode layer which penetrates the first insulating portion and the second insulating portion from a surface of the first semiconductor element or the second semiconductor element after laminating the first semiconductor element and the second semiconductor element.
18. The manufacturing method of a semiconductor device according to claim 16, further comprising:
forming a penetrating electrode layer which penetrates to a predetermined depth from a surface of the first insulating portion in the first semiconductor element before laminating the first semiconductor element and the second semiconductor element;
forming a penetrating electrode layer which penetrates to a predetermined depth from a surface of the second insulating portion in the second semiconductor element; and
connecting a penetrating electrode layer formed on the first semiconductor element and a penetrating electrode layer formed on the second semiconductor element when laminating the first semiconductor element and the second semiconductor element.
19. The manufacturing method of a semiconductor device according to claim 15,
wherein the first metal layer and the second metal layer are formed by an electrolytic plating method.
20. An electronic apparatus comprising:
an optical lens;
a solid-state imaging device into which light is focused to the optical lens is incident; and
a signal processing circuit that processes an output signal output from the solid-state imaging device,
wherein the solid-state imaging device includes an imaging element that includes a first semiconductor substrate, a first wiring layer that is formed on a surface of the first semiconductor substrate, and a first metal layer that is formed on an upper portion of the first wiring layer, in which a pixel region which is a light sensing surface is formed on a rear surface side of the first semiconductor substrate, and a logic element that includes a second semiconductor substrate, a second wiring layer that is formed on a surface of the second semiconductor substrate, and a second metal layer that is formed on an upper portion of the second wiring layer, a signal processing circuit that processes a pixel signal obtained at the pixel region is formed in the logic element, and the logic element is laminated to the imaging element so that the first metal layer and the second metal layer are bonded to each other, in which the first metal layer and the second metal layer are formed on a region excluding a region in which a penetrating electrode layer penetrating a bonding surface of the imaging element and the logic element is formed.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A device for generating hydrogen from a water vapor containing exhaust, said device comprising an exhaust diverter and a hydrogen generation section, wherein:
said exhaust diverter is configured to divert a portion of said exhaust and deliver said diverted exhaust to said hydrogen generation section;
said hydrogen generation section comprises an electrolysis unit defining a hermetically sealed void volume configured to accumulate and store hydrogen generated by said electrolysis unit; and
said hydrogen generation section is configured to deliver said hydrogen at a hydrogen output of said electrolysis unit.
2. A device as claimed in claim 1 wherein said void volume is characterized by a volumetric capacity of about 0.01 mL per square centimeter of electrolysis unit cell area at a pressure of about 300 psi (2100 kPa).
3. A device as claimed in claim 1 wherein said void volume is characterized by a volumetric capacity of about 0.2 mL per square centimeter of electrolysis unit cell area at a pressure of about 50 psi (2100 kPa).
4. A device as claimed in claim 1 wherein said void volume is characterized by a volumetric capacity of between about 0.01 mL and about 10 mL per square centimeter of electrolysis unit cell area at pressures of between about 5 psi (35 kPa) and about 1500 psi (10,500 kPa).
5. A device as claimed in claim 1 wherein said hydrogen generation further comprises a pressure monitor configured to monitor said accumulation and storage of hydrogen within said void volume.
6. A device as claimed in claim 1 wherein said hydrogen generation section comprises at least one hydrogen injector configured to control release of hydrogen stored within said void volume.
7. A device as claimed in claim 1 wherein said device further comprises a controller configured to monitor accumulation and storage of hydrogen in said void volume.
8. A device as claimed in claim 7 wherein monitoring of said accumulation and storage of hydrogen is enabled through a pressure monitor in communication with said controller.
9. A device as claimed in claim 8 wherein said pressure monitor is configured to monitor pressure of said hermetically sealed void volume.
10. A device as claimed in claim 1 wherein said electrolysis unit comprises an external box type manifold on an exhaust input side of said electrolysis unit.
11. A device as claimed in claim 10 wherein a width dimension of said electrolysis unit, defined along said external box type manifold is at least twice as large as a length dimension of said electrolysis unit, defined between said exhaust input side and an exhaust output side of said electrolysis unit.
12. A device as claimed in claim 10 wherein flow field grooves defined by said electrolysis unit extend at least as far as said external box type manifold.
13. A device as claimed in claim 10 wherein said external box type manifold is tapered from a maximum cross sectional area at an input side of said manifold to a minimum cross sectional area at an output side of said manifold.
14. A device as claimed in claim 1 wherein said electrolysis unit is thermally coupled to an exhaust duct carrying said exhaust.
15. A device as claimed in claim 1 wherein said hydrogen generation section is configured to return an oxygen-enriched exhaust to a non-diverted portion of said exhaust.
16. A device as claimed in claim 1 wherein said electrolysis unit is configured to generate a substantial amount of hydrogen from a diverted exhaust characterized by a fractional relative humidity of about 1 to about 3 percent.
17. A device as claimed in claim 1 wherein said hydrogen generation section comprises an electrolysis unit configured to generate a substantial amount of hydrogen from a diverted exhaust characterized by a fractional relative humidity of about 3% at about 125 C.
18. A device as claimed in claim 1 wherein said hydrogen generation section comprises an electrolysis unit configured to generate a substantial amount of hydrogen from a diverted exhaust characterized by a fractional relative humidity of about 80% at about 92 C.
19. A device as claimed in claim 1 wherein said hydrogen generation section is configured to deliver substantially pure hydrogen at said hydrogen output of said electrolysis unit.
20. A device as claimed in claim 1 wherein:
said device comprises an engine configured to generate torque; and
said engine generates said exhaust.
21. A device as claimed in claim 20 wherein said engine comprises a diesel engine.
22. A device as claimed in claim 20 wherein said engine is configured such that said exhaust is characterized by an oxygen content of about 1 to about 20 percent, by weight.
23. A device as claimed in claim 1 wherein said device comprises:
a vehicle body; and
an engine configured to generate said exhaust and sufficient torque to accelerate said vehicle body.
24. A device as claimed in claim 23 wherein said device comprises a controller configured to deactivate said exhaust diverter where said vehicle body decelerates.
25. A device for generating hydrogen from a water vapor containing exhaust, said device comprising an exhaust diverter and a hydrogen generation section, wherein:
said exhaust diverter is configured to divert a portion of said exhaust to said hydrogen generation section;
said exhaust diverter is in communication with a heat exchanger configured to increase fractional relative humidity of a portion of said diverted exhaust by cooling said diverted exhaust;
said hydrogen generation section comprises an electrolysis unit configured to generate hydrogen from said diverted exhaust; and
said hydrogen generation section is configured to deliver said hydrogen at a hydrogen output of said electrolysis unit.
26. A device as claimed in claim 25 wherein said heat exchanger is configured increase said fractional relative humidity to at least about 70%.
27. A device as claimed in claim 25 wherein said heat exchanger is configured increase said fractional relative humidity by at least a factor of two.
28. A device as claimed in claim 25 wherein said heat exchanger comprises an air-to-air heat exchanger.
29. A device as claimed in claim 25 wherein said diverted portion of said exhaust comprises less than about 25% of said exhaust.
30. A device as claimed in claim 25 further comprising a semi-permeable membrane configured to extract or concentrate water in said diverted exhaust.
31. A device as claimed in claim 25 further comprising a condensation unit configured to extract or concentrate water in said diverted exhaust.
32. A device comprising an engine configured to generate torque and a nitrogen oxide containing exhaust, at least one peripheral system, and a NOx removal system for removing nitrogen oxides from said nitrogen oxide containing exhaust, said NOx removal system comprising a NOx treatment section, an exhaust diverter, and a hydrogen generation section, wherein:
said NOx treatment section is configured to remove nitrogen oxides from said exhaust;
said exhaust diverter is configured to divert a portion of said exhaust to said hydrogen generation section;
said hydrogen generation section is configured to deliver hydrogen to said NOx treatment section;
said hydrogen generation section is configured to generate oxygen as a byproduct of hydrogen generation and deliver said oxygen with said diverted exhaust to said peripheral system.
33. A device as claimed in claim 32 wherein said peripheral system comprises a fuel injection system of said engine.
34. A device as claimed in claim 32 wherein said peripheral system comprises an engine cooling system.
35. A device as claimed in claim 32 wherein said peripheral system comprises a suspension system.
36. A device as claimed in claim 32 wherein said peripheral system comprises a gaseous filter regeneration system.
37. A device as claimed in claim 32 wherein said peripheral system comprises a hydrogen storage system.
38. A device as claimed in claim 37 wherein said hydrogen storage system comprises hydrogen dispensing hardware.