1. A boosting circuit, comprising:
a first capacitor connected between a first node and a second node;
a second capacitor connected between a third node and a fourth node;
a third capacitor connected between a first boosted voltage output node and a third power source;
a fourth capacitor connected between a second boosted voltage output node and the third power source;
a first switch which selectively connects or disconnects a fourth power source and the first node in response to a logic state of a first control signal;
a second switch which selectively connects or disconnects the fourth power source and the third node in response to a logic state of a second control signal;
a third switch which selectively connects or disconnects the third power source and the third node in response to a logic state of a third control signal;
a fourth switch which selectively connects or disconnects the first node and the first boosted voltage output node in response to a logic state of a fourth control signal;
a fifth switch which selectively connects or disconnects the first node and a first power source in response to a logic state of a fifth control signal;
a sixth switch which selectively connects or disconnects the first node and the third node in response to a logic state of a sixth control signal;
a seventh switch which selectively connects or disconnects the third node and the first boosted voltage output node in response to a logic state of a seventh control signal;
an eighth switch which selectively connects or disconnects the second node and the first power source in response to a logic state of an eighth control signal;
a ninth switch which selectively connects or disconnects the second node and the third power source in response to a logic state of a ninth control signal;
a tenth switch which selectively connects or disconnects the fourth node and the first power source in response to a logic state of a tenth control signal;
an eleventh switch which selectively connects or disconnects the fourth node and the third power source in response to a logic state of an eleventh control signal;
a twelfth switch which selectively connects or disconnects the fourth node and a second power source in response to a logic state of a twelfth control signal;
a thirteenth switch which selectively connects or disconnects the fourth node and the second boosted voltage output node in response to a logic state of a thirteenth control signal; and
a fourteenth switch which selectively connects or disconnects the second node and the second boosted voltage output node in response to a logic state of a fourteenth control signal.
2. The boosting circuit according to claim 1, wherein the switches are formed using metal-oxide-semiconductor field effect transistors (MOSFETs).
3. The boosting circuit according to claim 1, wherein each of the boosted voltage output nodes outputs boosted voltages under two-phase control of the control signals.
4. The boosting circuit according to claim 1, wherein the first boosted voltage output node and the second boosted voltage output node output three boosted positive voltages and three boosted negative voltages in response to the control signals, respectively.
5. A boosting circuit, comprising:
a first capacitor connected between a first node and a second node;
a second capacitor connected between a third node and a fourth node;
a third capacitor connected between a boosted voltage output node and a third power source;
a first switch which selectively connects or disconnects the first node and a first power source in response to a logic state of a first control signal;
a second switch which selectively connects or disconnects the first node and the third node in response to a logic state of a second control signal;
a third switch which selectively connects or disconnects the third node and the boosted voltage output node in response to a logic state of a third control signal;
a fourth switch which selectively connects or disconnects the first node and the boosted voltage output node in response to a logic state of a fourth control signal;
a fifth switch which selectively connects or disconnects the second node and the first power source in response to a logic state of a fifth control signal;
a sixth switch which selectively connects or disconnects the second node and the third power source in response to a logic state of a sixth control signal;
a seventh switch which selectively connects or disconnects the fourth node and the first power source in response to a logic state of a seventh control signal;
an eighth switch which selectively connects or disconnects the fourth node and a second power source in response to a logic state of an eighth control signal; and
a ninth switch which selectively connects or disconnects the fourth node and the third power source in response to a logic state of a ninth control signal.
6. The boosting circuit according to claim 5, wherein the switches are formed using metal-oxide-semiconductor field effect transistors (MOSFETs).
7. The boosting circuit according to claim 5, wherein each of the boosted voltage output nodes outputs boosted voltages under two-phase control of the control signals.
8. The boosting circuit according to claim 5, wherein the boosted voltage output node outputs three boosted voltages in response to the control signals.
9. A boosting circuit, comprising:
a first capacitor connected between a first node and a second node;
a second capacitor connected between a third node and a fourth node;
a third capacitor connected between a boosted voltage output node and a third power source;
a first switch which selectively connects or disconnects the first node and the third power source in response to a logic state of a first control signal;
a second switch which selectively connects or disconnects the first node and the third node in response to a logic state of a second control signal;
a third switch which selectively connects or disconnects the third node and the boosted voltage output node in response to a logic state of a third control signal;
a fourth switch which selectively connects or disconnects the first node and the boosted voltage output node in response to a logic state of a fourth control signal;
a fifth switch which selectively connects or disconnects the second node and the third power source in response to a logic state of a fifth control signal;
a sixth switch which selectively connects or disconnects the second node and a first power source in response to a logic state of a sixth control signal;
a seventh switch which selectively connects or disconnects the second node and a second power source in response to a logic state of a seventh control signal;
an eighth switch which selectively connects or disconnects the fourth node and the third power source in response to a logic state of an eighth control signal;
a ninth switch which selectively connects or disconnects the fourth node and the second power source in response to a logic state of a ninth control signal; and
a tenth switch which selectively connects or disconnects the fourth node and the first power source in response to a logic state of a tenth control signal.
10. The boosting circuit according to claim 9, wherein the switches are formed using metal-oxide-semiconductor field effect transistors (MOSFETs).
11. The boosting circuit according to claim 9, wherein each of the boosted voltage output nodes outputs boosted voltages under two-phase control of the control signals.
12. The boosting circuit according to claim 9, wherein the boosted voltage output node outputs three boosted voltages in response to the control signals.
13. A boosting power supply unit, comprising:
a phase control signal generator which outputs a phase control signal having one of a two-phase pulse form and a logic state value form in response to each of four logic combinations of a first enable signal and a second enable signal;
a switch control signal generator which generates and outputs two-phase step-down switch control signals corresponding to a mode signal in a first logic state of the phase control signal, and generates and outputs two-phase step-up switch control signals corresponding to the mode signal in a second logic state of the phase control signal; and
a boosting circuit which outputs boosted negative voltages by means of capacitors subjected to two-phase control of the step-down switch control signals, and outputs boosted positive voltages by means of capacitors subjected to two-phase control of the step-up switch control signals.
14. The boosting power supply unit according to claim 13, wherein the first enable signal and the second enable signal are digital signals having different logic states with respect to above and below a threshold amount of power in response to amounts of power consumed in loads connected to the boosted positive voltage and the boosted negative voltage, respectively.
15. The boosting power supply unit according to claim 13, wherein when both of the first enable signal and the second enable signal have a first logic state, at least one signal of the step-down switch control signals and at least one signal of the step-up switch control signals are not activated.
16. The boosting power supply unit according to claim 13, wherein the boosting circuit, which comprises shared capacitors subjected to two-phase control of the step-down switch control signals and the step-up switch control signals, alternately outputs the boosted positive voltage by the step-up switch control signals and the boosted negative voltage by the step-down switch control signals when the phase control signal has a two-phase pulse form, and outputs one of the boosted positive voltage and the boosted negative voltage when the phase control signal has a logic state value form.
17. The boosting power supply unit according to claim 16, wherein the boosting circuit, comprises:
a first capacitor connected between a first node and a second node;
a second capacitor connected between a third node and a fourth node;
a third capacitor connected between a boosted positive voltage output node and a third power source;
a fourth capacitor connected between a boosted negative voltage output node and the third power source;
a first switch which selectively connects or disconnects a fourth power source and the first node in response to a logic state of a first control signal;
a second switch which selectively connects or disconnects the fourth power source and the third node in response to a logic state of a second control signal;
a third switch which selectively connects or disconnects the third power source and the third node in response to a logic state of a third control signal;
a fourth switch which selectively connects or disconnects the first node and the boosted positive voltage output node in response to a logic state of a fourth control signal;
a fifth switch which selectively connects or disconnects the first node and a first power source in response to a logic state of a fifth control signal;
a sixth switch which selectively connects or disconnects the first node and the third node in response to a logic state of a sixth control signal;
a seventh switch which selectively connects or disconnects the third node and the boosted positive voltage output node in response to a logic state of a seventh control signal;
an eighth switch which selectively connects or disconnects the second node and the first power source in response to a logic state of an eighth control signal;
a ninth switch which selectively connects or disconnects the second node and the third power source in response to a logic state of a ninth control signal;
a tenth switch which selectively connects or disconnects the fourth node and the first power source in response to a logic state of a tenth control signal;
an eleventh switch which selectively connects or disconnects the fourth node and the third power source in response to a logic state of an eleventh control signal;
a twelfth switch which selectively connects or disconnects the fourth node and a second power source in response to a logic state of a twelfth control signal;
a thirteenth switch which selectively connects or disconnects the fourth node and the boosted negative voltage output node in response to a logic state of a thirteenth control signal; and
a fourteenth switch which selectively connects or disconnects the second node and the boosted negative voltage output node in response to a logic state of a fourteenth control signal, and
wherein the first control signal through the fourteenth control signal belong to one of a group of the step-down switch control signals and a group of the step-up switch control signals.
18. The boosting power supply unit according to claim 13, wherein the boosting circuit, which comprises separate capacitors subjected to two-phase control of each of the step-down switch control signals and the step-up switch control signals, alternately outputs the boosted positive voltage by the step-up switch control signals and the boosted negative voltage by the step-down switch control signals when the phase control signal has a two-phase pulse form, and outputs one of the boosted positive voltage and the boosted negative voltage when the phase control signal has a logic state value form.
19. The boosting power supply unit according to claim 18, wherein the boosting circuit, which comprises a positive boosting circuit which outputs the boosted positive voltage by means of a first group of capacitors subjected to two-phase control of the step-up switch control signals, and a negative boosting circuit which outputs the boosted negative voltage by means of a second group of capacitors subjected to two-phase control of the step-down switch control signals.
20. The boosting power supply unit according to claim 19, wherein the positive boosting circuit, comprises:
a first capacitor connected between a first node and a second node;
a second capacitor connected between a third node and a fourth node;
a third capacitor connected between a boosted positive voltage output node and a third power source;
a first switch which selectively connects or disconnects the first node and a first power source in response to a logic state of a first control signal;
a second switch which selectively connects or disconnects the first node and the third node in response to a logic state of a second control signal;
a third switch which selectively connects or disconnects the third node and the boosted positive voltage output node in response to a logic state of a third control signal;
a fourth switch which selectively connects or disconnects the first node and the boosted positive voltage output node in response to a logic state of a fourth control signal;
a fifth switch which selectively connects or disconnects the second node and the first power source in response to a logic state of a fifth control signal;
a sixth switch which selectively connects or disconnects the second node and the third power source in response to a logic state of a sixth control signal;
a seventh switch which selectively connects or disconnects the fourth node and the first power source in response to a logic state of a seventh control signal;
an eighth switch which selectively connects or disconnects the fourth node and a second power source in response to a logic state of an eighth control signal; and
a ninth switch which selectively connects or disconnects the fourth node and the third power source in response to a logic state of a ninth control signal, and
wherein the first control signal through the ninth control signal belong to a group of the step-up switch control signals.
21. The boosting power supply unit according to claim 19, wherein the negative boosting circuit, comprises:
a first capacitor connected between a first node and a second node;
a second capacitor connected between a third node and a fourth node;
a third capacitor connected between a boosted negative voltage output node and a third power source;
a first switch which selectively connects or disconnects the first node and the third power source in response to a logic state of a first control signal;
a second switch which selectively connects or disconnects the first node and the third node in response to a logic state of a second control signal;
a third switch which selectively connects or disconnects the third node and the boosted negative voltage output node in response to a logic state of a third control signal;
a fourth switch which selectively connects or disconnects the first node and the boosted negative voltage output node in response to a logic state of a fourth control signal;
a fifth switch which selectively connects or disconnects the second node and the third power source in response to a logic state of a fifth control signal;
a sixth switch which selectively connects or disconnects the second node and a first power source in response to a logic state of a sixth control signal;
a seventh switch which selectively connects or disconnects the second node and a second power source in response to a logic state of a seventh control signal;
an eighth switch which selectively connects or disconnects the fourth node and the third power source in response to a logic state of an eighth control signal;
a ninth switch which selectively connects or disconnects the fourth node and the second power source in response to a logic state of a ninth control signal; and
a tenth switch which selectively connects or disconnects the fourth node and the first power source in response to a logic state of a tenth control signal, and
wherein the first control signal through the tenth control signal belong to a group of the step-down switch control signals.
22. A voltage boosting method which outputs a boosted positive voltage to a first boosted voltage output node and outputs a boosted negative voltage to a second boosted voltage output node by sharing a first capacitor connected between a first node and a second node, a second capacitor connected between a third node and a fourth node, a third capacitor connected between the first boosted voltage output node and a third power source, and a fourth capacitor connected between the second boosted voltage output node and the third power source, the method comprising the steps of:
(a) selectively connecting or disconnecting a fourth power source and the first node in response to a logic state of a first control signal;
(b) selectively connecting or disconnecting the fourth power source and the third node in response to a logic state of a second control signal;
(c) selectively connecting or disconnecting the third power source and the third node in response to a logic state of a third control signal;
(d) selectively connecting or disconnecting the first node and the first boosted voltage output node in response to a logic state of a fourth control signal;
(e) selectively connecting or disconnecting the first node and a first power source in response to a logic state of a fifth control signal;
(f) selectively connecting or disconnecting the first node and the third node in response to a logic state of a sixth control signal;
(g) selectively connecting or disconnecting the third node and the first boosted voltage output node in response to a logic state of a seventh control signal;
(h) selectively connecting or disconnecting the second node and the first power source in response to a logic state of an eighth control signal;
(i) selectively connecting or disconnecting the second node and the third power source in response to a logic state of a ninth control signal;
(j) selectively connecting or disconnecting the fourth node and the first power source in response to a logic state of a tenth control signal;
(k) selectively connecting or disconnecting the fourth node and the third power source in response to a logic state of an eleventh control signal;
(l) selectively connecting or disconnecting the fourth node and a second power source in response to a logic state of a twelfth control signal;
(m) selectively connecting or disconnecting the fourth node and the second boosted voltage output node in response to a logic state of a thirteenth control signal; and
(n) selectively connecting or disconnecting the second node and the second boosted voltage output node in response to a logic state of a fourteenth control signal.
23. The voltage boosting method according to claim 22, wherein the steps of connecting or disconnecting are performed by a switching means formed using metal-oxide-semiconductor field effect transistors (MOSFETs).
24. The voltage boosting method according to claim 22, wherein each of the boosted voltage output nodes outputs boosted voltages under two-phase control of the control signals.
25. The voltage boosting method according to claim 22, wherein the first boosted voltage output node and the second boosted voltage output node output three boosted positive voltages and three boosted negative voltages, respectively, in response to the control signals.
26. A voltage boosting method which outputs a boosted voltage by using a first capacitor connected between a first node and a second node, a second capacitor connected between a third node and a fourth node and a third capacitor connected between a boosted voltage output node and a third power source, the method comprising the steps of:
(a) selectively connecting or disconnecting the first node and a first power source in response to a logic state of a first control signal;
(b) selectively connecting or disconnecting the first node and the third node in response to a logic state of a second control signal;
(c) selectively connecting or disconnecting the third node and the boosted voltage output node in response to a logic state of a third control signal;
(d) selectively connecting or disconnecting the first node and the boosted voltage output node in response to a logic state of a fourth control signal;
(e) selectively connecting or disconnecting the second node and the first power source in response to a logic state of a fifth control signal;
(f) selectively connecting or disconnecting the second node and the third power source in response to a logic state of a sixth control signal;
(g) selectively connecting or disconnecting the fourth node and the first power source in response to a logic state of a seventh control signal;
(h) selectively connecting or disconnecting the fourth node and a second power source in response to a logic state of an eighth control signal; and
(i) selectively connecting or disconnecting the fourth node and the third power source in response to a logic state of a ninth control signal.
27. The voltage boosting method according to claim 26, wherein the steps of connecting or disconnecting are performed by a switching means formed using metal-oxide-semiconductor field effect transistors (MOSFETs).
28. The voltage boosting method according to claim 26, wherein each of the boosted voltage output nodes outputs boosted voltages under two-phase control of the control signals.
29. The voltage boosting method according to claim 26, wherein the boosted voltage output node outputs three boosted voltages in response to the control signals.
30. A voltage boosting method which outputs a boosted voltage by using a first capacitor connected between a first node and a second node, a second capacitor connected between a third node and a fourth node, and a third capacitor connected between a boosted voltage output node and a third power source, the method comprising the steps of:
(a) selectively connecting or disconnecting the first node and the third power source in response to a logic state of a first control signal;
(b) selectively connecting or disconnecting the first node and the third node in response to a logic state of a second control signal;
(c) selectively connecting or disconnecting the third node and the boosted voltage output node in response to a logic state of a third control signal;
(d) selectively connecting or disconnecting the first node and the boosted voltage output node in response to a logic state of a fourth control signal;
(e) selectively connecting or disconnecting the second node and the third power source in response to a logic state of a fifth control signal;
(f) selectively connecting or disconnecting the second node and a first power source in response to a logic state of a sixth control signal;
(g) selectively connecting or disconnecting the second node and a second power source in response to a logic state of a seventh control signal;
(h) selectively connecting or disconnecting the fourth node and the third power source in response to a logic state of an eighth control signal;
(i) selectively connecting or disconnecting the fourth node and the second power source in response to a logic state of a ninth control signal; and
(j) selectively connecting or disconnecting the fourth node and the first power source in response to a logic state of a tenth control signal.
31. The voltage boosting method according to claim 30, wherein the steps of connecting or disconnecting are performed by a switching means formed using metal-oxide-semiconductor field effect transistors (MOSFETs).
32. The voltage boosting method according to claim 30, wherein each of the boosted voltage output nodes outputs boosted voltages under two-phase control of the control signals.
33. The voltage boosting method according to claim 30, wherein the boosted voltage output node outputs three boosted voltages in response to the control signals.
34. A power boosting control method comprising the steps of:
(a) outputting a phase control signal having one of two-phase pulse form and logic state value form in response to each of four logic combinations of a first enable signal and a second enable signal;
(b) generating and outputting two-phase step-down switch control signals corresponding to a mode signal in a first logic state of the phase control signal, and generating and outputting two-phase step-up switch control signals corresponding to the mode signal in a second logic state of the phase control signal; and
(c) outputting boosted negative voltages by means of capacitors subjected to two-phase control of the step-down switch control signals, and outputting boosted positive voltages by means of capacitors subjected to two-phase control of the step-up switch control signals.
35. The power boosting control method according to claim 34, wherein the first enable signal and the second enable signal are digital signals having different logic states with respect to above and below a threshold amount of power in response to amounts of power consumed in loads connected to the boosted positive voltage and the boosted negative voltage, respectively.
36. The power boosting control method according to claim 34, wherein when both of the first enable signal and the second enable signal have a first logic state, at least one signal of the step-down switch control signals and at least one signal of the step-up switch control signals are not activated.
37. The power boosting control method according to claim 34, wherein in the step of (c), by using shared capacitors subjected to two-phase control of the step-down switch control signals and the step-up switch control signals, the boosted positive voltage by the step-up switch control signals and the boosted negative voltage by the step-down switch control signals are alternately output when the phase control signal has a two-phase pulse form, and one of the boosted positive voltage and the boosted negative voltage is output when the phase control signal has a logic state value form.
38. The power boosting control method according to claim 37, wherein the step of (c) comprises the steps of;
by using a first capacitor connected between a first node and a second node, a second capacitor connected between a third node and a fourth node, a third capacitor connected between a boosted positive voltage output node and a third power source and a fourth capacitor connected between a boosted negative voltage output node and the third power source,
(c-1) selectively connecting or disconnecting a fourth power source and the first node in response to a logic state of a first control signal;
(c-2) selectively connecting or disconnecting the fourth power source and the third node in response to a logic state of a second control signal;
(c-3) selectively connecting or disconnecting the third power source and the third node in response to a logic state of a third control signal;
(c-4) selectively connecting or disconnecting the first node and the boosted positive voltage output node in response to a logic state of a fourth control signal;
(c-5) selectively connecting or disconnecting the first node and a first power source in response to a logic state of a fifth control signal;
(c-6) selectively connecting or disconnecting the first node and the third node in response to a logic state of a sixth control signal;
(c-7) selectively connecting or disconnecting the third node and the boosted positive voltage output node in response to a logic state of a seventh control signal;
(c-8) selectively connecting or disconnecting the second node and the first power source in response to a logic state of an eighth control signal;
(c-9) selectively connecting or disconnecting the second node and the third power source in response to a logic state of a ninth control signal;
(c-10) selectively connecting or disconnecting the fourth node and the first power source in response to a logic state of a tenth control signal;
(c-11) selectively connecting or disconnecting the fourth node and the third power source in response to a logic state of an eleventh control signal;
(c-12) selectively connecting or disconnecting the fourth node and a second power source in response to a logic state of a twelfth control signal;
(c-13) selectively connecting or disconnecting the fourth node and the boosted negative voltage output node in response to a logic state of a thirteenth control signal; and
(c-14) selectively connecting or disconnecting the second node and the boosted negative voltage output node in response to a logic state of a fourteenth control signal, and
wherein the first control signal through the fourteenth control signal belong to one of a group of the step-down switch control signals and a group of the step-up switch control signals.
39. The power boosting control method according to claim 34, wherein in the step of (c), by using separate capacitors subjected to two-phase control of each of the step-down switch control signals and the step-up switch control signals, the boosted positive voltage by the step-up switch control signals and the boosted negative voltage by the step-down switch control signals are alternately output when the phase control signal has a two-phase pulse form, and one of the boosted positive voltage and the boosted negative voltage is output when the phase control signal has a logic state value form.
40. The power boosting control method according to claim 39, wherein the step of (c) comprises the steps of:
(c-1) outputting the boosted positive voltage by means of a first group of capacitors subjected to two-phase control of the step-up switch control signals; and
(c-2) outputting the boosted negative voltage by means of a second group of capacitors subjected to two-phase control of the step-down switch control signals.
41. The power boosting control method according to claim 40, wherein the step of (c-1) comprises the steps of:
by using a first capacitor connected between a first node and a second node, a second capacitor connected between a third node and a fourth node, and a third capacitor connected between a boosted positive voltage output node and a third power source,
(c-1-1) selectively connecting or disconnecting the first node and a first power source in response to a logic state of a first control signal;
(c-1-2) selectively connecting or disconnecting the first node and the third node in response to a logic state of a second control signal;
(c-1-3) selectively connecting or disconnecting the third node and the boosted positive voltage output node in response to a logic state of a third control signal;
(c-1-4) selectively connecting or disconnecting the first node and the boosted positive voltage output node in response to a logic state of a fourth control signal;
(c-1-5) selectively connecting or disconnecting the second node and the first power source in response to a logic state of a fifth control signal;
(c-1-6) selectively connecting or disconnecting the second node and the third power source in response to a logic state of a sixth control signal;
(c-1-7) selectively connecting or disconnecting the fourth node and the first power source in response to a logic state of a seventh control signal;
(c-1-8) selectively connecting or disconnecting the fourth node and a second power source in response to a logic state of an eighth control signal; and
(c-1-9) selectively connecting or disconnecting the fourth node and the third power source in response to a logic state of a ninth control signal, and
wherein the first control signal through the ninth control signal belong to a group of the step-up switch control signals.
42. The power boosting control method according to claim 40, wherein the step of (c-2) comprises the steps of:
by using a first capacitor connected between a first node and a second node, a second capacitor connected between a third node and a fourth node, and a third capacitor connected between a boosted negative voltage output node and a third power source,
(c-2-1) selectively connecting or disconnecting the first node and the third power source in response to a logic state of a first control signal;
(c-2-2) selectively connecting or disconnecting the first node and the third node in response to a logic state of a second control signal;
(c-2-3) selectively connecting or disconnecting the third node and the boosted negative voltage output node in response to a logic state of a third control signal;
(c-2-4) selectively connecting or disconnecting the first node and the boosted negative voltage output node in response to a logic state of a fourth control signal;
(c-2-5) selectively connecting or disconnecting the second node and the third power source in response to a logic state of a fifth control signal;
(c-2-6) selectively connecting or disconnecting the second node and a first power source in response to a logic state of a sixth control signal;
(c-2-7) selectively connecting or disconnecting the second node and a second power source in response to a logic state of a seventh control signal;
(c-2-8) selectively connecting or disconnecting the fourth node and the third power source in response to a logic state of an eighth control signal;
(c-2-9) selectively connecting or disconnecting the fourth node and the second power source in response to a logic state of a ninth control signal; and
(c-2-10) selectively connecting or disconnecting the fourth node and the first power source in response to a logic state of a tenth control signal, and
wherein the first control signal through the tenth control signal belong to a group of the step-down switch control signals.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A device for the wet-treatment of laundry comprising:
a rotatingly driveable internal drum (11), which is liquid-permeable at least in part and in which treatment chambers (14), which follow one after another in the direction of its longitudinal center axis (12), are formed by partition walls (16), which extend perpendicular to the longitudinal center axis (12) of the internal drum (11);
at least two stationary external drums (19) which are assigned to the treatment chambers (14), wherein, support rings, which are sealed by means of seals (20, 21) in relation to the external drums (19), are provided between those treatment chambers (14), to which the external drums (19) are assigned, wherein separate seals (20, 21) are provided for adjacent treatment chambers (14) between in each case two adjacent external drums (19).
2. The device according to claim 1, wherein the two seals (20, 21) which are arranged between adjacent external drums (19) are operative in opposite directions and sealing edges (24) on free ends of sealing lips (22) of the seals (20, 21) preferably point to one another.
3. The device according to claim 1, wherein the two seals (20, 21) are oriented in a parallel manner between adjacent external drums (19).
4. The device according to claim 1, wherein the seals (20, 21) which are arranged between adjacent external drums (19) are realized identically or in a similar manner andor the two identical seals (20, 21) are oriented in an opposite or mirror-inverted manner.
5. The device according to claim 1, wherein the two seals (20, 21) in each case between two adjacent external drums (19) are assigned to an identical support ring on the outside circumference of the internal drum (20, 21), preferably in such a manner that sealing edges (24) of the seals (20, 21) abut in a sealing manner against support surfaces (18) of oppositely located sides of the support ring.
6. The device according to claim 5, wherein at least one support ring is formed by a partition wall (16) of the internal drum (11) by the outside diameter of the partition wall (16) being greater than the diameter of the internal drum (11) and the support ring being situated between the outside circumference of the internal drum (19) and the greater outside diameter of the partition wall (16).
7. The device according to claim 1, wherein each of the seals (20, 21) assigned to the two adjacent external drums (19) have assigned thereto an own support ring, wherein the two support rings are preferably situated between the adjacent external drums (19) andor are spaced apart from one another.
8. The device according to claim 7, wherein the two seals (20, 21) are assigned to outside end faces of the two support rings which are directed away from one another, preferably in such a manner that the sealing edges (24) of the seals (20, 21) abut in a sealing manner against support surfaces (18) of oppositely situated external end faces of the support rings.
9. The device according to claim 7, wherein the second support ring is formed by a separate ring (27) which surrounds the internal drum (11) and is connected to the internal drum (11), preferably in a liquid-tight manner.
10. The device according to claim 1, wherein the external drums (19) comprise open end faces and the open end faces of the external drums (19), preferably the two oppositely situated end faces of each external drum (19), also of adjacent external drums (19), have assigned thereto a separate seal (20, 21) for sealing the two open end faces of the external drums (19).
11. The device according to claim 1, wherein each seal (20, 21) comprises a preferably cylindrical foot portion (23) which surrounds the outside of an end-face edge region of the external drum (19) which is assigned the seal (20, 21) and on one end is connected in one piece to the sealing lip (22), preferably the seal (20, 21) is fastened to the foot portion (23) in a releasable manner on the end-face edge region of the external drum (19) assigned thereto.
12. The device according to claim 1, wherein the seals (20, 21) between adjacent external drums (19) are spaced apart from one another, preferably the foot portions (23) of the two seals (20, 21) are fastened in a releasable manner at a spacing from one another on the outside of the adjacent end-face edge regions of external drums (19) which are arranged side by side.
13. The device according to claim 1, wherein at least one collecting tray (31) for leakage liquids andor treatment liquids is assigned to the two seals (20, 21) between adjacent external drums (19), preferably a space between the adjacent seals (20, 21), at least in a bottom region.