Author: claimsbot

1-52. (canceled)
53. A method for determining a capacitance of a device used to hold a cell in an electrophysiological experiment, the method comprising:
applying a stimulus to the device through a force amplifier;
measuring a response to the stimulus with a separate sense amplifier; and
determining the capacitance of the device by analyzing the response to the stimulus.
54. The method of claim 53 further comprising employing compensation circuitry to compensate for the capacitance of the device.
55. The method of claim 53, wherein determining the capacitance of the device comprises calculating an RC time constant of the response to the stimulus.
56. A subsystem for determining a capacitance of a device used to hold a cell in an electrophysiological experiment, the subsystem comprising:
a force amplifier configured to apply a stimulus to the device;
a separate sense amplifier configured to measure a response to the stimulus; and
a determination module configured to determine the capacitance of the device by analyzing the response to the stimulus.
57. The subsystem of claim 56 further comprising compensation circuitry configured to compensate for the capacitance of the device.
58. The subsystem of claim 56, wherein the determination module is configured to calculate an RC time constant of the response to the stimulus in determining the capacitance of the device.
59-67. (canceled)
68. A method of compensating for a capacitive waveform present in a patch clamp system, comprising:
measuring a magnitude of the capacitive waveform at each of a plurality of times; and
outputting a gain-adjusted compensatory waveform from each of a plurality of compensation circuits to compensate for the capacitive waveform,
wherein each compensation circuit has a unique time constant.
69. The method of claim 68 further comprising outputting an unadjusted compensatory waveform from each of the plurality of compensation circuits.
70. The method of claim 69 further comprising measuring a magnitude of each unadjusted compensatory waveform at each of the plurality of times.
71. The method of claim 70 further comprising calculating a gain adjustment for each of the plurality of compensation circuits.
72. The method of claim 71, wherein each gain adjustment is calculated based on the measured magnitude of the capacitive waveform at each of the plurality of times and the measured magnitude of each unadjusted compensatory waveform at each of the plurality of times.
73. The method of claim 68 further comprising calculating a leakage resistance present in the patch clamp system.
74. The method of claim 73 further comprising adjusting the measurement of the capacitive waveform to account for a virtual peak to be introduced into the capacitive waveform following compensation of the leakage resistance.
75. The method of claim 73 further comprising compensating for the leakage resistance present in the patch clamp system.
76. The method of claim 75 further comprising re-measuring the magnitude of the capacitive waveform at each of the plurality of times while the leakage resistance is compensated for.
77. A subsystem for compensating for a capacitive waveform present in a patch clamp system, comprising:
measurement circuitry for measuring a magnitude of the capacitive waveform at each of a plurality of times; and
a plurality of compensation circuits, each compensation circuit having a unique time constant and configured to output a gain-adjusted compensatory waveform to compensate for the capacitive waveform.
78. The subsystem of claim 77, wherein each compensation circuit is further configured to output an unadjusted compensatory waveform.
79. The subsystem of claim 78, wherein the measurement circuitry is further configured to measure a magnitude of each unadjusted compensatory waveform at each of the plurality of times.
80. The subsystem of claim 79 further comprising calculation circuitry for calculating a gain adjustment for each of the plurality of compensation circuits.
81. The subsystem of claim 80, wherein each gain adjustment is calculated based on the measured magnitude of the capacitive waveform at each of the plurality of times and the measured magnitude of each unadjusted compensatory waveform at each of the plurality of times.
82. The subsystem of claim 77 further comprising calculation circuitry for calculating a leakage resistance present in the patch clamp system.
83. The subsystem of claim 82, wherein the calculation circuitry is further configured to adjust the measurement of the capacitive waveform to account for a virtual peak to be introduced into the capacitive waveform following compensation of the leakage resistance.
84. The subsystem of claim 82 further comprising leakage resistance compensation circuitry for compensating the leakage resistance present in the patch clamp system.
85. The subsystem of claim 84, wherein the measurement circuitry is further configured to re-measure the magnitude of the capacitive waveform at each of the plurality of times while the leakage resistance compensation circuitry compensates the leakage resistance.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A circuit comprising:
a log amp to generate an envelope signal in response to an RF input signal; and
a translinear post-processing circuit coupled to the log amp to provide a measure of the envelope signal to extract an RMS value of the RF input signal;
where the translinear post-processing circuit comprises devices in a translinear loop having exponential characteristics.
2. The circuit of claim 1 where the log amp comprises a demodulating progressive compression log amp.
3. The circuit of claim 1 where the post-processing circuit implements a square-law function.
4. The circuit of claim 3 where the envelope signal is scaled in the logarithmic domain so the post-processing circuit provides a square-law response in a linear domain.
5. The circuit of claim 3 where the post-processing circuit implements an RMS function.
6. The circuit of claim 1 where the post-processing circuit comprises a translinear loop having a \u0394VBE element to introduce the envelope signal into the loop.
7. A circuit according to claim 1 where:
the translinear loop is arranged to provide a power measurement function; and
the devices in the translinear loop include a \u0394VBE element to introduce an input signal into the loop in the logarithmic domain.
8. The circuit of claim 7 where the translinear loop is arranged to implement an RMS function.
9. The circuit of claim 7 where the \u0394VBE element comprises a resistor connected in series in the loop.
10. The circuit of claim 9 where the input signal is applied to the resistor as a current.
11. The circuit of claim 10 where the circuit is arranged to cancel a pedestal in the input signal.
12. The circuit of claim 7 where the translinear loop comprises:
an input path having one or more junctions arranged to operate at a constant current; and
an output path having one or more transistors coupled to the input path and arranged to provide an output signal as a current.
13. The circuit of claim 12 where the translinear loop is arranged to provide a square-law signal in response to the input signal.
14. The circuit of claim 13 further comprising a capacitor to average the square-law signal.
15. The circuit of claim 14 further comprising a feedback loop coupled to the capacitor and the translinear loop to implement an implicit square-root function.
16. The circuit of claim 15 where:
the input path includes two transistors having two junctions facing a first direction in the translinear loop;
the output path includes two transistors having two junctions facing a second direction in the translinear loop; and
the feedback loop comprises a transconductance cell having an input coupled to the capacitor and an output coupled to force a current through one of the two transistors in the output path.
17. A method comprising:
generating a compressed envelope signal using a logarithmic amplifier in response to an RF input signal; and
post-processing the envelope signal to provide a decompressed measure of the power represented by the envelope signal to extract an RMS value of the RF input signal using a translinear post-processing circuit;
where said post-processing the envelope signal comprises applying the envelope signal to devices in a translinear loop having exponential characteristics.
18. The method of claim 17 where said generating the envelope signal comprises rectifying and filtering the RF input signal.
19. The method of claim 18 where said rectifying and filtering the RF input signal comprises applying the RF input signal to a diode coupled to a capacitor.
20. The method of claim 19 further comprising generating the envelope signal in a logarithmic domain.
21. The method of claim 20 where said post-processing the envelope signal comprises converting the signal in the logarithmic domain back to the linear domain.
22. The method of claim 21 further comprising scaling the envelope signal in the logarithmic domain, thereby providing a square-law function in the linear domain.

1. A method for fabricating an electrostatic capacitance-type acceleration sensor having a capacitor which electrostatic capacitance between a movable electrode and a fixed electrode changes according to displacement of the movable electrode, the method comprising steps of:
forming a groove on at least one of one surface of an insulative substrate on which the fixed electrode is formed as a film and one surface of a semiconductor substrate to which the insulative substrate is joined, the one surface of the insulative substrate being on an opposite side of the other surface thereof on which the fixed electrode is formed as the film, and the insulative substrate being joined to the one surface of the semiconductor substrate;
forming a hole in the semiconductor substrate so as to penetrate from the one surface to the other surface of the semiconductor substrate, at a position communicating with a passage formed by the groove; and
forming an electrode extraction hole, for electrically connecting the fixed electrode to the semiconductor substrate, in the insulative substrate so as to penetrate from the one surface to the other surface of the insulative substrate, at a position communicating with the passage formed by the groove.
2. The method for fabricating an electrostatic capacitance-type acceleration sensor according to claim 1, wherein
the electrostatic capacitance-type acceleration sensor includes a first capacitor which electrostatic capacitance between the movable electrode and a first fixed electrode changes according to the displacement of the movable electrode, and a second capacitor which electrostatic capacitance between the movable electrode and a second fixed electrode changes according to the displacement of the movable electrode in a contrary manner to the first capacitor, and wherein
the step of forming the groove forms the groove on at least one of the one surface of the insulative substrate on which one of the first fixed electrode and the second fixed electrode is formed as the film and the one surface of the semiconductor substrate to which the insulative substrate is joined, the one surface of the insulative substrate being on the opposite side of the other surface thereof on which the fixed electrode is formed as the film, and the insulative substrate being joined to the one surface of the semiconductor substrate.
3. The method for fabricating an electrostatic capacitance-type acceleration sensor according to claim 1, wherein the step of forming the hole in the insulative substrate forms the hole in the insulative substrate, to which the semiconductor substrate is joined, from the surface side of the insulative substrate on which the fixed electrode is formed as the film.
4. An apparatus for fabricating an electrostatic capacitance-type acceleration sensor having a capacitor which electrostatic capacitance between a movable electrode and a fixed electrode changes according to displacement of the movable electrode, the apparatus comprising:
means for forming a groove on at least one of one surface of an insulative substrate on which the fixed electrode is formed as a film and one surface of a semiconductor substrate to which the insulative substrate is joined, the one surface of the insulative substrate being on an opposite side of the other surface thereof on which the fixed electrode is formed as the film, and the insulative substrate being joined to the one surface of the semiconductor substrate;
means for forming a hole in the semiconductor substrate so as to penetrate from the one surface to the other surface of the semiconductor substrate, at a position communicating with a passage formed by the groove; and
means for forming an electrode extraction hole, for electrically connecting the fixed electrode to the semiconductor substrate, in the insulative substrate so as to penetrate from the one surface to the other surface of the insulative substrate, at a position communicating with the passage formed by the groove.
5. An electrostatic capacitance-type acceleration sensor having a capacitor which electrostatic capacitance between a movable electrode and a fixed electrode changes according to displacement acceleration of the movable electrode, comprising:
an insulative substrate on which the fixed electrode of the capacitor is formed as a film; and
a semiconductor substrate which is joined to one surface of the insulative substrate on an opposite side of the other surface thereof on which the fixed electrode is formed as the film, wherein
a groove is formed on at least one of the one surface of the insulative substrate and the one surface of the semiconductor substrate to which the insulative substrate is joined, the one surface of the insulative substrate being on the opposite side of the other surface thereof on which the fixed electrode is formed as the film, wherein
a first hole is formed in the semiconductor substrate so as to penetrate from the one surface to the other surface of the semiconductor substrate, at a position communicating with a passage formed by the groove, and wherein
a second hole for electrode extraction, for electrically connecting the fixed electrode to the semiconductor substrate, is formed in the insulative substrate so as to penetrate from the one surface to the other surface of the insulative substrate, at a position communicating with the passage formed by the groove.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An image processing apparatus comprising:
conversion means for converting a standard definition interlace image including a first number of pixels into a first standard definition progressive image;
interpolation means for interpolating the first standard definition progressive image to generate a first high definition progressive image including a second number of pixels, higher than the first number of pixels, which are equal to a number of pixels of a target high definition image;
classification means for classifying, in accordance with a feature of the first high definition progressive image, into classes, subject pixels forming a second high definition progressive image, which serves as the target high definition image, including the second number of pixels and having a quality higher than the first high definition progressive image, the second high definition progressive image being determined from the first high definition progressive image;
storage means for storing a prediction coefficient for each of the classes, the prediction coefficient being obtained by conducting learning using a plurality of high definition progressive images, each including the second number of pixels; and
computation means for performing computation using the first high definition progressive image and the prediction coefficient for each of the classes into which the subject pixels are classified to determine the second high definition progressive image, which serves as the target high definition image, from the first high definition progressive image, wherein the conversion means includes,
interlace-progressive conversion means for converting the standard definition interlace image into a progressive intermediate image,
motion-vector detection means for detecting motion vectors and macro-block differences of the standard definition interlace image by using, as a minimum unit, a distance shorter than an interval between pixels forming the progressive intermediate image,
cyclic-coefficient setting means for setting, based on a vertical motion, which is a vertical component of each of the motion vectors, a first cyclic coefficient for a first type of pixel that is located at a position where a pixel forming the standard definition interlace image exists, the first cyclic coefficient calculated by using the corresponding motion vector and the macro-block difference, and a second cyclic coefficient for a second type of pixel, which is located at a position where a pixel forming the standard definition interlace image does not exist, the second cyclic coefficient calculated by using the corresponding motion vector and the macro-block difference,
motion compensation means for motion-compensating, on a basis of the motion vectors, a past first progressive image to generate a motion-compensated image, and
output image generating means for generating the first standard definition progressive image by adding pixel values of the first type of pixels located at corresponding positions of the intermediate image and the motion-compensated image by using the first cyclic coefficients as weights and by adding pixel values of the second type of pixels located at corresponding positions of the intermediate image and the motion-compensated image by using the second cyclic coefficients as weights.
2. The image processing apparatus according to claim 1, wherein the computation means includes a means for predicting a natural image of the first high definition progressive image, a means for predicting an artificial image of the first high definition progressive image, a means for determining a ratio between the natural image and the artificial image of the first high definition progressive image, and a means for synthesizing an output from the means for predicting the natural image and the means for predicting the artificial image based on the determined ratio to form the second high definition image.
3. An image processing method comprising the steps of:
converting a standard definition interlace image including a first number of pixels into a first standard definition progressive image;
generating a first high definition progressive image including a second number of pixels, higher than the first number of pixels, which are equal to a number of pixels of a target image by interpolating the first standard definition progressive image;
classifying, in accordance with a feature of the first high definition progressive image, into classes, subject pixels forming a second high definition progressive image, which serves as the target high definition image, including the second number of pixels and having a quality higher than the first high definition progressive image, the second high definition progressive image being determined from the first high definition progressive image; and
determining the second high definition progressive image, which serves as the target high definition image, from the first high definition progressive image by performing computation using the first high definition progressive image and a prediction coefficient for each of the classes into which the subject pixels are classified among prediction coefficients obtained by conducting learning using a plurality of high definition progressive images, each including the second number of pixels, wherein said step of converting includes,
converting the standard definition interlace image into a progressive intermediate image,
detecting motion vectors and macro-block differences of the standard definition interlace image by using, as a minimum unit, a distance shorter than an interval between pixels forming the progressive intermediate image,
setting, based on a vertical motion, which is a vertical component of each of the motion vectors, a first cyclic coefficient for a first type of pixel that is located at a position where a pixel forming the standard definition interlace image exists, the first cyclic coefficient calculated by using the corresponding motion vector and the macro-block difference, and a second cyclic coefficient for a second type of pixel, which is located at a position where a pixel forming the standard definition interlace image does not exist, the second cyclic coefficient calculated by using the corresponding motion vector and the macro-block difference,
motion-compensating, on a basis of the motion vectors, a past first progressive image to generate a motion-compensated image, and
generating the first standard definition progressive image by adding pixel values of the first type of pixels located at corresponding positions of the intermediate image and the motion-compensated image by using the first cyclic coefficients as weights and by adding pixel values of the second type of pixels located at corresponding positions of the intermediate image and the motion-compensated image by using the second cyclic coefficients as weights.
4. A non-transitory computer readable medium having computer instructions recorded thereon, the computer instructions configured to perform a method when executed on a computer, the method comprising the steps of:
converting a standard definition interlace image including a first number of pixels into a first standard definition progressive image;
generating a first high definition progressive image including a second number of pixels, higher than the first number of pixels, which are equal to a number of pixels of a target high definition image by interpolating the first standard definition progressive image;
classifying, in accordance with a feature of the first high definition progressive image, into classes, subject pixels forming a second high definition progressive image, which serves as the target high definition image, including the second number of pixels and having a quality higher than the first high definition progressive image, the second high definition progressive image being determined from the first high definition progressive image; and
determining the second high definition progressive image, which serves as the target high definition image, from the first high definition progressive image by performing computation using the first high definition progressive image and a prediction coefficient for each of the classes into which the subject pixels are classified among prediction coefficients obtained by conducting learning using a plurality of high definition progressive images, each including the second number of pixels, wherein said step of converting includes,
converting the standard definition interlace image into a progressive intermediate image,
detecting motion vectors and macro-block differences of the standard definition interlace image by using, as a minimum unit, a distance shorter than an interval between pixels forming the progressive intermediate image,
setting, based on a vertical motion, which is a vertical component of each of the motion vectors, a first cyclic coefficient for a first type of pixel that is located at a position where a pixel forming the standard definition interlace image exists, the first cyclic coefficient calculated by using the corresponding motion vector and the macro-block difference, and a second cyclic coefficient for a second type of pixel, which is located at a position where a pixel forming the standard definition interlace image does not exist, the second cyclic coefficient calculated by using the corresponding motion vector and the macro-block difference,
motion-compensating, on a basis of the motion vectors, a past first progressive image to generate a motion-compensated image, and
generating the first standard definition progressive image by adding pixel values of the first type of pixels located at corresponding positions of the intermediate image and the motion-compensated image by using the first cyclic coefficients as weights and by adding pixel values of the second type of pixels located at corresponding positions of the intermediate image and the motion-compensated image by using the second cyclic coefficients as weights.
5. An image processing apparatus comprising:
a converter configured to convert a standard definition interlace image including a first number of pixels into a first standard definition progressive image;
an interpolator configured to interpolate the first standard definition progressive image to generate a first high definition progressive image including a second number of pixels, higher than the first number of pixels, which are equal to a number of pixels of a target high definition image;
a classification unit configured to classify, in accordance with a feature of the first high definition progressive image, into classes, subject pixels forming a second high definition progressive image, which serves as the target high definition image, including the second number of pixels and having a quality higher than the first high definition progressive image, the second high definition progressive image being determined from the first high definition progressive image;
a storage unit configured to store a prediction coefficient for each of the classes, the prediction coefficient being obtained by conducting learning using a plurality of high definition progressive images, each including the second number of pixels; and
a computation unit configured to perform computation using the first high definition progressive image and the prediction coefficient for each of the classes into which the subject pixels are classified to determine the second high definition progressive image, which serves as the target high definition image, from the first high definition progressive image, wherein the converter includes,
an interlace-progressive converter configured to convert the standard definition interlace image into a progressive intermediate image,
a motion-vector detector configured to detect motion vectors and macro-block differences of the standard definition interlace image by using, as a minimum unit, a distance shorter than an interval between pixels forming the progressive intermediate image,
a cyclic-coefficient setting unit configured to set, based on a vertical motion, which is a vertical component of each of the motion vectors, a first cyclic coefficient for a first type of pixel that is located at a position where a pixel forming standard definition the interlace image exists, the first cyclic coefficient calculated by using the corresponding motion vector and the macro-block difference, and a second cyclic coefficient for a second type of pixel, which is located at a position where a pixel forming the standard definition interlace image does not exist, the second cyclic coefficient calculated by using the corresponding motion vector and the macro-block difference,
a motion compensator configured to motion-compensate, on a basis of the motion vectors, a past first progressive image to generate a motion-compensated image, and
an output image generator configured to generate the first standard definition progressive image by adding pixel values of the first type of pixels located at corresponding positions of the intermediate image and the motion-compensated image by using the first cyclic coefficients as weights and by adding pixel values of the second type of pixels located at corresponding positions of the intermediate image and the motion-compensated image by using the second cyclic coefficients as weights.