Author: claimsbot

1. A semiconductor storage device comprising;
a memory cell array part including a plurality of banks;
a refresh control circuit configured to output a refresh timing control signal periodically; and
an access control circuit configured to perform a refresh operation on a group of banks which are not adjacent to one another in accordance with a preset combination of banks which are simultaneously activated and a preset activating order when the refresh timing control signal is supplied.
2. The semiconductor storage device according to claim 1, wherein the access control circuit comprises a row control circuit configured to output a row address enable signal and a sense enable signal to the group of banks in accordance with the preset combination of banks and the preset activating order when the refresh timing control signal is supplied,
each of the plurality of banks comprises a memory cell array, a row decoder and a sense amplifier,
the row decoder in the group of banks selectively activates a word line os the memory cell array in the group of banks in response to the row address enable signal, and
the sense amplifier in the group of banks activates a bit line of the memory cell array in the group of banks in response to the sense enable signal.
3. The semiconductor storage device according to claim 2, wherein the plurality of banks are arranged in M rows and N columns (each of M and N is an integer equal to or larger than 2 and M\xd7N is an even number),
the row control circuit comprises a bank activation allocation circuit, and
the bank activation allocation circuit comprises:
a refresh bank switch circuit in which X number of banks being the group of banks which are simultaneously activated by the access control circuit are allocated to the plurality of banks arranged in M rows and N columns as Y number of combinations from 1st combination to Y-th combination (each of X and Y is an integer equal to or larger than 2 and satisfying X\xd7Y=M\xd7N) which correspond to the preset activating order, and
a bank enable switch circuit configured to output the row address enable signal and the sense enable signal to the Y number of combinations from the 1st combination to Y-th combination in order in accordance with the preset combination of banks which are simultaneously activated and the preset activating order.
4. The semiconductor storage device according to claim 3, wherein the row control circuit further comprises:
an interruption refresh determination circuit configured to output an interruption refresh signal for performing the refresh operation when reading or is performed in a period where the refresh timing control signal is supplied; and
an internal refresh division circuit configured to output a refresh activation one shot signal corresponding to a frequency Z (Z is an integer satisfying 1\u2266Z\u2266Y) indicating a frequency of a supply of the interruption refresh signal, and
the bank enable switch circuit is configured to output the row address enable signal and the sense enable signal to a bank group of a Z-th combination corresponding to the refresh activation one shot signal among the Y number of combinations in accordance with the preset combination of banks which are simultaneously activated and the preset activating order.
5. The semiconductor storage device according to claim 4, wherein the internal refresh division circuit comprises:
a refresh activation frequency counter configured to count the frequency Z indicating the frequency of the supply of the interruption refresh signal; and
a refresh activation one shot circuit configured to output a refresh activation one shot signal indicating a count value of the frequency Z, and
the bank enable switch circuit is configured to output the row address enable signal and the sense enable signal to the bank group of the Z-th combination corresponding to the count value indicated by the refresh activation one shot signal among the Y number of combinations in accordance with the preset combination of banks which are simultaneously activated and the preset activating order.
6. The semiconductor storage device according to claim 5, wherein the refresh activation frequency counter is configured to be reset after a predetermined time when the count value is Y.
7. The semiconductor storage device according to claim 4, wherein the row control circuit further comprising:
a standby refresh division circuit configured to perform monitoring whether the reading or writing is performed or not in a period where the refresh timing control signal is supplied and to output standby refresh control signal indicating a result of the monitoring, and
the interrupt refresh determination circuit is configured to output the interruption refresh signal when the standby refresh control signal does not indicate that the reading or writing is performed.
8. The semiconductor storage device according to claim 3, wherein in the refresh bank switch circuit, when the Y number of combinations are assumed to be a first specification of Y number of bank groups, a second specification of Y number of bank groups which is different from the first specification in the preset combination and the preset activating order is further allocated, and
the bank enable switch circuit is configured to:
output the row address enable signal and the sense enable signal to the first specification of Y number of combinations from the 1st combination to Y-th combination in order in accordance with the preset combination of banks which are simultaneously activated and the preset activating order when a bank selection test mode entry signal is not supplied; and
output the row address enable signal and the sense enable signal to the second specification of Y number of combinations from the 1st combination to Y-th combination in order in accordance with the preset combination of banks which are simultaneously activated and the preset activating order when the bank selection test mode entry signal is supplied.
9. The semiconductor storage device according to claim 1, wherein the refresh operation is a self-refresh operation.
10. A refresh control method of a semiconductor storage device having a memory cell array part including a plurality of banks comprising:
outputting a refresh timing control signal periodically; and
performing a refresh operation on a group of banks which are not adjacent to one another in accordance with a preset combination of banks which are simultaneously activated and a preset activating order when the refresh timing control signal is supplied.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method comprising the steps of:
providing a disk drive having a disk surface with servo information written thereon, said servo information including repeatable runout;
providing position correction values to compensate for said repeatable runout, the position correction values including unintended frequency content, wherein the position correction values are calculated using a kernel and wherein the unintended frequency content in the position correction values is due to non-ideal representations of the kernel;
removing, either periodically or continuously, the unintended frequency content in the position correction values.
2. The method of claim 1 wherein the unintended frequency content is removed by periodically resetting the position correction values to zero.
3. The method of claim 2 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
4. The method of claim 1 wherein the unintended frequency content is removed by periodically reducing the position correction values.
5. The method of claim 4 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
6. The method of claim 1 wherein the unintended frequency content is removed by continuously reducing the position correction values.
7. The method of claim 6 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
8. The method of claim 1 wherein the disk drive includes a servo system and wherein the servo system has an error transfer function, the method further including the step of:
determining frequencies where the error transfer function may experience phase changes.
9. The method of claim 8 wherein the phase changes occur during a self-servo write process.
10. The method of claim 8 further including the steps of:
calculating the position correction values using a kernel;
removing frequency components from the kernel that correspond to frequencies where the error transfer function may experience phase changes.
11. A method comprising the steps of:
providing a disk drive having a disk surface with servo information written thereon, said servo information including repeatable runout, said disk drive including a servo system having an error transfer function;
determining frequencies where the error transfer function may experience phase changes and determining the direction of the phase changes;
providing a kernel, which is used to calculate position correction values to compensate for said repeatable runout;
rotating phases of frequency components in the kernel that correspond to the frequencies where the error transfer function may experience phase changes.
12. The method of claim 11, wherein the phases of the frequency components in the kernel are rotated in a direction corresponding to the phase change directions in the error transfer function.
13. The method of claim 11 wherein the phase changes in the error transfer function occur during a self-servo write process.
14. The method of claim 11 wherein kernel gain is reduced at frequency components corresponding with the rotated phases.
15. The method of claim 11 wherein the phases of the frequency components in the kernel are rotated by at least 45 degrees.
16. The method of claim 11 wherein the phases of the frequency components in the kernel are rotated by at least 60 degrees.
17. The method of claim 15 wherein not all of the phases of the frequency components in the kernel are rotated by an equal amount.
18. An apparatus comprising:
a disk drive having a disk surface with servo information written thereon, said servo information including repeatable runout;
circuitry for providing position correction values for compensating for said repeatable runout, the position correction values including unintended frequency content, wherein the position correction values are calculated using a kernel and wherein the unintended frequency content in the position correction values is due to non-ideal representations of the kernel;
circuitry for removing, either periodically or continuously, the unintended frequency content in the position correction values.
19. A disk drive comprising:
a disk surface with servo information written thereon, said servo information including repeatable runout, said disk drive including a servo system having an error transfer function;
circuitry for determining frequencies where the error transfer function may experience phase changes and determining the direction of the phase changes;
circuitry for providing a kernel, which is used to calculate position correction values to compensate for said repeatable runout;
circuitry for rotating phases of frequency components in the kernel that correspond to the frequencies where the error transfer function may experience phase changes.
20. A method comprising the steps of:
providing a disk drive having a disk surface with servo information written thereon, wherein said servo information includes repeatable runout, wherein the disk drive includes a servo system and wherein the servo system has an error transfer function;
determining frequencies where the error transfer function may experience phase changes;
providing position correction values to compensate for said repeatable runout, the position correction values including unintended frequency content;
removing, either periodically or continuously, the unintended frequency content in the position correction values.
21. The method of claim 20 wherein the unintended frequency content is removed by periodically resetting the position correction values to zero.
22. The method of claim 20 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
23. The method of claim 20 wherein the unintended frequency content is removed by periodically reducing the position correction values.
24. The method of claim 23 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
25. The method of claim 20 wherein the unintended frequency content is removed by continuously reducing the position correction values.
26. The method of claim 25 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
27. The method of claim 20 wherein the phase changes occur during a self-servo write process.
28. The method of claim 27 wherein the unintended frequency content is removed by periodically resetting the position correction values to zero.
29. The method of claim 27 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
30. The method of claim 27 wherein the unintended frequency content is removed by periodically reducing the position correction values.
31. The method of claim 29 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
32. The method of claim 27 wherein the unintended frequency content is removed by continuously reducing the position correction values.
33. The method of claim 32 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
34. The method of claim 20 further including the steps of:
calculating the position correction values using a kernel;
removing frequency components from the kernel that correspond to frequencies where the error transfer function may experience phase changes.
35. The method of claim 34 wherein the unintended frequency content is removed by periodically resetting the position correction values to zero.
36. The method of claim 34 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
37. The method of claim 34 wherein the unintended frequency content is removed by periodically reducing the position correction values.
38. The method of claim 37 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
39. The method of claim 34 wherein the unintended frequency content is removed by continuously reducing the position correction values.
40. The method of claim 39 wherein the position correction values are continuously modified, via integration, while tracking on the servo information.
41. The apparatus of claim 18 wherein the disk drive includes a servo system and wherein the servo system has an error transfer function, further including:
circuitry for determining frequencies where the error transfer function may experience phase changes.
42. The apparatus of claim 41 wherein the phase changes occur during a self-servo write process.
43. The apparatus of claim 41 further including:
circuitry for calculating the position correction values using a kernel;
circuitry for removing frequency components from the kernel that correspond to frequencies where the error transfer function may experience phase changes.
44. An apparatus comprising:
a disk drive having a disk surface with servo information written thereon, wherein said servo information includes repeatable runout, wherein the disk drive includes a servo system and wherein the servo system has an error transfer function;
circuitry for determining frequencies where the error transfer function may experience phase changes;
circuitry for providing position correction values for compensating for said repeatable runout, the position correction values including unintended frequency content;
circuitry for removing, either periodically or continuously, the unintended frequency content in the position correction values.
45. The apparatus of claim 44 wherein the phase changes occur during a self-servo write process.
46. The apparatus of claim 44 further including:
circuitry for calculating the position correction values using a kernel;
circuitry for removing frequency components from the kernel that correspond to frequencies where the error transfer function may experience phase changes.
47. The disk drive of claim 19 wherein the phases of the frequency components in the kernel are rotated in a direction corresponding to the phase change directions in the error transfer function.
48. The desk drive of claim 19 wherein the phase changes in the error transfer function occur during a self-servo write process.
49. The disk drive of claim 19 wherein kernel gain is reduced at frequency components corresponding with the rotated phases.
50. The disk drive of claim 19 wherein the phases of the frequency components in the kernel are rotated by at least 45 degrees.
51. The disk drive of claim 19 wherein the phases of the frequency components in the kernel are rotated by at least 60 degrees.
52. The disk drive of claim 50 wherein not all of the phases of the frequency components in the kernel are rotated by an equal amount.

1-13. (canceled)
14. A method of operating an integrated metal-insulator-semiconductor (MIS) capacitor of the type having a first capacitor and a second capacitor, wherein each of said first and second capacitors has a first region of a first conductivity type, adjacent to a channel region of the first conductivity type, in the same semiconductor substrate, wherein each of said channel region characterized by a threshold voltage, a gate electrode insulated and spaced apart from the channel region, wherein the gate of the first capacitor is electrically connected to the first region of the second capacitor, and the gate of the second capacitor is electrically connected to the first region of the first capacitor; wherein said method comprising:
periodically setting the gate electrode of the first capacitor to an accumulation bias, wherein the period is less than the time constant for the formation of an inversion layer in the channel of the first capacitor.
15. The method of claim 14 wherein said setting comprises applying a voltage between the gate electrode of the first capacitor and the first region of the first capacitor wherein said voltage biases said first capacitor below the threshold voltage of said channel of first capacitor.
16. The method of claim 15 further comprising:
periodically applying a voltage between the gate electrode of the second capacitor and the first region of the second capacitor wherein said voltage biases said second capacitor below the threshold voltage, wherein said voltage is applied periodically with a period less than the time constant for the formation of an inversion layer in said channel region.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-7. (canceled)
8. A computer program product for analytic solution integration, the computer program product comprising:
a computer readable storage medium having computer readable program code embodied therewith, said program code being executable by a processor to perform a method comprising:
establishing an engine abstraction layer configured to interface with a plurality of analytic engines associated with a plurality of models;
interfacing a services layer with the engine abstraction layer to provide a communication interface to invoke the analytic engines associated with the models; and
providing a user interface to the services layer, the user interface configured to define an analytic solution as an executable sequence of one or more of the models.
9. The computer program product of claim 8, wherein at least one of the models is an analytic model, and further comprising:
defining a schema associated with the analytic model as data that are available in the analytic model; and
performing input data validation for the analytic model based on the schema.
10. The computer program product of claim 8, wherein the models include representations of one or more of a descriptive, prescriptive, or predictive solution to a problem.
11. The computer program product of claim 8, wherein the services layer provides representational state transfer web services that support direct invocation by an enterprise application and an administrative console that provides the user interface.
12. The computer program product of claim 8, further comprising:
providing analytics solutions that include a combination of transportation analytics, energy and utility analytics, building analytics, and cross industry analytics.
13. The computer program product of claim 8, further comprising:
registering, deploying, executing, and monitoring the models through the services layer; and
storing registered data in a metadata repository that is accessible through one of: a file system and a database system.
14. The computer program product of claim 8, further comprising:
providing a common logging interface across the plurality of analytic engines.
15. A system for analytic solution integration, the system comprising:
a processor; and
an analytics solution kit executable by the processor to perform a method comprising:
establishing an engine abstraction layer configured to interface with a plurality of analytic engines associated with a plurality of models;
interfacing a services layer with the engine abstraction layer to provide a communication interface to invoke the analytic engines associated with the models; and
providing a user interface to the services layer, the user interface configured to define an analytic solution as an executable sequence of one or more of the models.
16. The system of claim 15, wherein at least one of the models is an analytic model, and the analytics solution kit is further configured to perform:
defining a schema associated with the analytic model as data that are available in the analytic model; and
performing input data validation for the analytic model based on the schema.
17. The system of claim 15, wherein the services layer provides representational state transfer web services that support direct invocation by an enterprise application and an administrative console that provides the user interface.
18. The system of claim 15, wherein the analytics solution kit is further configured to perform:
providing analytics solutions that include a combination of transportation analytics, energy and utility analytics, building analytics, and cross industry analytics.
19. The system of claim 15, wherein the analytics solution kit is further configured to perform:
registering, deploying, executing, and monitoring the models through the services layer; and
storing registered data in a metadata repository that is accessible through one of: a file system and a database system.
20. The system of claim 15, wherein the analytics solution kit is further configured to perform:
providing a common logging interface across the plurality of analytic engines.