Author: claimsbot

1. A liquid crystal display apparatus, comprising:
a first substrate comprising a pixel area;
a second substrate facing the first substrate;
a liquid crystal layer comprising liquid crystals interposed between the first substrate and the second substrate;
a pixel electrode positioned in the pixel area and comprising a cut-out pattern;
a conductive pattern arranged between the first substrate and the pixel electrode, the conductive pattern partially overlapping the cut-out pattern when viewed from a plan view;
a common electrode disposed on the second substrate; and
a light blocking member arranged on any one of the first substrate and the second substrate, the light blocking member positioned corresponding to an area in which the cut-out pattern overlaps the conductive pattern within the pixel area.
2. The liquid crystal display apparatus of claim 1, wherein the conductive pattern comprises at least one of a gate line and a data line.
3. The liquid crystal display apparatus of claim 2, wherein the gate line is disposed in a first direction substantially parallel to a short lateral side of the pixel electrode, and the data line passes through the pixel area and crosses the gate line.
4. The liquid crystal display apparatus of claim 3, wherein the pixel electrode extends in a second direction at an angle to a first direction and in a third direction symmetrical to the second direction with respect to the first direction.
5. The liquid crystal display apparatus of claim 4, wherein the light blocking member is positioned corresponding to an area in which the data line overlaps the cut-out pattern.
6. The liquid crystal display apparatus of claim 4, further comprising a light blocking layer pattern disposed on the second substrate and positioned corresponding to a boundary of the pixel area.
7. The liquid crystal display apparatus of claim 6, wherein the light blocking member is disposed on the second substrate, spaced apart from the light blocking layer pattern, and comprises the same material as the light blocking layer pattern.
8. The liquid crystal display apparatus of claim 7, wherein the second substrate comprises a color filter disposed between the light blocking member and the common electrode, the first substrate comprises a protection layer covering the data line, and the light blocking member is positioned corresponding to an area in which the data line overlaps the cut-out pattern.
9. The liquid crystal display apparatus of claim 8, wherein the first substrate further comprises a semiconductor pattern disposing between the first substrate and the data line, and the semiconductor pattern overlaps the data line.
10. The liquid crystal display apparatus of claim 7, wherein the light blocking member and the light blocking layer pattern are formed simultaneously through the same process.
11. The liquid crystal display apparatus of claim 4, further comprising a thin film transistor comprising:
a gate electrode branching from the gate line,
a source electrode branching from the data line, and
a drain electrode spaced apart from the source electrode and connected to the pixel electrode.
12. The liquid crystal display apparatus of claim 11, wherein the light blocking member comprises:
a floating electrode disposed on the first substrate, the floating electrode spaced apart from the gate electrode, and
the same material as the gate electrode.
13. The liquid crystal display apparatus of claim 12, wherein the second substrate comprises a color filter disposed between the second substrate and the common electrode, the first substrate comprises a protection layer covering the data line, and the light blocking member is positioned corresponding to an area in which the data line overlaps the cut-out pattern.
14. The liquid crystal display apparatus of claim 13, wherein the first substrate further comprises a semiconductor pattern disposing between the first substrate and the data line, and the semiconductor pattern overlaps the data line.
15. The liquid crystal display apparatus of claim 12, wherein the light blocking member and the gate electrode are formed simultaneously through the same process.
16. The liquid crystal display apparatus of claim 4, wherein the pixel electrode comprises a first pixel electrode and a second pixel electrode to receive different voltages, the first pixel electrode and the second pixel electrode being spaced apart from each other.
17. The liquid crystal display apparatus of claim 16, wherein the cut-out pattern is positioned in a region between the first pixel electrode and the second pixel electrode.
18. The liquid crystal display apparatus of claim 4, wherein the cut-out pattern comprises:
a first cut-out pattern extending in the first direction;
a second cut-out pattern extending in the second direction; and
a third cut-out pattern extending in the third direction.
19. The liquid crystal display apparatus of claim 18, wherein the light blocking member covers an area where the data line overlaps the second cut-out pattern and the third cut-out pattern.
20. The liquid crystal display apparatus of claim 19, wherein the light blocking member covering the second cut-out pattern has a rectangular shape comprising a long lateral side substantially parallel to the second direction, and the light blocking member covering the third cut-out pattern has a rectangular shape comprising a long lateral side substantially parallel to the third direction.
21. The liquid crystal display apparatus of claim 19, wherein the light blocking member covering the second cut-out pattern and the third cut-out pattern has a circular shape.
22. The liquid crystal display apparatus of claim 4, wherein the common electrode comprise a domain divider dividing the pixel area into a plurality of domains.
23. The liquid crystal display apparatus of claim 22, wherein the domain divider is a cut-out pattern or a protrusion disposed on a portion of the common electrode.
24. The liquid crystal display apparatus of claim 23, wherein the domain divider comprises:
a first domain divider extending in the first direction;
a second domain divider extending in the second direction; and
a third domain divider extending in the third direction.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A motorcycle helmet comprising:
an outer shell; and
a chin bar;
wherein said chin bar comprises:
a chin bar pad;
said chin bar pad comprising;
an inlet duct adapted to receive air flow; and
a ridged duct portion, wherein said ridged duct portion is fluidically coupled to said inlet duct.
2. The motorcycle helmet of claim 1, wherein said ridged duct portion is predominantly located along the interior surface of said chin bar pad.
3. The motorcycle helmet of claim 1, further comprising a cheek pad, said cheek pad attached to the interior surface of said chin bar pad.
4. The motorcycle helmet of claim 3, wherein said ridged duct portion is predominantly located along the interior surface of said chin bar pad.
5. The motorcycle helmet of claim 3, wherein said cheek pad comprises a cheek pad base.
6. The motorcycle helmet of claim 5 wherein said cheek pad further comprises a cheek pad cushion.
7. The motorcycle helmet of claim 6, wherein said cheek pad base comprises holes in its structure.
8. The motorcycle helmet of claim 7, wherein said holes are aligned predominantly along the depressions of said ridged duct portion.
9. The motorcycle helmet of claim 7 wherein said cheek pad base is in physical contact with said ridged duct portion.
10. A helmet comprising:
an outer shell; and
a chin bar;
wherein said chin bar comprises:
a chin bar pad;
said chin bar pad comprising;
an inlet duct adapted to receive air flow; and
a ridged duct portion, wherein said ridged duct portion is fluidically coupled to said inlet duct.
11. The helmet of claim 10, wherein said ridged duct portion is predominantly located along the interior surface of said chin bar pad.
12. The helmet of claim 11, wherein said ridged duct portion comprises a plurality of ridged ducts, some of said plurality of ridged ducts fluidically coupled to said inlet duct on one end of the ducts and fluidically coupled to the front opening of said helmet on the other end of the ducts.
13. The helmet of claim 11, wherein said ridged duct portion comprises a plurality of ridged ducts, some of said plurality of ridged ducts fluidically coupled to said inlet duct on one end of the ducts and fluidically coupled to the bottom of said helmet on the other end of the ducts.
14. The helmet of claim 10, wherein said ridged duct portion is predominantly located along the exterior surface of said chin bar pad between said chin bar pad and said outer shell.
15. The helmet of claim 14, wherein said ridged duct portion comprises a plurality of ridged ducts, some of said plurality of ridged ducts fluidically coupled to said inlet duct on one end of the ducts and fluidically coupled to the front opening of said helmet on the other end of the ducts.
16. The helmet of claim 14, wherein said ridged duct portion comprises a plurality of ridged ducts, some of said plurality of ridged ducts fluidically coupled to said inlet duct on one end of the ducts and fluidically coupled to the bottom of said helmet on the other end of the ducts.
17. The helmet of claim 15 wherein said plurality of ridged duct are fluidically coupled to the interior surface of said chin bar pad by holes through said chin bar pad.
18. The helmet of claim 16 wherein said plurality of ridged ducts are fluidically coupled to the interior surface of said chin bar pad by holes through said chin bar pad.
19. A motorcycle helmet comprising:
an outer shell; and
a chin bar;
wherein said chin bar comprises a chin bar pad,
said chin bar pad comprising a ridged duct portion.

1. A device for recovering electric energy in an AC motor-driven electric vehicle, the device comprising:
a) a battery;
b) a single-phase or three-phase inverter;
c) a single-phase or three-phase inductor, the single-phase or three-phase inductor comprising a primary coil and a secondary coil;
d) an AC motor;
e) a rectifier bridge or a second inverter; and
f) a charger;

wherein
an anode and a cathode of the battery are connected to input ends of the single-phase or three-phase inverter, respectively; an output end of the single-phase or three-phase inverter is connected to the AC motor via the primary coil of the single-phase or three-phase inductor;
an output end of the secondary coil of the single-phase or three-phase inductor is connected to an input end of the rectifier bridge or the second inverter; output ends of the rectifier bridge are connected to the anode and the cathode of the battery, respectively;
the inductor is employed to rectify the current and regulate the voltage; the primary coil of the single-phase or three-phase inductor is in series connection with the load of the AC motor; when the AC motor works, the current and the voltage on the primary coil of the single-phase or three-phase inductor produce an electromagnetic induction and influence the secondary coil of the single-phase or three-phase inductor to produce the AC current and voltage on the secondary coil; the AC current and voltage is further rectified and inverted into a direct current by the rectifier bridge or the second inverter, and the direct current is input to the battery for electric energy recovery; and
the charger is connected to the anode and the cathode of the battery for supplying power from an external power supply.
2. The device of claim 1, wherein
the single-phase or three-phase inductor comprises: a magnetic core, a coil, a mounting bracket, a skeleton, and an insulating material; and
the single-phase or three-phase inductor is assembled by winding the coil on the skeleton, inserting the magnetic core inside the coil, fixing the coil on the mounting bracket, and using the insulating material for package.
3. The device of claim 2, wherein the coil is made of an enamel-covered wire or an insulating conductive material.
4. The device of claim 1, wherein the AC motor is provided with a speed controller for controlling a rotary speed of the AC motor.
5. The device of claim 1, wherein the battery is a battery pack or a single battery.
6. The device of claim 1, wherein the battery comprises a power manager for management of charging and discharging of the battery.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A device, comprising:
a silicon substrate;
a semiconducting fin extending outward from a top surface of the silicon substrate to a fin height, the fin including a channel of the device;
a source extending above the silicon substrate to a source height and in a transverse orientation with respect to the fin, the source abutting a first end of the fin, the source doped so as to supply charge to the channel;
a drain extending above the silicon substrate to a drain height and in a transverse orientation with respect to the fin, the drain abutting a second end of the fin, the drain doped so as to drain charge from the channel; and
a gate structure wrapping around at least three sides of the fin, the gate structure configured to control current in the channel in response to an applied voltage.
2. The device of claim 1 wherein the fin height, the source height, and the drain height are substantially equal.
3. The device of claim 1 wherein the fin, source, and drain are portions of a single contiguous layer on top of the silicon substrate.
4. The device of claim 1 wherein the fin, source, and drain are portions of a top layer of the silicon substrate.
5. The device of claim 1 wherein the gate structure is a dual gate having two independent nodes separated by an insulator, each of the independent nodes being capacitively coupled to the channel.
6. The device of claim 1, further comprising additional semiconducting fins extending between the source and drain, each of the additional fins including a channel, the gate structure wrapping around at least three sides of each additional fin and providing a single electrical node that controls current flow in the channels in response to the applied voltage.
7. The device of claim 6 wherein the fins are coupled to a common source and a common drain.
8. The device of claim 1 wherein the gate structure includes at least one gate electrode and a gate oxide disposed between the gate electrode and the channel.
9. The device of claim 1 wherein the substrate includes one or more of a buried oxide layer, a strained silicon layer, and a strained heterostructure layer.
10. The device of claim 1 wherein the silicon substrate includes components that impart strain to at least one channel.
11. The device of claim 1 wherein the silicon substrate is a fully-depleted silicon-on-insulator substrate.
12. An integrated circuit including a plurality of devices as claimed in claim 6, wherein no trench isolation structures exist in the substrate between adjacent ones of the plurality of devices.
13. The integrated circuit of claim 12, further comprising metal interconnects coupling a plurality of the devices, the metal interconnects made of a same material as the gate electrode.
14. The integrated circuit of claim 13 wherein the metal interconnects coupling a plurality of the devices include doped contacts.
15. A static read-only memory cell, comprising:
pairs of n-type FinFETs in which respective fins, source regions, and drain regions are portions of a same layer on top of a silicon substrate; and
pairs of p-type FinFETs in which respective fins, source regions, and drain regions are portions of the same layer,
the pairs of n-type FinFETs and the pairs of p-type FinFETs arranged to form cross-coupled inverters.
16. The memory cell of claim 15 wherein each pair of FinFETs is configured as a dual gate device in which current flow in a single channel is controlled by two independent nodes.
17. A memory cell array that includes static read-only-memory cells according to claim 15, the memory cells arranged in rows and columns, and the memory cells being electrically accessible via control lines coupling the rows and columns.
18. The memory cell array of claim 17 wherein the memory cells further comprise local interconnects having doped contacts, wherein portions of the control lines include portions of the local interconnects.
19. The memory cell of claim 15 wherein the single layer of silicon is a strained silicon layer.
20. The memory cell of claim 19 in which the strained silicon layer includes SiGe.