Author: claimsbot

1. A method of processing an interrupt disable instruction included in a program instruction sequence, comprising:
fetching an interrupt disable instruction from the sequence including an operand specifying a number of cycles for disabling interrupt processing; and
executing the instruction.
2. The method according to claim 1 wherein the instruction operand is the number.
3. The method according to claim 1 wherein the instruction operand is a pointer to the number.
4. The method according to claim 3, wherein the pointer is stored in a register.
5. The method according to claim 1, wherein the operand identifies a register that stores the number.
6. The method according to claim 1, further comprising loading the number into a register.
7. The method according to claim 6, further comprising changing the number stored in the register based on processor cycles until the number reaches a predetermined value.
8. The method according to claim 7, wherein the changing is decrementing the number stored in the register.
9. The method according to claim 7, wherein the changing is incrementing the number stored in the register.
10. The method according to claim 7, wherein the predetermined value is zero.
11. The method according to claim 7, further comprising generating an interrupt disable signal during the changing of the number.
12. The method according to claim 11, further comprising generating an interrupt enable signal when the number reaches a predetermined value.
13. The method according to claim 7, further comprising writing the register with a value based on a write instruction.
14. A processor including an interrupt disable instruction processing feature, comprising:
a program memory for storing instructions including an interrupt disable instruction having an operand specifying a number corresponding to an interrupt disable duration;
a register for storing the number;
an instruction fetchdecode unit for fetching and decoding instructions, the instruction fetchdecode unit decoding the interrupt disable instruction and disabling the interrupt processing capability of the processor based on the number.
15. The processor according to claim 14, wherein the register changes the number based on processor cycles.
16. The processor according to claim 15, wherein the register changes the number by incrementing it.
17. The processor according to claim 15, wherein the register changes the number by decrementing it.
18. The processor according to claim 15, wherein the disabling the interrupt processing capability ends when the number reaches zero.
19. The processor according to claim 15, further comprising:
interrupt disable logic, coupled to the register, the interrupt disable logic generating an interrupt disable signal during the changing of the number.
20. The processor according to claim 15, wherein the interrupt disable logic generates an interrupt disable until the number reaches a predetermined value.
21. The processor according to claim 15, wherein a write instruction updates the register.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A cutter assembly for a rotary shear shredder comprising
a plural-cutting-tool, rotary carrier having a body possessing a rotational axis and a plural-tool-carrying periphery distributed about said axis,
for each tool which is to be carried by said carrier, an associated, radially-outwardly-extending, radial projection formed at a location on and projecting from said periphery,
for each said projection, an associated shear cutting tool having radially spaced, opposite faces,
a projection-receiving void space, complementary to said projection, formed in each said tool and opening to each of said faces, and,
defined collectively by and for each associated, projection and complementary void space, a sliding-friction, reversible-heat-cycle, connectiondisconnection, binding interface removably anchoring said tool directly to said carrier body at said location, and accommodating connection and disconnection between the carrier body and said tool along a line which is radial relative to said rotational axis.

1. A digital phase lock loop, comprising:
a digitally controlled oscillator controlled by an oscillator tuning word to generate a variable signal, wherein the oscillator tuning word comprises a first tuning word and a second tuning word, wherein a second tuning word adjustable frequency range of the digitally controlled oscillator is broader than a first tuning word adjustable frequency range of the digitally controlled oscillator;
a phase detector arranged to measure a phase error between the variable signal and a reference signal; and
a loop filter arranged to generate the oscillator tuning word in response to the phase error, wherein the loop filter comprises:
a plurality of low pass filter stages, including a front low pass filter and a back low pass filter; and

a modification circuit arranged to adjust the second tuning word based on an output from at least one of the front low pass filter and the back low pass filter, wherein the modification circuit comprises a first decision circuit configured to output a first variation based on the filter output of the back low pass filter, a second decision circuit configured to output a second variation based on the filter output of the front low pass filter, and an accumulator configured to adjust the second tuning word based on accumulated differences between the first variation and the second variation.
2. The digital phase lock loop as claimed in claim 1, wherein the digitally controlled oscillator comprises:
a plurality of first capacitors with the same capacitance, controlled by the first tuning word; and
a plurality of second capacitors controlled by the second tuning word, wherein the capacitance of each second capacitor is larger than the capacitance of the first capacitor.
3. The digital phase lock loop as claimed in claim 1, wherein the oscillator tuning word further comprises a third tuning word, wherein a third tuning word adjustable frequency range of the digitally controlled oscillator is broader than the second tuning word adjustable frequency range, the modification circuit is a first modification circuit, and the digital phase lock loop further comprises:
a second modification circuit configured to directly detect two filter outputs from two low pass filters and adjust the third tuning word based upon a predetermined condition.
4. The digital phase lock loop as claimed in claim 3, wherein the output of the front low pass filter received by the first modification circuit is a back filter output received by the second modification circuit.
5. The digital phase lock loop as claimed in claim 3, wherein the front filter output received by the first modification circuit is not the back filter output received by the second modification circuit.
6. The digital phase lock loop as claimed in claim 1, wherein the loop filter further comprises a multiplier serving as a loop gain to adjust the oscillator tuning word.
7. The digital phase lock loop as claimed in claim 1, wherein each low pass filter is an infinite impulse response filter or a finite impulse response filter.
8. A control method for a phase lock loop, comprising:
low pass filtering a phase error to generate an oscillator tuning word to control a digitally controlled oscillator, wherein the oscillator tuning word comprises a first tuning word and a second tuning word, and a second tuning word adjustable frequency range of the digitally controlled oscillator being broader than a first tuning word adjustable frequency range;
generating two filter outputs, wherein a first filter output is of a front low pass filter and a second filter output is of a back low pass filter; and
adjusting the second tuning word when the two filter outputs meet a predetermined condition.
9. The method as claimed in claim 8, wherein the oscillator tuning word further comprises a third tuning word, the frequency range of the digitally controlled oscillator, capable to be adjusted by the third tuning word, is broader than the adjustable range provided by the second tuning word, the method further comprises:
detecting two filter outputs of another front low pass filter and another back low pass filter; and
adjusting the third tuning word when the two filter outputs of the another front low pass filter and the another back low pass filter meet another predetermined condition.
10. The method as claimed in claim 8, further comprising:
adjusting the oscillator tuning word using a loop gain.
11. The method as claimed in claim 10, wherein the loop gain is a first loop gain, and the method further comprises:
adjusting a last filter output by decreasing the loop gain when the predetermined condition is met.
12. The method as claimed in claim 8, wherein the step of adjusting the second tuning word comprises:
adjusting the second tuning word in a first direction if the output of the front low pass filter exceeds a first predetermined value;
adjusting the second tuning word in a second direction opposite to the first direction if the output of the front low pass filter is lower than a second predetermined value;
adjusting the second tuning word in the second direction if the output of the back low pass filter exceeds a third predetermined value;
adjusting the second tuning word in the first direction if the output of the back low pass filter is lower than a fourth predetermined value; and
stopping adjustment of the second tuning word if the value of an accumulator has not changed for a predetermined period of time.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A gallium nitride (GaN) based light-emitting device (LED), comprising:
a light-emitting body comprising a GaN-based material capable of emitting a light; and
a light extraction layer comprising:
a current spreading layer disposed over said light-emitting body; and
a micro-structure layer disposed over said current spreading layer and being a Pt layer having metal clusters.
2. The LED according to claim 1, wherein said light-emitting body comprises an n-type GaN-based layer, a semiconductor active layer and a p-type GaN-based layer and said semiconductor active layer is disposed over said n-type GaN-based layer and said p-GaN-based layer is disposed over said active layer.
3. The LED according to claims 1 or 2, wherein said light-emitting body has a p-type electrode and an n-type electrode and said p-type electrode is disposed over said micro-structure layer.
4. The LED according to claim 3, wherein said p-type electrode is disposed beside said micro-structure layer and said current spreading layer.
5. The LED according to claim 1, wherein said Pt layer having metal clusters is formed by annealing a Pt layer.