Author: claimsbot

1. A method, comprising:
receiving a message that a call has been made to a destination;
determining that the destination is not available;
providing a menu of options for receiving content while the destination is not available;
receiving a selection of one of the menu options; and
providing content according to the selection.
2. The method of claim 1, wherein a calling party uses one of an analog telephone, a digital telephone, and a digital telephony device to make the call.
3. The method of claim 1, wherein the destination is one of a human and an interactive voice response (IVR) application.
4. The method of claim 1, further comprising providing a notification to a point of origin that the destination is unavailable.
5. The method of claim 1, further comprising retrieving the content from a content library.
6. The method of claim 1, further comprising:
determining that the destination is available; and
providing a connection between a point of origin and the destination.
7. The method of claim 1, wherein the content is audio content.
8. The method of claim 1, wherein the menu is provided by an interactive voice response unitintelligent peripheral.
9. The method of claim 1, wherein the message is received via Signaling System 7 (SS7) signaling.
10. The method of claim 1, wherein determining that the destination is not available includes using one of an advanced intelligent network, a private branch exchange, and an automated call distribution system.
11. The method of claim 1, tangibly embodied as computer-executable instructions stored on one or more computer-readable media.
12. The method of claim 1, wherein the content is one or more of music, news, and an advertisement.
13. A system, comprising:
at least a first computing device configured to receive a message that a call has been made to a destination and to determine whether the destination is available;
a content library including electronic content;
a second computing device distinct from said first computing device in selective communication with the content library, the second computing device configured to:
receive a message from the first computing device that the destination is unavailable;
provide a menu of options for receiving content;
receive a selection of one of the menu options; and
provide content from the content library according to the selection.
14. The system of claim 13, wherein a calling party uses one of an analog telephone, a digital telephone, and a digital telephony device to make the call.
15. The system of claim 13, wherein said first computing device is one of an advanced intelligent network, a private branch exchange, and an automated call distribution system.
16. The system of claim 13, wherein said second computing device is an interactive voice response unitintelligent peripheral.
17. The system of claim 13, wherein the electronic content is one of music, news, and an advertisement.
18. The system of claim 13, wherein the message is received via Signaling System 7 (SS7) signaling.
19. A system, comprising:
an advanced intelligent network (AIN) configured to receive a message that a calling party has made a call to a called telephone and to determine whether the called party is available;
a content library including electronic content; and
an interactive voice response unitintelligent peripheral in selective communication with the content library, the interactive voice response unitintelligent peripheral configured to:
receive a message from the AIN that the called party is unavailable;
provide to the calling party a menu of options for receiving content;
receive a selection of one of the menu options from the calling party; and
provide content to the calling party according to the content selection.
20. The system of claim 19, wherein at least one of a calling telephone and a called telephone is one of an analog telephone, a digital telephone, and a digital telephony device.
21. The system of claim 19, wherein the electronic content is one of music, news, and an advertisement.
22. The system of claim 19, wherein the message is received via Signaling System 7 (SS7) signaling.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of processing a wafer using a Post Application Bake (PAB)) procedure, the method comprising:
transferring a plurality of selected wafers to one or more deposition modules, wherein a plurality of coated wafers are created by depositing a first material layer on each of the selected wafers;
transferring at least one coated wafer to an inspection module coupled to at least one of the deposition modules, wherein pre-processing inspection data is determine by the inspection module;
transferring a first coated wafer to a bake plate in a thermal processing unit coupled to one or more of the deposition modules, wherein a first wafer thermal profile is established for the first coated wafer using a pre-heated bake plate;
determining first exhaust gas data (EG1) for the first coated wafer at a first processing time (t1), wherein the bake plate is configured within a processing chamber in the thermal processing unit and an Exhaust Gas Analyzer (EGA) subsystem is coupled to a top portion of the processing chamber, the EGA subsystem being configured to determine the first exhaust gas data (EG1);
comparing the first exhaust gas data (EG1) to processing limits established for the first coated wafer;
continuing to process the first coated wafer if the first exhaust gas data (EG1) does not exceed at least one of the processing limits established for the first coated wafer; and
stopping the PAB procedure if the first exhaust gas data (EG1) exceeds one or more of the processing limits established for the first coated wafer.
2. The method of claim 1, wherein continuing to process the first coated wafer further comprises:
determining new exhaust gas data (EGn) for the first coated wafer at a new processing time (tn), wherein the bake plate is configured to heat the first coated wafer during the new processing time (tn), the EGA subsystem being configured to determine the new exhaust gas data (EGn) during the new processing time (tn);
comparing the new exhaust gas data (EGn) to new processing limits established for the first coated wafer;
continuing to perform the PAB procedure if the new exhaust gas data (EGn) does not exceed at least one of the new processing limits established for the first coated wafer; and
stopping the PAB procedure if the new exhaust gas data (EGn) exceeds one or more of the new processing limits established for the first coated wafer.
3. The method of claim 2, wherein continuing to perform the PAB procedure further comprises:
storing the new exhaust gas data (EGn) and an associated new processing time (tn);
establishing a new integer counting variable (n+1);
comparing new integer counting variable (n+1) to a counting variable limit (PN) established for the first coated wafer;
continuing to perform the PAB procedure if the new integer counting variable (n+1) does not exceed the counting variable limit (PN) established for the first coated wafer; and
stopping the PAB procedure if the new integer counting variable (n+1) exceeds the counting variable limit (PN) established for the first coated wafer.
4. The method of claim 1, wherein the first material layer comprises organic material, non-organic material, radiation-sensitive material, non-radiation-sensitive material, solvent material, photoresist material, or anti-reflective coating (ARC) material, or any combination thereof.
5. The method of claim 1, further comprising:
determining if the first coated wafer is on the bake plate using the first exhaust gas data (EG1); and
stopping the PAB procedure when the wafer is not on the bake plate.
6. The method of claim 1, further comprising:
determining if a correct first material layer is on the first coated wafer using the first exhaust gas data (EG1); and
stopping the PAB procedure when the correct first material layer is not on the first coated wafer.
7. The method of claim 1, wherein the first exhaust gas data (EG1) includes concentration data for gas components associated with top coat (TC) barrier material, top antireflective coating (TARC) material, bottom antireflective coating (BARC) material, photoresist material, sacrificial material, filler material, barrier material, poly-gate material, or metal gate material, or any combination thereof.
8. The method of claim 1, wherein the first exhaust gas data (EG1) includes wavelength data for gas components associated with top coat (TC) barrier material, top antireflective coating (TARC) material, bottom antireflective coating (BARC) material, photoresist material, sacrificial material, filler material, barrier material, poly-gate material, or metal gate material, or any combination thereof.
9. The method of claim 1, wherein the first exhaust gas data (EG1) includes concentration data for gas components associated with solvents for top coat (TC) barrier material, solvents for top antireflective coating (TARC) material, solvents for bottom antireflective coating (BARC) material, solvents for photoresist material, solvents for sacrificial material, solvents for filler material, solvents for barrier material, solvents for poly-gate material, or solvents for metal gate material, or any combination thereof.
10. A method of processing a plurality of wafers using a Post Application Bake (PAB)) teaching procedure, the method comprising:
a) initializing the PAB teaching procedure, wherein a first counting variable (n) and a teaching limit (TN) are established for each teaching time (tn), the first counting variable (n) having an integer value greater than zero, the teaching limit (TN) being an integer having a value greater than ten, wherein a second counting variable (m) and a counting limit (WM) are established for coated wafers (Wm), the second counting variable (m) having an integer value greater than zero, the counting limit (WM) being an integer having a value greater than three;
b) establishing a first value (n=1) for a first PAB teaching time (t1), wherein an initial value (m=1) is determined for a first PAB teaching wafer (TW1);
c) establishing an (nth) teaching bake plate temperature profile (TBPTPn) for a bake plate during an (nth) PAB teaching time (tn), wherein an (mth) coated teaching wafer (TWm) is positioned on the bake plate and (nth) teaching input powers (TIPn) are provided to at least one resistance heater embedded in the bake plate during the (nth) PAB teaching time (tn);
d) determining (nth) teaching exhaust gas data (TEGn) for the (mth) coated teaching wafer (TWm) during the (nth) PAB teaching time (tn), wherein an (nth) wafer temperature profile (WTPn) is established for the (mth) coated teaching wafer (TWm) during the (nth) PAB teaching time (tn), and an Exhaust Gas Analyzer (EGA) subsystem is coupled to a top portion of a processing chamber, the EGA subsystem being configured to determine the (nth) teaching exhaust gas data (TEGn) for the (mth) coated teaching wafer (TWm) during the (nth) PAB teaching time (tn);
e) determining if the (nth) teaching exhaust gas data (TEGn) exceeds one or more (nth) teaching exhaust gas limits (TEGLn) during the (nth) PAB teaching time (tn);
f) performing an (nth) corrective action (CAn) when the (nth) teaching exhaust gas data (TEGn) exceeds one or more (nth) teaching exhaust gas limits (TEGLn) during the (nth) PAB teaching time (tn);
g) establishing a new first counting variable (n+1) by incrementing the first counting variable (n), wherein the new first counting variable (n+1) is compared to the teaching limit (TN) established for the (mth) coated teaching wafer (TWm);
h) repeating steps c-g, when the new first counting variable (n+1) does not exceed the teaching limit (TN) established for the (mth) coated teaching wafer (TWm);
i) establishing a new second counting variable (m+1) by incrementing the second counting variable (m), when the new first counting variable (n+1) exceeds the teaching limit (TN) established for the (mth) coated teaching wafer (TWm);
j) repeating steps b-i, using a new coated teaching wafer (TWm+1) when the new second counting variable (m+1) does not exceed the counting limit (WM) established for the PAB teaching procedure; and
m) stopping the PAB teaching procedure when the new second counting variable (m+1) exceeds the counting limit (WM) established for the PAB teaching procedure.
11. The method of claim 10, wherein the new exhaust gas data (EGn) and new PAB processing time (tn) are stored before the PAB teaching procedure is stopped.
12. The method of claim 10, wherein the (nth) corrective action (CAn) includes providing new teaching input power (NIPTn) values to one or more resistance heaters embedded in the bake plate.
13. The method of claim 10, wherein the (nth) corrective action (CAn) includes: updating at least one bake plate temperature profile (BPTPn+1) that is to be established for the bake plate during a next processing time (tn+1); updating an input power (IPn+i) that is to be provided to one or more resistance heaters embedded in the bake plate during the for the next processing time (tn+1); and storing the updated bake plate temperature profile (BPTPn+1) and the updated input power (IPn+1).
14. The method of claim 10, wherein first teaching exhaust gas data (TEG1) is determined for a coated teaching wafer during the first PAB teaching time (t1); the first teaching exhaust gas data (TEG1) is compared to historical exhaust gas data to determine if the coated teaching wafer is correctly positioned on a pre-heated bake plate and if the coated teaching wafer has a correct material layer thereon; and the PAB teaching procedure is stopped when the coated teaching wafer is not correctly positioned on the pre-heated bake plate or when the coated teaching wafer has an incorrect material layer thereon.
15. The method of claim 10, wherein each coated teaching wafer includes organic material, non-organic material, radiation-sensitive material, non-radiation-sensitive material, solvent material, photoresist material, barrier material, anti-reflective coating (ARC) material, bottom antireflective coating (BARC) material, top antireflective coating (TARC) material, sacrificial material, filler material, ceramic material, poly-gate material, or metal gate material, or any combination thereof deposited on a semiconductor layer.
16. The method of claim 10, wherein the (nth) teaching exhaust gas data (TEGn) includes concentration data for gas components associated with top coat (TC) barrier material, top antireflective coating (TARC) material, bottom antireflective coating (BARC) material, photoresist material, sacrificial material, filler material, barrier material, poly-gate material, or metal gate material, or any combination thereof.
17. The method of claim 10, wherein the (nth) teaching exhaust gas data (TEGn) includes wavelength data for gas components associated with top coat (TC) barrier material, top antireflective coating (TARC) material, bottom antireflective coating (BARC) material, photoresist material, sacrificial material, filler material, barrier material, poly-gate material, or metal gate material, or any combination thereof.
18. The method of claim 10, wherein pre-processing inspection data is obtained for a first coated teaching wafer (TW1) before the first coated teaching wafer (TW1) is positioned on the bake plate, and post-processing inspection data is obtained for the first coated teaching wafer (TW1) after the first coated teaching wafer (TW1) is removed from the bake plate.
19. The method of claim 10, wherein one or more photoresist drying profiles andor photoresist drying rates are calculated using the (nth) teaching exhaust gas data and associated teaching wafer temperature profiles.
20. The method of claim 10, wherein one or more gas concentration profiles andor gas flow rates are calculated using the (nth) teaching exhaust gas data and associated teaching wafer temperature profiles.

1. A manufacturing method for semiconductor chips comprising:
performing plasma etching on a second surface of a semiconductor wafer that has a first surface on which semiconductor devices placed in a plurality of device-formation-regions defined by dividing regions and an insulating film placed in the dividing regions are formed and the second surface on which a mask for defining the dividing regions is placed, the second surface being located opposite from the first surface, whereby portions that correspond to the dividing regions are removed and the insulating film is exposed from etching bottom portions;
removing corner portions on the first surface side put in contact with the insulating film in the device-formation-regions by performing the plasma etching in a state in which exposed surfaces of the insulating film are charged with electric charge due to ions in plasma; and
subsequently, removing the exposed insulating film so that the device-formation-regions are separated into individual semiconductor chips, whereby the semiconductor chips each of which includes the individualized semiconductor device are manufactured,
wherein isotropic plasma etching is further performed from the second surface on the semiconductor wafer or the individual semiconductor chips with the mask placed at any timing before or after exposure of the insulating film, removal of the corner portions or removal of the insulating film is carried out.
2. The manufacturing method for the semiconductor chips as defined in claim 1, wherein corner portions put in contact with the mask placed on the second surface side are removed in the device-formation-regions of the semiconductor wafer or the semiconductor chips by carrying out the isotropic plasma etching.
3. The manufacturing method for the semiconductor chips as defined in claim 1, wherein
the exposure of the insulating film is performed by carrying out anisotropic plasma etching on the semiconductor wafer,
the corner portions are removed by continuously performing the anisotropic etching,
the corner portions brought in contact with the mask are removed by carrying out the isotopic etching by switching over from the anisotropic etching to the isotopic etching, and
then the insulator is removed.
4. The manufacturing method for the semiconductor chips as defined in claim 3, wherein
the switchover between the anisotropic etching and the isotopic etching is performed by switching over between plasma conditions for the anisotropic etching and plasma conditions for the isotopic etching determined by combining one parameter or a plurality of parameters including a pressure of a gas for plasma generation, a gas composition, a high-frequency output or a discharge frequency.
5. The manufacturing method for the semiconductor chips as defined in claim 1, wherein, in the plasma etching from the second surface, the insulating film formed of silicon oxide (SiO2) on the first surface of the semiconductor wafer is exposed from the etching bottom portion.
6. The manufacturing method for the semiconductor chips as defined in claim 1, wherein, in the plasma etching from the second surface, a surface protection film formed of polyimide (PI) to protect surfaces of the semiconductor devices formed on the first surface of the semiconductor wafer is exposed from the etching bottom portion as the insulating film.
7. The manufacturing method for the semiconductor chips as defined in claim 1, wherein, after the removal of the insulating film, the mask is removed by performing ashing on the second surface of the semiconductor wafer.
8. The manufacturing method for the semiconductor chips as defined in claim 1, wherein, the plasma etching is performed from the second surface of the semiconductor wafer, on which the mask is placed, the mask having roughly convex curved portions formed in portions that correspond to the corner portions of each of the device-formation-regions, each of the device-formation-regions having a roughly rectangular region.
9. A manufacturing method for semiconductor chips comprising:
performing plasma etching on a second surface of a semiconductor wafer that has a first surface on which semiconductor devices placed in a plurality of device-formation-regions defined by dividing regions and an insulating film placed in the dividing regions are formed and the second surface on which a mask for defining the dividing regions is placed, the second surface being located opposite from the first surface, whereby portions that correspond to the dividing regions are removed and the insulating film is exposed from etching bottom portions; and
removing the exposed insulating film while removing corner portions on the first surface side put in contact with the insulating film in the device-formation-regions by performing the plasma etching in a state in which exposed surfaces of the insulating film are charged with electric charge due to ions in plasma, whereby the device-formation-regions are separated into individual semiconductor chips and consequently the semiconductor chips each of which includes individualized semiconductor device are manufactured,
wherein isotropic plasma etching is further performed from the second surface on the semiconductor wafer or the individual semiconductor chips with the mask placed at any timing before or after exposure of the insulating film, removal of the corner portions or removal of the insulating film is carried out.
10. The manufacturing method for the semiconductor chips as defined in claim 9, wherein corner portions put in contact with the mask placed on the second surface side is removed in the device-formation-regions of the semiconductor wafer or the semiconductor chips by carrying out the isotropic plasma etching.
11. The manufacturing method for the semiconductor chips as defined in claim 9, wherein
the exposure of the insulating film is performed by carrying out anisotropic plasma etching on the semiconductor wafer,
the corner portions are removed by continuously performing the anisotropic etching, and
then the corner portions brought in contact with the mask are removed by carrying out the isotopic etching by switching over from the anisotropic etching to the isotopic etching.
12. The manufacturing method for the semiconductor chips as defined in claim 11, wherein
the switchover between the anisotropic etching and the isotopic etching is performed by switching over between plasma conditions for the anisotropic etching and plasma conditions for the isotopic etching determined by combining one parameter or a plurality of parameters including a pressure of a gas for plasma generation, a gas composition, a high-frequency output or a discharge frequency.
13. The manufacturing method for the semiconductor chips as defined in claim 9, wherein, in the plasma etching from the second surface, a surface protection film formed of silicon nitride (Si3N4) to protect surfaces of the semiconductor devices formed on the first surface of the semiconductor wafer is exposed from the etching bottom portion as the insulating film.
14. The manufacturing method for the semiconductor chips as defined in claim 9, wherein, after removing the corner portions put in contact with the mask by performing the isotopic etching, the mask is removed by performing ashing on the second surface of the semiconductor wafer.
15. The manufacturing method for the semiconductor chips as defined in claim 9, wherein, the plasma etching is performed from the second surface of the semiconductor wafer on which the mask is placed, the mask having roughly convex curved portions formed in portions that correspond to the corner portions of each of the device-formation-regions, each of the device-formation-regions having a roughly rectangular region.
16. A manufacturing method for semiconductor chips comprising:
performing plasma etching on a second surface of a semiconductor wafer that has a first surface on which semiconductor devices placed in a plurality of device-formation-regions defined by dividing regions are formed and onto which a protective sheet having an insulating property is stuck and a second surface on which a mask for defining the dividing regions is placed, the second surface being located opposite from the first surface, whereby portions that correspond to the dividing regions are removed and the insulating protective sheet is exposed from etching bottom portions, and then the device-formation-regions are separated into individual semiconductor chips; and
removing corner portions put in contact with the insulating protective sheet at each of the semiconductor chips by performing the plasma etching in a state in which the exposed surfaces of the insulating film are charged with electric charge due to ions in plasma, whereby semiconductor chips including individualized semiconductor devices are consequently manufactured,
wherein isotropic plasma etching is further performed from the second surface on the semiconductor wafer or the individual semiconductor chips with the mask placed at any timing before or after exposure of the protective sheet or removal of the corner portions is carried out.
17. The manufacturing method for the semiconductor chips as defined in claim 16, wherein the corner portions put in contact with the mask placed on the second surface side are removed in the device-formation-regions of the semiconductor wafer or the semiconductor chips by carrying out the isotropic plasma etching.
18. The manufacturing method for the semiconductor chips as defined in claim 16, wherein
the exposure of the protective sheet is performed by carrying out anisotropic plasma etching on the semiconductor wafer,
the corner portion removal processing is carried out by continuously performing the anisotropic etching, and
then the corner portions brought in contact with the mask are removed by carrying out the isotopic etching by switching over from the anisotropic etching to the isotopic etching.
19. The manufacturing method for the semiconductor chips as defined in claim 18, wherein
the switchover between the anisotropic etching and the isotopic etching is performed by switching over between plasma conditions for the anisotropic etching and plasma conditions for the isotopic etching determined by combining one parameter or a plurality of parameters including a pressure of a gas for plasma generation, a gas composition, a high-frequency output or a discharge frequency.
20. The manufacturing method for the semiconductor chips as defined in claim 16, wherein, after the corner portions brought in contact with the mask are removed by performing the isotopic etching, the insulating protective sheet is removed by being peeled off from the first surface of the semiconductor wafer.
21. The manufacturing method for the semiconductor chips as defined in claim 16, wherein, the plasma etching is performed from the second surface of the semiconductor wafer on which the mask is placed, the mask having roughly convex curved portions formed in portions that correspond to the corner portions of each of the device-formation-regions, each of the device-formation-regions having a roughly rectangular region.
22. A semiconductor chip having a roughly rectangular shape obtained by dividing a semiconductor wafer in which a plurality of semiconductor devices are formed into individual pieces of the semiconductor devices, wherein
the rectangular shape of the chip is defined by rounded ridgelines thereof.
23. The semiconductor chip as defined in claim 22, wherein a curved convex surface portion is formed in portions that correspond to the rounded ridgelines of the rectangular shape.
24. A semiconductor chip comprising:
a first surface on which semiconductor devices are formed;
a second surface located parallel to the first surface on a side opposite from the first surface; and
a connection surface, which is located at peripheries of the first surface and the second surface and connects an outer end portion of the first surface and an outer end portion of the second surface, wherein
the connection surface has a curved convex surface portion so that no ridgeline is formed at the outer end portions of the first and the second surfaces.
25. The semiconductor chip as defined in claim 24, wherein the connection surface is comprised of the curved convex surface portion.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. The nylon cord that attaches to the putter will show the user whether or not heshe is drawing the putter back in a straight line.
2. The nylon cord that attaches to the putter will show the user whether or not heshe is following through to the target in a straight line.
3. The minimal tension on the nylon cord will teach the golfer to stroke the ball with enough force to make the ball travel to the hole, thus never being short again, never up, never in