Author: claimsbot

1. A fluid injection system including: a pressurized fluid source operatively coupled to an injector, the injector including:
a handle portion,
a frame portion,
a spike portion,
a pressure plate attached to the spike portion,
a fluid inlet proximate the handle portion,
a fluid outlet proximate a distal tip of the spike portion,
a fluid pathway extending between the fluid inlet and the fluid outlet, the fluid pathway including a valve operable to control the flow of fluid through the fluid pathway,
wherein during insertion or removal of the spike portion at a desired location fluid from the pressurized fluid source is delivered to the location.
2. The fluid injection system of claim 1, wherein the pressurized fluid source is a pressurized gas source.
3. The fluid injection system of claim 1, wherein the pressurized fluid source is a pressurized liquid source.
4. The air injection system of claim 2, further including proximate the handle portion a switch operable to open and close the valve.
5. The air injection system of claim 2, further including a plurality of depth markers disposed along a length of the spike portion.
6. The air injection system of claim 2, wherein the fluid outlet includes a plurality of fluid ports spaced along a length of the spike portion.
7. The air injection system of claim 2, wherein the fluid outlet includes a plurality of fluid ports spaced about a circumference of the spike portion.
8. The air injection system of claim 7, wherein four fluid ports are spaced at approximately ninety degree intervals.
9. The air injection system of claim 2, wherein the desired location is a turf area.
10. A fluid injector including:
a handle portion,
a frame portion,
a spike portion,
a pressure plate attached to the spike portion,
a fluid inlet proximate the handle portion,
a fluid outlet proximate a distal tip of the spike portion,
a fluid pathway extending between the fluid inlet and the fluid outlet, the fluid pathway including a valve operable to control the flow of fluid through the fluid pathway,
wherein during insertion or removal of the spike portion at a desired location fluid at the fluid inlet is deliverable to the location.
11. The fluid injector of claim 10, wherein the fluid injector further includes:
proximate the handle portion, a switch operable to open and close the valve;
a plurality of depth markers disposed along a length of the spike portion; and
a plurality of fluid ports spaced about a circumference of the spike portion.
12. The fluid injector of claim 11, wherein two fluid ports are spaced about ninety degrees apart.
13. The fluid injector of claim 11, wherein two fluid ports are spaced about one hundred eighty degrees apart.
14. A turf treatment method including the steps of:
(a) providing a fluid injection system including a fluid injector operably coupled to a source of pressurized fluid; the fluid injector including a handle portion, a frame portion, a spike portion, a pressure plate attached to the spike portion, a fluid inlet, a fluid outlet proximate a distal tip of the spike portion, a fluid pathway extending between the fluid inlet and the fluid outlet, the fluid pathway including a valve operable to control the flow of fluid through the fluid pathway;
(b) providing fluid from the pressurized fluid source to the turf to be treated via the fluid injector at a desired time.
15. The method of claim 14, wherein the desired time is during insertion of the spike portion into the turf.
16. The method of claim 14, wherein the desired time is after insertion of the spike portion into the turf.
17. The method of claim 14, wherein the desired time is during withdrawal of the spike portion from the turf.
18. The method of claim 14, wherein the fluid is air.
19. The method of claim 14, wherein the fluid includes water.
20. The method of claim 18, further including the step of forming macropore spaces in the turf.
21. The system of claim 1, wherein the pressure plate is positionable along the length of the spike portion.
22. The fluid injector of claim 10, wherein the pressure plate is positionable along the length of the spike portion.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising a semiconductor chip, the semiconductor chip comprising:
a bonding wire; and
a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising:
precious-metal-containing bonding areas on the upper side of the semiconductor chip, and
a plurality of metal layers arranged one on top of the other and comprising:
a copper-containing lower metal layer forming interconnects and contact terminal areas,
a central metal layer comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and
an upper metal layer comprising a precious metal, covering at least the bonding areas and, the bonding wire being attached to the upper metal layer, the upper metal layer having a total thickness do such that 0.1 \u03bcm\u2266do\u22661.0 \u03bcm,
wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height tm of the central metal layer is 0.05 \u03bcm\u2266tm\u22661.00 \u03bcm.
2. The semiconductor device according to claim 1, wherein a roughness of the interface of the central metal layer is formed galvanically in a front-end process by variation of current densities during deposition.
3. The semiconductor device according to claim 1, wherein a roughness of the interface of the central metal layer is such that there is great adhesiveness with respect to the plastic package molding compound, and the roughness of the interface of the central metal layer is further such that a bondability of the bonding areas is not impaired.
4. The semiconductor device according to claim 1, wherein a thickness du of the lower copper-containing metal layer of the coating structure is 2 \u03bcm\u2266du\u226650 \u03bcm.
5. The semiconductor device according to claim 1, wherein a diffusion-inhibiting metal layer comprising at least one of tungsten and titanium is arranged between the copper-containing metal layer of the contact terminal areas and the contact areas of the semiconductor chip, which are in connection with the electrodes of semiconductor elements of the semiconductor chip.
6. The semiconductor device according to claim 1, wherein a metal layer comprising at least one of tungsten and titanium is arranged as a diffusion barrier between the copper-containing metal layer of the interconnects and the passivation layers of the upper side of the semiconductor chip.
7. The semiconductor device according to claim 1, wherein cross sections of the interconnects of the metal coating structure have such dimensions that the interconnects are capable of carrying source or emitter currents of power semiconductor chips.
8. The semiconductor device according to claim 1, wherein the metal coating structure covers a proportion of a surface area \u0394F of the active upper side of the semiconductor chip, with \u0394F 50%.
9. The semiconductor device according to claim 1, wherein the semiconductor device is a power device.
10. A power semiconductor module comprising a semiconductor chip, the semiconductor chip comprising:
a bonding wire; and
a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising:
precious-metal-containing bonding areas on the upper side of the semiconductor chip, and
a plurality of metal layers arranged one on top of the other and comprising:
a copper-containing lower metal layer forming interconnects and contact terminal areas,
a central metal layer comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and
an upper metal layer comprising a precious metal, covering at least the bonding areas, the bonding wire being attached to the upper metal layer, the upper metal layer having a total thickness do such that 0.1 \u03bcm\u2266do\u22661.0 \u03bcm,
wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height tm of the central metal layer is 0.05 \u03bcm\u2266tm\u22661.00 \u03bcm.
11. A semiconductor chip comprising a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising:
precious-metal-containing bonding areas on the active upper side;
a plurality of metal layers arranged one on top of the other and comprising:
a copper-containing lower metal layer forming interconnects and contact terminal areas,
a central metal layer, comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and
an upper metal layer comprising palladium, covering at least the bonding areas, the upper metal layer having a total thickness do such that 0.1 \u03bcm\u2266do\u22661.0 \u03bcm,
wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height tm of the central metal layer is 0.05 \u03bcm\u2266tm\u22661.00 \u03bcm; and

a bonding wire attached to the upper metal layer.
12. The semiconductor chip according to claim 11, wherein a roughness of the interface of the central metal layer is formed galvanically in a front-end process by variation of current densities during deposition.
13. The semiconductor chip according to claim 11, wherein a roughness of the interface of the central metal layer is such that there is great adhesiveness with respect to the plastic package molding compound, and the roughness of the interface of the central metal layer is further such that a bondability of the bonding areas is not impaired.
14. The semiconductor chip according to claim 11, wherein a thickness du of the lower copper-containing metal layer of the coating structure is 2 \u03bcm\u2266du\u226650 \u03bcm.
15. The semiconductor device of according to claim 1, wherein the upper metal layer covers only the bonding areas, and wherein the central metal layer further has a rough interface with respect to a plastic package molding compound surrounding the metal coating structure.
16. The semiconductor chip according to claim 11, wherein the upper metal layer covers only the bonding areas, and wherein the central metal layer further has a rough interface with respect to a plastic package molding compound surrounding the metal coating structure.
17. The semiconductor device of claim 1, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.
18. The power semiconductor module of claim 10, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.
19. The semiconductor chip of claim 11, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.
20. A semiconductor device comprising a semiconductor chip, the semiconductor chip comprising a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising:
precious-metal-containing bonding areas on the active upper side;
a plurality of metal layers arranged one on top of the other and comprising:
a copper-containing lower metal layer forming interconnects and contact terminal areas,
a central metal layer, comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and
an upper metal layer comprising palladium, covering at least the bonding areas, the upper metal layer having a total thickness do such that 0.1 \u03bcm\u2266do\u22661.0 \u03bcm,
wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height tm of the central metal layer is 0.05 \u03bcm\u2266tm\u22661.00 \u03bcm; and

a bonding wire attached to the upper metal layer.
21. The semiconductor device of claim 20, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.
22. A power semiconductor module comprising a semiconductor chip, the semiconductor chip comprising a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising:
precious-metal-containing bonding areas on the active upper side;
a plurality of metal layers arranged one on top of the other and comprising:
a copper-containing lower metal layer forming interconnects and contact terminal areas,
a central metal layer, comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and
an upper metal layer comprising palladium, covering at least the bonding areas, the upper metal layer having a total thickness do such that 0.1 \u03bcm\u2266do\u22661.0 \u03bcm,
wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height tm of the central metal layer is 0.05 \u03bcm\u2266tm\u22661.00 \u03bcm; and

a bonding wire attached to the upper metal layer.
23. The power semiconductor module of claim 22, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.

1-14. (canceled)
15. A secure communications terminal, comprising:
a satellite phone comprising a data port;
an encryption device; and
a modem to satellite phone interconnect board to capture a Dial Tone Modulation Frequency (DTMF) tone, demodulate V.34 encrypted modem information received from said encryption device, and convert said DTMF tone and said demodulate V.34 encrypted modem information into an ASCII string, said ASCII string being presented out-of-band with respect to said DTMF tone to said satellite phone data port.
16. The secure communications terminal according to claim 15, wherein:
said modem to satellite phone interconnect board is comprised of a modem.
17. The secure communications terminal according to claim 15, wherein:
said modem to satellite phone interconnect board is formed in a programmable integrated circuit (PIC).
18. The secure communications terminal according to claim 15, wherein:
said modem to satellite phone interconnect board alternately received an output from a FAXdata interface.
19. The secure communications terminal according to claim 15, wherein:
said satellite phone is controlled from a secure side of said encryption device.
20. The secure communications terminal according to claim 15, wherein:
said ASCII string is presented out-of-band with respect to a control signal presented to said satellite phone data port.
21. A method of providing secure communications over a non-secure data network, comprising:
capturing a Dial Tone Modulation Frequency (DTMF) tone;
demodulating V.34 encrypted modem information received from an encryption device;
converting said DTMF tone and said demodulate V.34 encrypted modem information into an ASCII string; and
presenting said ASCII string out-of-band with respect to said DTMF tone to a data port of a satellite phone.
22. The method of providing secure communications over a non-secure data network according to claim 21, further comprising:
alternatively receiving demodulated V.34 information at a FAXdata interface.
23. The method of providing secure communications over a non-secure data network according to claim 21, further comprising:
controlling said satellite phone from a secure side of said encryption device.
24. The method of providing secure communications over a non-secure data network according to claim 21, further comprising:
controlling a function of a satellite phone directly from a secure side of said encryption device.
25. The method of providing secure communications over a non-secure data network according to claim 21, further comprising:
presenting said ASCII string out-of-band with respect to a control signal presented to said data port of said satellite phone.
26. Apparatus for providing secure communications over a non-secure data network, comprising:
means for providing a false dial tone to an encryption device;
means for capturing a Dial Tone Modulation Frequency (DTMF) tone;
means for demodulating V.34 encrypted modem information from a modem;
means for converting said DTMF tone and said demodulate V.34 encrypted modem information into an ASCII string; and
means for presenting said ASCII string to a data port of a satellite phone.
27. The apparatus for providing secure communications over a non-secure data network according to claim 26, further comprising:
means for alternatively receiving an output from a FAXdata interface.
28. The apparatus for providing secure communications over a non-secure data network according to claim 26, further comprising:
means for controlling said satellite phone from a secure side of said encryption device.
29. The apparatus for providing secure communications over a non-secure data network according to claim 26, further comprising:
means for controlling a function of a satellite phone directly from a secure side of said encryption device.
30. The apparatus for providing secure communications over a non-secure data network according to claim 26, further comprising:
means for presenting said ASCII string presents said ASCII string out-of-band with respect to a control signal presented to said data port of said satellite phone.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated circuit, comprising:
a substrate having a surface;
a first conductive path disposed on the substrate at a first level and having a first thickness in a direction normal to the substrate surface; and
a second conductive path disposed on the substrate at the first level and having a second thickness in the direction, the second thickness being significantly different than the first thickness.
2. The integrated circuit of claim 1 wherein:
the first conductive path comprises a digit line; and
the second conductive path comprises a supply line.
3. The integrated circuit of claim 1 wherein:
the first conductive path comprises a digit line;
the second conductive path comprises a supply line; and
the thickness of the supply line is significantly greater than the thickness of the digit line.
4. A memory circuit, comprising:
a substrate;
an insulator disposed on the substrate in a first level;
a digit line disposed on the insulator in a second level, the digit line having a first height; and
a supply line disposed on the insulator in the second level, the supply line having a second height that is significantly greater than the first height.
5. The memory circuit of claim 4 wherein:
the second level comprises first and second sublevels;
the digit line comprises,
a first portion of a first conductive material disposed on the insulator in the first sublevel; and

the supply line comprises,
a second portion of the first conductive material disposed on the insulator in the first sublevel, and
a portion of a second conductive material disposed on the second portion of the first conductive material in the second sublevel.
6. The memory circuit of claim 4 wherein:
the second level comprises first and second sublevels;
the digit line comprises,
a first portion of a conductive etch-stop material disposed on the insulator in the first sublevel; and

the supply line comprises,
a second portion of the conductive etch-stop material disposed on the insulator in the first sublevel, and
a portion of a conductive material disposed on the second portion of the conductive etch-stop material in the second sublevel.
7. The memory circuit of claim 4 wherein:
the second level comprises first, second, and third sublevels;
the digit line comprises,
a first portion of a first conductive material disposed on the insulator in the first sublevel, and
a first portion of a second conductive material disposed on the first portion of the first conductive material in the second sublevel; and

the supply line comprises,
a second portion of the first conductive material disposed on the insulator in the first sublevel,
a second portion of the second conductive material disposed on the second portion of the first conductive material in the second sublevel, and
a portion of a third conductive material disposed on the second portion of the second conductive material in the third sublevel.
8. The memory circuit of claim 4 wherein:
the second level comprises first, second, and third sublevels;
the digit line comprises,
a first portion of a first conductive material disposed on the insulator in the first sublevel, and
a first portion of a conductive etch-stop material disposed on the first portion of the first conductive material in the second sublevel; and

the supply line comprises,
a second portion of the first conductive material disposed on the insulator in the first sublevel,
a second portion of the conductive etch-stop material disposed on the second portion of the first conductive material in the second sublevel, and
a portion of a third conductive material disposed on the second portion of the conductive etch-stop material in the third sublevel.
9. An integrated circuit, comprising:
a substrate;
a conductive layer structure disposed on the substrate;
a first conductive path formed from the conductive layer and having a first height; and
a second conductive path formed from the conductive layer and having a second height that is significantly different than the first height.
10. The integrated circuit of claim 9 wherein the conductive layer structure comprises a single conductive layer.
11. The integrated circuit of claim 10 wherein:
the conductive layer structure comprises,
a first conductive layer disposed on the substrate, and
a second conductive layer disposed on the first conductive layer;

the first conductive path comprises,
a first portion formed from the first conductive layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the second conductive layer.
12. The integrated circuit of claim 10 wherein:
the conductive layer structure comprises,
a barrier layer disposed on the substrate,
a conductive layer disposed on the barrier layer;

the first conductive path comprises,
a first portion formed from the barrier layer, and
a second portion formed from the conductive layer; and

the second conductive path comprises,
a first portion formed from the barrier layer,
a second portion formed from the conductive layer, the second portion of the second conductive path having a significantly greater height that the second portion of the first conductive path.
13. The integrated circuit of claim 10 wherein:
the conductive layer structure comprises,
a conductive layer disposed on the substrate, and
a cap layer disposed on the conductive layer;

the first conductive path comprises,
a first portion formed from the conductive layer, and
a second portion formed from the cap layer; and

the second conductive path comprises,
a first portion formed from the conductive layer, the first portion of the second conductive path having a significantly greater height than the first portion of the first conductive path; and
a second portion formed from the cap layer.
14. The integrated circuit of claim 10 wherein:
the conductive layer structure comprises,
a first conductive layer disposed on the substrate, and
a conductive etch-stop layer disposed on the first conductive layer;

the first conductive path comprises,
a first portion formed from the first conductive layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the conductive etch-stop layer.
15. The integrated circuit of claim 10 wherein:
the conductive layer structure comprises,
a first conductive layer disposed on the substrate,
a second conductive layer disposed on the first conductive layer, and
a third conductive layer disposed on the second conductive layer;

the first conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the second conductive layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer,
a second portion formed from the second conductive layer, and
a third portion formed from the third conductive layer.
16. The integrated circuit of claim 10 wherein:
the conductive structure layer comprises,
a first conductive layer disposed on the substrate,
a conductive etch-stop layer disposed on the first conductive layer, and
a third conductive layer disposed on the conductive etch-stop layer;

the first conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the conductive etch-stop layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer,
a second portion formed from the conductive etch-stop layer, and
a third portion formed from the third conductive layer.
17. An integrated circuit, comprising:
a substrate;
a conductive layer structure disposed over the substrate;
a memory array including a first conductive path formed from the conductive layer structure and having a first height; and
a second conductive path formed from the conductive layer structure and having a second height that is significantly different than the first height.
18. The integrated circuit of claim 17 wherein:
the conductive layer structure comprises,
a first conductive layer disposed on the substrate, and
a second conductive layer disposed on the first conductive layer;

the first conductive path comprises,
a first portion formed from the first conductive layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the second conductive layer.
19. The integrated circuit of claim 17 wherein:
the conductive layer structure comprises,
a first conductive layer disposed on the substrate, and
a conductive etch-stop layer disposed on the first conductive layer;

the first conductive path comprises,
a first portion formed from the first conductive layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the conductive etch-stop layer.
20. The integrated circuit of claim 17 wherein:
the conductive layer structure comprises,
a first conductive layer disposed on the substrate,
a second conductive layer disposed on the first conductive layer, and
a third conductive layer disposed on the second conductive layer;

the first conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the second conductive layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer,
a second portion formed from the second conductive layer, and
a third portion formed from the third conductive layer.
21. The integrated circuit of claim 17 wherein:
the conductive layer structure comprises,
a first conductive layer disposed on the substrate,
a conductive etch-stop layer disposed on the first conductive layer, and
a third conductive layer disposed on the conductive etch-stop layer;

the first conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the conductive etch-stop layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer,
a second portion formed from the conductive etch-stop layer, and
a third portion formed from the third conductive layer.
22. The integrated circuit of claim 17 wherein:
the conductive layer is covered with a barrier layer
23. An integrated circuit, comprising:
a substrate;
a conductive layer structure disposed over the substrate;
a memory array including,
a first conductive path formed from the conductive layer structure and having a first height, and
a second conductive path formed from the conductive layer structure and having a second height that is significantly different than the first height.
24. The integrated circuit of claim 23 wherein:
the conductive layer structure comprises,
a first conductive layer disposed on the substrate, and
a second conductive layer disposed on the first conductive layer;

the first conductive path comprises,
a first portion formed from the first conductive layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the second conductive layer.
25. The integrated circuit of claim 23 wherein:
the conductive layer structure comprises,
a first conductive layer disposed on the substrate, and
a conductive etch-stop layer disposed on the first conductive layer;

the first conductive path comprises,
a first portion formed from the first conductive layer; and

the second conductive path comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the conductive etch-stop layer.
26. A memory circuit, comprising:
a substrate;
a plurality of conductive layer structures disposed on the substrate;
address, data, and command busses each disposed in one of the conductive layer structures;
a memory array coupled to the address, data, and command busses, the memory array including,
memory cells arranged in rows and columns, and
digit lines disposed in one of the conductive layers, each of the digit lines having substantially a first height and being coupled to the memory cells in a respective column; and

a signal line disposed in the one of the conductive layer structures and outside of the memory array, the signal lines having substantially a second height that is significantly greater than the first height.
27. The memory circuit of claim 26 wherein:
the one conductive layer structure comprises,
a first conductive layer, and
a second conductive layer disposed on the first conductive layer;

the digit lines each comprise,
a first portion formed from the first conductive layer; and

the signal line comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the second conductive layer.
28. The memory circuit of claim 26 wherein:
the one conductive layer structure comprises,
a first conductive layer, and
a conductive etch-stop layer disposed on the first conductive layer;

each digit line comprises,
a first portion formed from the first conductive layer; and

the signal line comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the conductive etch-stop layer.
29. The memory circuit of claim 26 wherein:
the one conductive layer structure comprises,
a first conductive layer disposed on the substrate,
a second conductive layer disposed on the first conductive layer, and
a third conductive layer disposed on the second conductive layer;

each digit line comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the second conductive layer; and

the signal line comprises,
a first portion formed from the first conductive layer,
a second portion formed from the second conductive layer, and
a third portion formed from the third conductive layer.
30. The memory circuit of claim 26 wherein:
the one conductive layer structure comprises,
a first conductive layer disposed on the substrate,
a conductive etch-stop layer disposed on the first conductive layer, and
a third conductive layer disposed on the conductive etch-stop layer;

each digit line comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the conductive etch-stop layer; and

the signal line comprises,
a first portion formed from the first conductive layer,
a second portion formed from the conductive etch-stop layer, and
a third portion formed from the third conductive layer.
31. The memory circuit of claim 26 wherein the memory cells each comprise a dynamic-random-access memory cell.
32. The memory circuit of claim 26 wherein the memory cells each comprise a static-random-access memory cell.
33. The memory circuit of claim 26 wherein the signal line comprises a supply rail.
34. The memory circuit of claim 26 wherein the signal line comprises a ground rail.
35. A memory circuit, comprising:
a substrate;
a plurality of conductive layer structures disposed on the substrate;
address, data, and command busses each disposed in one of the conductive layers;
a memory array coupled to the address, data, and command busses, the memory array including,
memory cells arranged in rows and columns, and
digit lines disposed in one of the conductive layer structures, each of the digit lines having substantially a first height and being coupled to the memory cells in a respective column, and
a signal line disposed in the one of the conductive layer structures and having substantially a second height that is significantly greater than the first height.
36. The memory circuit of claim 35 wherein:
the one conductive layer structure comprises,
a first conductive layer, and
a second conductive layer disposed on the first conductive layer;

the digit lines each comprise,
a first portion formed from the first conductive layer; and

the signal line comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the second conductive layer.
37. The memory circuit of claim 35 wherein:
the one conductive layer structure comprises,
a first conductive layer, and
a conductive etch-stop layer disposed on the first conductive layer;

each digit line comprises,
a first portion formed from the first conductive layer; and

the signal line comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the conductive etch-stop layer.
38. An electronic system, comprising:
a data input device;
a data output device; and
computing circuitry coupled to the data input and output devices, the computing circuitry including a memory circuit, the memory circuit including,
a substrate;
a plurality of conductive layer structures disposed on the substrate;
address, data, and command busses each disposed in one of the conductive layer structures;
a memory array coupled to the address, data, and command busses, the memory array including,
memory cells arranged in rows and columns, and
digit lines disposed in one of the conductive layer structures, each of the digit lines having substantially a first height and being coupled to the memory cells in a respective column; and

a signal line disposed in the one of the conductive layer structures and outside of the memory array, the signal lines having substantially a second height that is significantly greater than the first height.
39. The electronic system of claim 38 wherein:
the one conductive layer structure comprises,
a first conductive layer, and
a second conductive layer disposed on the first conductive layer;

the digit lines each comprise,
a first portion formed from the first conductive layer; and

the signal line comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the second conductive layer.
40. The electronic system circuit of claim 38 wherein:
the one conductive layer structure comprises,
a first conductive layer, and
a conductive etch-stop layer disposed on the first conductive layer;

each digit line comprises,
a first portion formed from the first conductive layer; and

the signal line comprises,
a first portion formed from the first conductive layer, and
a second portion formed from the conductive etch-stop layer.
41. A method for forming an integrated circuit, comprising:
forming on a substrate a conductive layer having a first thickness;
reducing the thickness in a first region of the conductive layer while preserving the thickness in a second region of the conductive layer;
forming a first conductive path in the first region, the first conductive path having a second thickness that is significantly less than the first thickness; and
forming a second conductive path in the second region, the second conductive path having substantially the first thickness.
42. The method of claim 41, wherein the forming a first conductive path comprises:
removing a portion of the conductive layer in the first region; and
forming the first conductive path from a remaining portion of the conductive layer.
43. The method of claim 41, further comprising forming a cap layer on the conductive layer after reducing the thickness.
44. A method for forming an integrated circuit, comprising:
forming a first conductive layer on a substrate;
forming a second conductive layer on the first conductive layer;
exposing a region of the first conductive layer through the second conductive layer;
forming a first conductive path in the exposed region of the first conductive layer; and
forming a second conductive path in a region that includes the first and second conductive layers.
45. The method of claim 44 wherein the forming a first conductive path comprises etching a region of the second conductive layer over the region of the first conductive layer with an etchant that is significantly more reactive with the second layer than with the first layer.
46. The method of claim 44, further comprising forming a cap layer on the exposed region of the first conductive layer and on the second conductive layer.
47. A method, comprising:
forming a structure on a substrate, the structure including a first conductive layer disposed on the substrate and a second conductive layer disposed on the first conductive layer;
removing the second conductive layer from a first region of the structure while preserving the second conductive layer in a second region of the structure;
forming a first conductive path in the first region of the structure from the first conductive layer; and
forming a second conductive path in the second region of the substrate from the first and second conductive layers.
48. The method of claim 47 wherein the removing comprises:
masking the second region of the structure; and
etching the first region of the structure with an etchant that etches the second layer significantly faster than the first layer.
49. A method, comprising:
forming a structure on a substrate, the structure including a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer;
removing the third conductive layer from a first region of the structure while preserving the third conductive layer in a second region of the structure;
forming a first conductive path in the first region of the structure from the first and second conductive layers; and
forming a second conductive path in the second region of the substrate from the first, second, and third conductive layers.
50. The method of claim 49 wherein the removing comprises:
masking the second region of the structure; and
etching the first region of the structure with an etchant that etches the third layer significantly faster than the second layer.
51. A method for forming a memory circuit, comprising:
forming on a substrate a conductive layer having a first thickness;
reducing the thickness in a first region of the conductive layer while preserving the thickness in a second region of the conductive layer;
forming digit lines in the first region, each of the digit lines having substantially a second thickness that is significantly less than the first thickness; and
forming a signal line in the second region, the signal line having substantially the first thickness.
52. The method of claim 51 wherein the forming digit lines comprises:
removing a portion of the conductive layer in the first region; and
forming the digit lines from a remaining portion of the conductive layer
53. A method for forming a memory circuit, comprising:
forming a structure on a substrate, the structure including a first conductive layer disposed on the substrate and a second conductive layer disposed on the first conductive layer;
removing the second conductive layer from a first region of the structure while preserving the second conductive layer in a second region of the structure;
forming digit lines in the first region of the structure from the first conductive layer; and
forming a signal line in the second region of the substrate from the first and second conductive layers.
54. The method of claim 53 wherein the removing comprises:
masking the second region of the structure; and
etching the first region of the structure with an etchant that etches the second layer significantly faster than the first layer.
55. A method for forming a memory circuit, comprising:
forming a structure on a substrate, the structure including a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer;
removing the third conductive layer from a first region of the structure while preserving the third conductive layer in a second region of the structure;
forming digit lines in the first region of the structure from the first and second conductive layers; and
forming a signal line in the second region of the substrate from the first, second, and third conductive layers.
56. The method of claim 55 wherein the removing comprises:
masking the second region of the structure; and
etching the first region of the structure with an etchant that etches the third layer significantly faster than the second layer.