1. A nonwoven fabric substrate for a clothes dryer fabric softener sheet, said nonwoven fabric substrate being formed from substantially continuous filaments having a denier within the range of 2 to 12 denier per filament, said filaments including matrix filaments formed of polyester homopolymer and binder filaments formed a polyester copolymer, and a multiplicity of bonds throughout the fabric at locations where the binder filaments contact other filaments, said bonds integrating the filaments into a coherent nonwoven fabric with a grab tensile strength of at least 6 pounds per inch in the machine direction and 3.5 pounds per inch in the cross-direction, said fabric having a basis weight of no more than 0.50 ounces per square yard and a thickness of from about 0.1 80mm to about 0.200 mm.
2. The nonwoven fabric substrate of claim 1, wherein the grab tensile strength is at least 7 pounds per inch in the machine direction and at least 4.5 pounds per inch in the cross direction.
3. The nonwoven fabric substrate of claim 2, wherein the thickness is from about 0.190 mm to about 0.195 mm.
4. The nonwoven fabric substrate of claim 1, wherein the nonwoven fabric basis weight is 0.48 ounce per square yard.
5. The nonwoven fabric substrate of claim 1, wherein the filaments have a denier per filament of 5 to 7.
6. The nonwoven fabric substrate of claim 1, wherein the filament have a trilobal cross-section.
7. The nonwoven fabric substrate of claim 1, in which the fabric is formed from 80% to 95% by weight polyethylene terephthalate homopolymer matrix filaments and 5% to 20% by weight polyethylene isophthalate copolymer binder filaments.
8. A nonwoven fabric substrate for a clothes dryer fabric softener sheet, said nonwoven fabric substrate being formed from substantially continuous filaments having a trilobal cross-section and a denier within the range of 5 to 7 denier per filament, said filaments including 80% to 95% by weight polyethylene terephthalate homopolymer matrix filaments and 5% to 20% by weight polyethylene isophthalate copolymer binder filaments, and a multiplicity of bonds throughout the fabric at locations where the binder filaments contact other filaments, said bonds integrating the filaments into a coherent nonwoven fabric with a grab tensile strength of at least 7 pounds per inch in the machine direction and 4.5 pounds per inch in the cross-direction, said fabric having a basis weight of from about 0.46 to 0.50 ounces per square yard and a thickness of from about 0.190mm to about 0.195 mm.
9. A process for producing a nonwoven fabric substrate for a clothes dryer fabric softener sheet, said process comprising extruding substantially continuous filaments, drawing the filaments to a denier within the range of 2 to 12 denier per filament, randomly depositing the filaments on a collection surface for form a filamentary web with a basis weight of no more than 0.50 ounce per square yard, consolidating the web of filaments in a steam consolidator at a surface temperature of less than 100 degrees C to maintain a fabric thickness of from about 0.180 mm to about 0.200 mm, and directing the consolidated nonwoven web through a hot air bonder and forming a multiplicity of bonds throughout the fabric at locations, the bonds imparting to the nonwoven fabric a tensile strength of at least 6 pounds per inch in the machine direction and 3.5 pounds per inch in the cross-direction.
10. A process according to claim 9, wherein the surface temperature of the steam consolidator drum is less than 95 degrees C.
11. A process according to claim 10, wherein said step of consolidating the web of filaments in a steam consolidator includes operating the consolidator at a chest steam flow of less than 12,000 pounds per hour and a drum pressure less than 12 pounds per square inch.
12. A process according to claim 9, wherein the step of extruding substantially continuous filaments comprises extruding a first plurality of polyethylene terephthalate homopolymer matrix filaments from a first set of spinneret orifices and extruding a second plurality of polyethylene isopolymer binder filaments from a second set of spinneret orifices, and wherein the step of forming a multiplicity of bonds comprises forming bonds through out the web at locations where the binder filaments contact other filaments.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A non-volatile semiconductor memory device including a memory cell transistor and peripheral transistor on the same substrate, comprising:
a metal suicide layer formed on at least one diffusion layer of the memory cell transistor, at least one diffusion layer of the peripheral transistor and on a gate electrode of the peripheral transistor; and
a self aligned contact structure providing an electrical connection to the at least one diffusion layer of the memory cell transistor.
2. The non-volatile semiconductor memory device according to claim 1, wherein:
the gate electrode of the peripheral transistor and a floating gate electrode of the memory cell transistor are formed from the same material.
3. The non-volatile semiconductor memory device according to claim 1, further including:
a gate insulating film formed under the gate of the peripheral transistor and floating gate insulating film under a floating gate electrode of the memory cell transistor wherein the gate insulating film is thicker than the floating gate insulating film.
4. The non-volatile semiconductor memory device according to claim 1, wherein:
the self aligned contact structure includes a conductive plug and the conductive plug includes a conductive plug portion at least partially overlapping a memory cell gate electrode of the memory cell transistor.
5. The non-volatile semiconductor memory device according to claim 1, further including:
an element separation region disposed between the peripheral transistor and the memory cell transistor.
6. The non-volatile semiconductor memory device according to claim 1, wherein:
the metal silicide layer includes cobalt.
7. A method of manufacturing a non-volatile semiconductor memory device having a memory cell transistor and a peripheral transistor on the same substrate, comprising the steps of:
forming a metal silicide layer on at least one diffusion layer of the memory cell transistor and at least one diffusion layer of the peripheral transistor at essentially the same time; and
forming a self aligned contact to provide an electrical connection to the at least one diffusion layer of the memory cell transistor.
8. The method of manufacturing a non-volatile semiconductor memory device according to claim 7, wherein:
forming a contact hole to provide an electrical connection to the at least one diffusion layer of the peripheral transistor, the contact hole being formed at essentially the same time as the self aligned contact.
9. The method of manufacturing a non-volatile semiconductor memory device according to claim 7, wherein:
the memory cell transistor includes a floating gate and a memory cell transistor control gate and the self aligned contact includes a conductive plug including a conductive plug portion at least partially overlapping the memory cell transistor control gate.
10. The method of manufacturing a non-volatile semiconductor memory device according to claim 9, further including:
Forming a side wall insulating film on a side of the memory cell transistor control gate.
11. A method of manufacturing a non-volatile semiconductor memory device having a memory cell transistor and a peripheral transistor on a semiconductor substrate, comprising the steps of:
forming an element separation region on the semiconductor substrate;
forming a first gate oxide film in a memory cell transistor region and a peripheral transistor region;
forming a peripheral transistor gate electrode and a memory cell transistor floating gate electrode;
forming an inter-electrode insulating film over the floating gate electrode;
forming a memory cell transistor control gate electrode over the inter-electrode insulating film;
forming a first nitride film over the memory cell transistor control gate electrode;
forming a peripheral diffusion electrode for the peripheral transistor and a memory cell diffusion electrode for the memory cell transistor;
forming a second nitride film as side walls on the side faces of the memory cell transistor control gate electrode;
forming metal silicide layers on the peripheral transistor gate electrode and peripheral transistor diffusion electrode;
sequentially forming a third nitride film and an interlayer insulating film over the memory cell transistor region and peripheral transistor region; and
removing portions of the interlayer insulating film and the third nitride film that are over the memory cell diffusion electrode to open a memory cell contact hole.
12. The method of manufacturing a non-volatile semiconductor memory device according to claim 11, wherein:
forming the peripheral transistor gate electrode and the memory cell transistor floating gate includes forming a first polycrystalline silicon film over the surface and patterning the first polycrystalline silicon film so as to separate the peripheral transistor region from the memory cell transistor region.
13. The method of manufacturing a non-volatile semiconductor memory device according to claim 12, wherein:
the steps of forming the interlayer electrode insulating film, forming the memory cell transistor control gate electrode, and forming the first nitride film include
forming the inter-electrode insulating film, a second polycrystalline silicon film, and the first nitride film in that order on the semiconductor substrate; and
etching the first nitride film, second polycrystalline film, and inter-electrode insulating film to form the memory cell transistor control gate electrode.
14. The method of manufacturing a non-volatile semiconductor memory device according to claim 13, wherein:
forming the memory cell transistor floating gate electrode includes etching the first polycrystalline silicon film in the memory cell transistor region in the step of etching the first nitride film, second polycrystalline film, and inter-electrode insulating film.
15. The method of manufacturing a non-volatile semiconductor memory device according to claim 14, wherein:
the second polycrystalline silicon film contains an impurity.
16. The method of manufacturing a non-volatile semiconductor memory device according to claim 15, wherein:
forming the peripheral diffusion electrode and the memory cell diffusion electrode includes a heat treatment.
17. The method of manufacturing a non-volatile semiconductor memory device according to claim 16, wherein:
forming the peripheral transistor gate electrode includes etching the first polycrystalline film in the peripheral transistor region separately from etching the first polycrystalline film in the memory cell transistor region.
18. The method of manufacturing a non-volatile semiconductor memory device according to claim 17, wherein:
removing portions of the interlayer insulating film and the third nitride layer includes removing portions of the interlayer insulating film and the third nitride layer over the peripheral transistor diffusion electrode to open a peripheral contact hole.
19. The method of manufacturing a non-volatile semiconductor memory device according to claim 18, further including the step of:
forming a second gate oxide film on the first gate oxide film in the peripheral transistor region while substantially leaving the first gate oxide film in the memory cell region.
20. The method of manufacturing a non-volatile semiconductor memory device according to claim 11, wherein:
the non-volatile semiconductor memory device is a flash memory.