1. A clock synthesizer for generating a desired clock signal from an input clock signal, comprising:
an exclusive OR gate, having a first input, a second input and an output, the first input coupled to receive a reset signal;
a delay string buffer having an input, a control input and an output, the delay string buffer input coupled to the output of the exclusive OR gate,
wherein;
a fine tuning unit, having an input, a control input and an output, the fine tuning unit input coupled to the output of the delay string buffer, the fine tuning unit output coupled to the second input of the exclusive OR gate; and
a control unit, having a first input, a second input and an output, the first input of the control unit coupled to receive the input clock signal and the second input of the control unit coupled to the output of the exclusive OR gate to generate a control signal at the output;
wherein the control input of the delay string buffer is coupled to receive the control signal to provide a coarse adjustment of the input clock signal corresponding to the desired clock signal, and wherein the control input of the fine tuning unit is coupled to receive the control signal to provide a fine adjustment of the input clock signal corresponding to the desired clock signal.
2. The clock synthesizer of claim 1, wherein the delay string buffer comprises:
a multiplexer, having a plurality of inputs, a control input and an output, the multiplexer control input coupled to receive the control signal, wherein the output of the multiplexer provides the output of the delay string buffer; and
a plurality of tristated buffers, each having an input, a tristate input, and output, each of the plurality of buffers coupled in series, the input of each of the plurality of buffers coupled to a respective input of the plurality of inputs of the multiplexer, the input of the least significant one of the plurality of tristated buffers coupled to receive the output of the exclusive OR gate through the input of the delay string buffer, each of the plurality of tristate inputs coupled to receive the control signal.
3. The clock synthesizer of claim 2, wherein the plurality of tristate inputs are coupled to receive the control signal to switch specific ones of the plurality of tristate inputs on and off to save power.
4. The clock synthesizer of claim 1, wherein the fine tuning unit comprises:
an input buffer coupled to the fine tuning unit input;
a plurality of AND gates, each having a first input, a second input and an output, each of the plurality of the first inputs of the AND gates coupled to the input buffer, each of the plurality of the second inputs of the AND gates coupled to receive a respective bit of the control signal;
a plurality of intermediate buffers coupled to a respective one of the plurality of outputs of the plurality of AND gates; and
an OR gate, having an output and a plurality of inputs corresponding to the number of plurality of AND gates, wherein the plurality of inputs couple to each respective one of the plurality of intermediate buffers.
5. The clock synthesizer of claim 4, wherein the plurality of intermediate buffers are tristate buffers, having an input, a tristate input and an output, each one of the plurality of the tristate inputs coupled to receive the control signal to switch specific ones of the plurality of tristate inputs on and off to save power.
6. The clock synthesizer of claim 1, wherein a bus width of the output of the control unit is equal to the sum of the number (N) of bits necessary to control the fine tuning unit and the number (M) of bits necessary to control the delay string buffer.
7. A method of synthesizing a multiplied clock signal at a desired frequency, comprising:
a. receiving an input clock signal in a clock synthesizer;
b. resetting initialization variables for a control unit within the clock synthesizer;
c. generating a coarse adjustment for a delay buffer string within the clock synthesizer;
d. setting the coarse adjustment by sending control signals from the control unit to the delay buffer string;
e. generating a fine adjustment for a fine tuning unit within the clock synthesizer;
f. setting the fine adjustment by sending control signals from the control unit to the fine tuning unit;
g. providing dither to a generated clock signal by shifting the signal modified by the fine tuning unit:
h. monitoring the frequency of the generated clock signal at predetermined intervals (R) of time per second;
i. returning to step (e) when a fine adjustment of the generated clock signal is necessary; and
j. returning to step (h) until the system that incorporates the clock synthesizer powers down.
8. The method of claim 7, wherein the method further comprises returning to step (c) when a coarse adjustment of the generated clock signal is necessary after the monitoring step (h).
9. The method of claim 7, wherein the step of generating a coarse adjustment, comprises:
a. counting the cycles of the output clock and the input clock;
b. calculating the ratio of output clock cycles to the number of input clock cycles;
c. comparing the ratio to a predetermined desired ratio corresponding to the desired frequency; and
d. calculating coarse adjustment for a delay buffer string within the clock synthesizer corresponding to the desired frequency based upon the comparison of ratios.
10. The method of claim 7, wherein the step of generating a fine adjustment, comprises:
a. counting the cycles of the output clock and the input clock;
b. calculating the ratio of output clock cycles to the number of input clock cycles;
c. comparing the ratio to a predetermined desired ratio corresponding to the desired frequency;
d. calculating a residue from the comparison of ratios; and
e. calculating fine adjustment for a fine tuning unit within the clock synthesizer corresponding to the desired frequency based upon the residue.
11. The method of claim 7, wherein predetermined number (R) is equal to 10.
12. The method of claim 7, wherein the method further comprises switching on and off a plurality of tristated buffers within the fine tuning unit to save power and generate a clock signal at the desired frequency.
13. The method of claim 7, wherein the method further comprises switching on and off a plurality of tristated buffers within the delay buffer string to save power and generate a clock signal at the desired frequency.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of acquiring MR data with reduced specific absorption rate (SAR), comprising:
applying a magnetic resonance sequence in which at least one RF pulse is repeatedly applied to generate MR scan data during an MR acquisition scan using two or more transmit coils;
altering a composition of the repeatedly applied RF pulse such that the RF pulse causes lower SAR in some repetitions than in others; and
acquiring the MR scan data in k-space.
2. The method according to claim 1, further including:
reconstructing the scan data into an image; and
at least one of displaying and storing the image.
3. The method according to claim 1, wherein the lower SAR RF pulses have lower frequency components and the other RF pulses further include higher frequency components.
4. The method according to claim 1, wherein:
the repeatedly applied RF pulses with higher frequency components are used to acquire the MR scan data in a periphery region of k-space, and the RF pulses with lower frequency components are used to acquire the MR scan data in a central region of k-space; or
the repeatedly applied RF pulses with higher frequency components are used to acquire the MR scan data in a central region of k-space, and the RF pulses with lower frequency components are used to acquire the MR scan data in a periphery region of k-space.
5. The method according to claim 1, further including:
shimming the B1 field using one or more Eigenmodes when acquiring periphery k-space data; and
shimming the B1 field using a single central Eigenmode when acquiring central k-space data.
6. The method according to claim 1, wherein the components of the repeatedly applied RF pulses include contributions from each of a plurality of transmit channels and wherein altering the composition of the repeatedly applied RF pulse includes altering a weighting among the contributions and the RF pulse k-space trajectory.
7. The method according to claim 3, wherein the low frequency RF pulses are one-dimensional RF pulses and wherein the high frequency RF pulses are at least two-dimensional RF pulses.
8. The method according to claim 1, wherein the RF pulses are magnetization preparation RF pulses employed in a multiple-channel transmit system.
9. The method according to claim 1, wherein the repeatedly applied RF pulses with lower SAR have a lower spatial resolution, and repeatedly applied pulses with higher SAR have a higher spatial resolution.
10. A multi-transmit channel MRI device including an RF pulse generator that generates the versions of the repeatedly applied RF pulses for executing the method according to claim 1.
11. A computer-readable medium carrying software for controlling a processor to perform the method according to claim 1.
12. A magnetic resonance system for reducing specific absorption rate (SAR), the system including:
two or more transmit RF coils;
an RF pulse generator;
a processor configured to:
control the RF pulse generator to apply an MR scan sequence with at least one repeatedly applied RF pulse;
select from among at least two pre-generated versions of the repeatedly applied RF pulses, each version exhibiting a different SAR, with different frequency components;
supply the RF pulse generator with higher frequency versions of the repeatedly applied RF pulse when acquiring MR data from a first region of k-space and lower frequency versions of the repeatedly applied RF pulse when acquiring MR data from a second region of k-space; and
process the MR data; and
a display configured to display the processed MR data.
13. The system according to claim 12, wherein the RF coil includes a plurality of RF transmit coils, each RF coil being connected with a corresponding RF pulse generator, and wherein the high frequency RF pulses are optionally at least two-dimensional RF pulses.
14. The system according to claim 13, wherein the processor executes computer-executable instructions for:
shimming the B1 field using one or more Eigenmodes when acquiring periphery k-space data; and
shimming the B1 field using a single central Eigenvalue when acquiring central k-space data.
15. The method according to claim 12, wherein the first region of k-space is one of a central region of k-space and a peripheral region of k-space, and wherein the second region of k-space is the other of the central region of k-space and the peripheral region of k-space.