What is claimed:
1. A data processing system for performing authentications and business transactions comprising:
a predetermined authentication policy which is shared between at least one server and a PSD; wherein the predetermined authentication policy is functionally stored within the PSD and server;
at least one server configured to perform authentications according to the predetermined authentication policy and further configured to support at least one network connection; wherein the server is functionally connected to at least one client over at least one network connection;
at least one local client configured to support a plurality of local device connections and at least one network connection; wherein the client is functionally connected to at least one server over at least one network connection;
an intelligent portable device configured to support a PSD, a plurality of local device connections and a plurality of network connections; and
the PSD which is functionally connected to the intelligent portable device and configured to generate authentication information according to the predetermined authentication policy.
2. The system according to claim 1, wherein an end user sends an authentication request from the client to the server over the network.
3. The system according to claim 2, wherein the server, responsive to the authentication request sent by an end user from the client, authenticates the end user using the predetermined authentication policy.
4. The system according to claim 1, wherein the intelligent device is functionally connected to the client through at least one local device connection and further configured as a hardware device peripheral which allows the PSD to communicate authentication information with the server using the network connection.
5. The system according to claim 4, wherein the local device connection between the client and intelligent portable device is selected from the group consisting of a direct connection, an optical connection, wireless RF connection or electro acoustical connection.
6. The system according to claim 3, wherein the predetermined authentication policy includes asynchronous authentication means, synchronous authentication means and cryptography means.
7. The system according to claim 5, wherein at least a second client functionally connected to a second server may connect with the intelligent portable device as a hardware device peripheral allowing use of the predetermined authentication policy shared with the PSD and the server.
8. The system according to claim 1, wherein the intelligent device is functionally connected to at least one network in common with the server and configured as an independent portable device which allows the PSD to communicate authentication information with the server over at least one network connection.
9. The system according to claim 2, wherein the authentication request includes at least one unique identifier associated with the end user.
10. The system according to claim 9, wherein the unique identifier is used by the server for locating and communicating with the intelligent portable device associated with the end user.
11. The system according to claim 9, wherein the unique identifier is used by the server for locating and communicating with another intelligent portable device associated with a second level approver.
12. The system according to claim 8, wherein the network connection between the server and intelligent portable device is selected from the group consisting of a wireless RF network or digital cellular network.
13. The system according to claim 8, wherein a first portion of authentication information is sent over a first network connecting the intelligent portable device with the server and a second portion of the authentication information is sent over a second network connecting the client with the server.
14. The system according to claim 12, wherein the intelligent portable device connects to at least a second server over at least one networking allowing use of the predetermined authentication policy shared with the PSD and the second server.
15. The system according to claim 7 or 14, wherein a plurality of network and local device connections are facilitated using the intelligent portable device.
16. The system according to claim 15, wherein plurality of authentications are facilitated using the shared predetermined authentication policy.
17. The system according to claim 16, wherein a plurality of local device connections, a plurality of network connections and a plurality of authentications are facilitated using the intelligent portable device
18. A method for performing authentications and business transactions comprising:
networking an intelligent portable device including a functionally connected PSD to at least one server using a network connection; wherein a shared predetermined authentication policy is functionally stored in the server and PSD,
initiating an authentication request by an end user at the client,
sending the request to a server, wherein the client and the server are functionally connected by a network,
authenticating the end user using the predetermined authentication policy,
allowing the end user access to the network following successful authentication for purposes of performing additional transactions.
19. The method according to claim 18, wherein the intelligent portable device is configured as a hardware device peripheral.
20. The method according to claim 18, wherein the intelligent portable device is configured as an independent intelligent portable device.
21. The method according to claim 18, wherein the predetermined authentication policy includes asynchronous authentication means and cryptography means.
22. The method according to claim 18, wherein the predetermined authentication policy includes synchronous authentication means and cryptography means.
23. The method according to claim 18, further comprising end user authentication to the PSD by entry of a PIN.
24. The method according to claim 18, further comprising end user authentication to the PSD using a biometric result.
25. The method according to claim 23 or 24, wherein the entry is conducted using a user interface and display associated with the intelligent portable device.
26. The method according to claim 23 or 24, wherein the entry is conducted using a user interface and display associated with the client.
27. The method according to claim 23 or 24, wherein exceeding a maximum number of attempts at authentication ends the authentication process.
28. The method according to claim 21, wherein exceeding a predetermined response time ends the authentication process.
29. The method according to claim 18 further comprising business transactions.
30. An intelligent portable data processing device for performing authentications and business transactions comprising:
a user interface, a display, data processing means, data storage means, authentication means, business transaction means, a plurality of local device connection means, a plurality of network connection means, PSD interfacing means and a PSD.
31. The device according to claim 30, wherein the authentication means includes a predetermined authentication policy, which is functionally stored in the PSD and shared with at least one additional server.
32. The device according to claim 30, wherein the device is functionally connected to at least one client using at least one local device connection means.
33. The device according to claim 30, wherein the device is functionally connected to at least one server using at least one network connection means.
34. The device according to claim 30, wherein the device is functionally connected to at least one local client using at least one local device connection means and functionally connected to at least one server using at least one network connection means.
35. The device according to claim 30, wherein the device is functionally connected to a plurality of local clients using at least one local connection means.
36. The device according to claim 30, wherein the device is functionally connected to a plurality of servers using at least one network connection means.
37. The device according to claim 30, wherein the device is functionally connected to a plurality of local clients using at least one local connection means and functionally connected to multiple servers using at least one network connection means
38. The PSD according to any one of the preceding claims wherein the PSD is a physical device.
39. The PSD according to claim 38, wherein the PSD is a virtual device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A differential buffer circuit, comprising:
a current source;
a current sink;
a switching circuit connected to the current source at a first node and connected to the current sink at a second node, the switching circuit being operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal applied to the switching circuit;
a common mode detection circuit connected to the differential outputs of the buffer circuit, the common mode detection circuit being operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage; and
a common mode control circuit having a first terminal connected to the current source and a second terminal connected to the current sink, the common mode control circuit being operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.
2. The circuit of claim 1, wherein the common mode control circuit comprises:
a first transistor having a first bias terminal adapted for connection to a first voltage source providing a first voltage, a second bias terminal connected to the first node of the switching circuit, and a control terminal adapted to receive the second control signal; and
a second transistor device having a first bias terminal adapted for connection to a second voltage source providing a second voltage, a second bias terminal connected to the second node of the switching circuit, and a control terminal adapted to receive the second control signal.
3. The circuit of claim 2, wherein the first transistor comprises a PMOS device, the first bias terminal of the first transistor being a source of the PMOS device, the second bias terminal of the first transistor being a drain of the PMOS device, and the control terminal of the first transistor being a gate of the PMOS device.
4. The circuit of claim 2, wherein the second transistor comprises an NMOS device, the first bias terminal of the second transistor being a source of the NMOS device, the second bias terminal of the second transistor being a drain of the NMOS device, and the control terminal of the second transistor being a gate of the NMOS device.
5. The circuit of claim 1, wherein the common mode control circuit is operative to supply a first current to the first node of the switching circuit and to remove a second current from the second node of the switching circuit, a magnitude of the first and second currents being controlled as a function of the second control signal.
6. The circuit of claim 5, wherein the common mode control circuit is configured such that a magnitude of the first current supplied to the first node of the switching circuit is inversely proportional to a magnitude of the second control signal, and a magnitude of the second current removed from the second node of the switching circuit is proportional to the magnitude of the second control signal.
7. The circuit of claim 5, wherein the common mode control circuit is configured such that a change in magnitude of the first current is inversely proportional to a change in magnitude of the second current.
8. The circuit of claim 1, wherein the current source comprises a PMOS device including a first sourcedrain adapted for connection to a first voltage source providing a first voltage, a second sourcedrain connected to the first node, and gate adapted to receive a first bias signal for controlling a magnitude of a first current supplied by the current source.
9. The circuit of claim 1, wherein the current sink comprises an NMOS device including a first sourcedrain adapted for connection to a second voltage source providing a second voltage, a second sourcedrain connected to the second node, and gate adapted to receive a second bias signal for controlling a magnitude of a second current returned to the second voltage source.
10. The circuit of claim 1, wherein the common mode detection circuit comprises a resistor divider connected between the differential outputs of the buffer circuit, the resistor divider being operative to generate a voltage which is substantially equal to a middle point between the respective voltages at the differential outputs of the buffer circuit.
11. The circuit of claim 1, wherein the common mode detection circuit comprises a first resistive element connected between one of the differential outputs of the buffer circuit and a common mode node, and a second resistive element connected between another of the differential outputs of the buffer circuit and the common mode node, a resistance of the first resistive element being substantially equal to a resistance of the second resistive element.
12. The circuit of claim 1, wherein the switching circuit comprises:
a first transistor device of a first polarity type including a first bias terminal connected to the current source, a second bias terminal connected to a first differential output of the buffer circuit, and a control terminal adapted to receive the first control signal;
a second transistor device of a second polarity type including a first bias terminal connected to the first differential output, a second bias terminal connected to the current sink, and a control terminal adapted to receive the first control signal;
a third transistor device of the first polarity type including a first bias terminal connected to the current source, a second bias terminal connected to a second differential output of the buffer circuit, and a control terminal adapted to receive a logical complement of the first control signal; and
a fourth transistor device of the second polarity type including a first bias terminal connected to the second differential output, a second bias terminal connected to the current sink, and a control terminal adapted to receive the logical complement of the first control signal.
13. The circuit of claim 1, wherein the switching circuit comprises:
a first PMOS transistor including a first sourcedrain connected to the current source, a second sourcedrain connected to a first differential output of the buffer circuit, and a gate adapted to receive the first control signal;
a first NMOS transistor including a first sourcedrain connected to the first differential output, a second sourcedrain connected to the current sink, and a gate adapted to receive the first control signal;
a second PMOS transistor including a first sourcedrain connected to the current source, a second sourcedrain connected to a second differential output of the buffer circuit, and a gate adapted to receive a logical complement of the first control signal; and
a second NMOS transistor including a first sourcedrain connected to the second differential output, a second sourcedrain connected to the current sink, and a gate adapted to receive the logical complement of the first control signal.
14. The circuit of claim 1, further comprising an \u201cH\u201d bridge, the \u201cH\u201d bridge comprising the current source, the current sink and the switching circuit.
15. The circuit of claim 1, further comprising a reference bias circuit for generating the first and second bias signals, the reference bias circuit being operative to control the first and second bias signals as a function of a variation in at least one of a process, a supply voltage and a temperature condition of the buffer circuit.
16. The circuit of claim 1, further comprising a reference bias circuit operative to generate first and second bias signals for controlling a magnitude of a first current supplied by the current source and a magnitude of a second current sunk by the current sink, respectively, the reference bias circuit comprising:
an \u201cH\u201d bridge circuit including a second current source for supplying a third current as a function of the first bias signal, a second current sink for returning a fourth current as a function of the second bias signal, and a second switching circuit connected to the second current source at a first node and connected to the second current sink at a second node, the second switching circuit being operative to control a direction of current flowing through differential outputs of the \u201cH\u201d bridge circuit in response to at least a third control signal;
a second common mode detection circuit operative to detect an output common mode voltage of the \u201cH\u201d bridge circuit and to generate a fourth control signal representative of the output common mode voltage of the \u201cH\u201d bridge circuit;
a second common mode control circuit having a first terminal connected to the second current source and a second terminal connected to the second current sink, the second common mode control circuit being operative to selectively control the output common mode voltage of the \u201cH\u201d bridge circuit as a function of the fourth control signal;
a first operational amplifier including a first input connected to a first of the differential outputs of the \u201cH\u201d bridge circuit, a second input adapted to receive a first reference signal, and an output for generating the first bias signal; and
a second operational amplifier including a first input connected to a second of the differential outputs of the \u201cH\u201d bridge circuit, a second input adapted to receive a second reference signal, and an output for generating the second bias signal.
17. The circuit of claim 16, wherein the reference bias circuit is operative to control the first and second bias signals as a function of at least one of: (i) a variation in at least one of a process, a supply voltage and a temperature condition of the buffer circuit; and (ii) at least one of the first and second reference signals.
18. An integrated circuit including at least one differential buffer circuit, the at least one differential buffer circuit comprising:
a current source;
a current sink;
a switching circuit connected to the current source at a first node and connected to the current sink at a second node, the switching circuit being operative to selectively control a direction of current flowing through differential outputs of the at least one buffer circuit in response to at least a first control signal applied to the switching circuit;
a common mode detection circuit connected to the differential outputs of the at least one buffer circuit, the common mode detection circuit being operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage; and
a common mode control circuit having a first terminal connected to the current source and a second terminal connected to the current sink, the common mode control circuit being operative to selectively control the output common mode voltage of the at least one buffer circuit as a function of the second control signal.
19. The integrated circuit of claim 18, wherein the common mode control circuit comprises:
a first transistor having a first bias terminal adapted for connection to a first voltage source providing a first voltage, a second bias terminal connected to the first node of the switching circuit, and a control terminal adapted to receive the second control signal; and
a second transistor device having a first bias terminal adapted for connection to a second voltage source providing a second voltage, a second bias terminal connected to the second node of the switching circuit, and a control terminal adapted to receive the second control signal.
20. The integrated circuit of claim 18, wherein the common mode control circuit is operative to supply a first current to the first node of the switching circuit and to remove a second current from the second node of the switching circuit, a magnitude of the first and second currents being controlled as a function of the second control signal.
21. A bias circuit operative to generate at least first and second bias signals for biasing a differential buffer circuit, the bias circuit comprising:
an \u201cH\u201d bridge circuit including:
a current source;
a current sink; and
switching circuitry connected to the current source at a first node and connected to the current sink at a second node, the switching circuitry being operative to control a direction of current flowing through differential outputs of the \u201cH\u201d bridge circuit in response to at least a first control signal;
a common mode detection circuit connected to the differential outputs of the \u201cH\u201d bridge circuit, the common mode detection circuit being operative to detect an output common mode voltage of the \u201cH\u201d bridge circuit and to generate a second control signal representative of the output common mode voltage;
a common mode control circuit having a first terminal connected to the current source and a second terminal connected to the current sink, the common mode control circuit being operative to selectively control the output common mode voltage of the \u201cH\u201d bridge circuit as a function of the second control signal;
a first operational amplifier including a first input connected to a first of the differential outputs of the \u201cH\u201d bridge circuit, a second input adapted to receive a first reference signal, and an output for generating the first bias signal; and
a second operational amplifier including a first input connected to a second of the differential outputs of the \u201cH\u201d bridge circuit, a second input adapted to receive a second reference signal, and an output for generating the second bias signal.