Author: claimsbot

1. A semiconductor device, comprising:
a conductive well comprising a first conductive type impurity in a semiconductor substrate;
a device isolation film on one side of the conductive well; and
an insulating region below the device isolation film, including the first conductive type impurity and a second conductive type impurity.
2. The semiconductor device according to claim 1, wherein a concentration of the first conductive type impurity and a concentration of the second conductive impurity in the insulating region are substantially identical.
3. The semiconductor device according to claim 1, wherein the device isolation film includes a trench with a groove in and an inner side wall an insulating material to be filled in the inner side of the trench.
4. The semiconductor device according to claim 3, wherein the trench includes first side walls facing each other and second side walls angled from the first side walls.
5. The semiconductor device according to claim 4, wherein the trench includes a bottom surface, and a width of the bottom surface is greater than that of an opening of the trench.
6. The semiconductor device according to claim 1, wherein the device isolation film is over an entire vertical interface between the conductive well and the substrate, the substrate including a second conductive type impurity.
7. The semiconductor device according to claim 6, wherein the insulating region is entirely within a portion of the conductive well below device isolation film.
8. The semiconductor device according to claim 1, wherein the first conductive type impurity is an n type impurity.
9. The semiconductor device according to claim 8, wherein the second conductive type impurity is a p type impurity.
10. The semiconductor device according to claim 1, further comprising an NMOS transistor on the conductive well.
11. The semiconductor device according to claim 10, further comprising a PMOS transistor on the substrate in an active region adjacent to the device isolation.
12. The semiconductor device according to claim 11, wherein each of the NMOS transistor and the PMOS transistor comprises a gate electrode on a gate insulating layer, a spacer on a sidewall of the gate electrode, and n-type LDD regions and n+ type sourcedrain regions on opposite sides of the gate electrode.
13. A method of fabricating a semiconductor device comprising:
forming a trench in a semiconductor substrate;
forming an insulating region including a first conductive type impurity and a second conductive type impurity below the trench; and
filling the trench with an insulating material.
14. The method according to claim 13, wherein forming the trench includes:
forming a first trench by selectively etching the semiconductor substrate; and
forming a second trench which includes a lateral groove in the first trench by etching an inner surface of the first trench.
15. The method according to claim 14, wherein forming the second trench further includes:
forming a protective film on inner surfaces of the first trench;
removing a portion of the protective film; and
etching an exposed inner surface of the first trench using a remaining portion of the protective film as a mask.
16. The method according to claim 15, wherein the trench includes first side walls facing each other, second side walls angled away from the first side walls, and a bottom surface, the bottom surface having a width that is greater than that of an opening of the first trench.
17. The method according to claim 16, wherein etching the exposed inner surface of the first trench comprises wet etching.
18. The method according to claim 14, further comprising depositing a device isolation film in the trench.
19. The method according to claim 13, wherein forming the insulating region includes:
forming a conductive well by implanting the first conductive type impurity into the semiconductor substrate; and
forming the insulating region by implanting the second conductive impurity into a portion of the conductive well.
20. The method according to claim 19, wherein the second conductive type impurity has a concentration corresponding to or substantially equal to a concentration of the first conductive type impurity in the conductive well.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A voltage peak detector, comprising:
a first detector logic configured to detect a peak voltage of an input signal, the first detector logic having a circuit behavior that produces a leakage current that may alter the peak voltage;
a second detector logic configured to replicate the circuit behavior of the first detector logic including logic for detecting a replica peak voltage and being configured to produce a replica leakage current that is equivalent to the leakage current; and
the second detector logic being operably connected to the first detector logic to cause the replica leakage current to negate the leakage current.
2. The voltage peak detector of claim 1 where the second detector logic is identical to the flint detector logic.
3. The voltage peak detector of claim 1 further including a leak compensation circuit configured to operably connect the second detector logic to the first detector logic.
4. The voltage peak detector of claim 3 where the leak compensation circuit is a current minor.
5. The voltage peak detector of claim 1 where the first detector logic includes:
a capacitor configured to store the peak voltage of the input signal; and
a gate connected to the capacitor and being configured to control flow of the input signal to the capacitor where in an off state, the gate allows the leakage current to flow;
where the second detector logic includes:
a replica capacitor configured to store a replica peak voltage of a reference signal;
a replica gate connected to the replica capacitor and being configured to control flow of the reference signal to the replica capacitor, where in an off state, the replica gate allows the replica leakage current to flow that is identical to the leakage current; and
the replica leakage current being applied between the gate and the capacitor of the first detector logic to cancel effects of the leakage current.
6. The voltage peak detector of claim 5 where the gate and the replica gate are formed of one or more transistors.
7. The voltage peak detector of claim 1 where the first detector logic and the second detector logic are integrated circuits.
8. A system comprising:
a peak detector logic configured to detect a peak voltage of an input signal;
a replica peak detector logic configured to detect a replica peak voltage of a reference signal where the peak voltage and the replica peak voltage are substantially equal; and
a leak compensation logic configured to apply a replica leakage current from the replica peak detector logic to the peak detector logic that negates a leakage current from the peak detector logic to maintain the detected peak voltage at a desired peak value.
9. The system of claim 8 where the peak detector logic includes a storage device to store the peak voltage.
10. The system of claim 9 where the peak detector logic includes a gate connected to the storage device, the gate being configured to turn off when a desired peak voltage is stored in the storage device.
11. The system of claim 10 where the leak compensation logic is configured to apply the replica leakage current to a node between the gate and the storage device to negate the leakage current from the gate.
12. The system of claim 8 where the leak compensation logic is a current mirror circuit.
13. The system of claim 8 where the peak detector logic and the replica peak detector logic are equivalent circuits that are configured to produce an equivalent output voltage.
14. The system of claim 8 where:
the peak detector logic includes a means for detecting the peak voltage of the input signal;
the replica peak detector logic includes a means for detecting the replica peak voltage of the reference signal; and
the leak compensation logic includes a means for negating the leakage current.
15. The system of claim 8 where the system is embodied in an electronic device and operably connected to dynamically calibrate a clocking function.
16. The system of claim 15 where the electronic device includes a processor and where the system is operably connected to a clock that controls a receiving component of a point-to-point link.
17. The system of claim 8 where the system is processor chip.
18. A method of detecting a peak voltage, comprising:
detecting a first peak voltage of an input signal and producing a leakage current that may alter the peak voltage;
detecting a second peak voltage that replicates the detecting of the first peak voltage and producing a replica leakage current that is equivalent to the leakage current; and
negating the leakage current using the replica leakage current.
19. The method of claim 18 where the detecting the second peak voltage includes processing a second input signal having a desired peak voltage value.
20. The method of claim 18 where the method is implemented by a circuit and where:
the detecting the first peak voltage includes detecting with a first circuit having a circuit behavior that produces the leakage current after the peak voltage is detected; and
the detecting the second peak voltage includes detecting with a second circuit that replicates the circuit behavior of the first circuit including producing the replica leakage current that is used to negate the leakage current.
21. The method of claim 18 where the negating step is performed when the peak voltage is detected.
22. The method of claim 18 where the detecting includes storing the peak voltage in a capacitor.
23. The method of claim 18 further including calibrating a clocking function based on the peak voltage detected.
24. A computing system, comprising:
a processor configured to process executable instructions;
one or more memories configured to store at least the executable instructions;
one or more electronic components connected to each other with point-to-point links that communicate signals, the one or more electronic components including at least one receiver component configured to receive signals from a point-to-point link and being controlled by a clock;
a means for detecting a peak voltage of a voltage signal where the means for detecting the peak voltage may produce a leakage current that can affect the peak voltage, the means for detecting being configured for calibrating the clock using the peak voltage;
means for detecting a replica peak voltage that replicates the peak voltage;
a means for producing a replica leakage current from the means for detecting a replica peak voltage, the replica leakage current being equal to the leakage current; and
a means for negating the leakage current of the means for detecting the peak voltage with the replica leakage current so that the peak voltage is not affected by the leakage current.
25. A voltage detector system comprising:
a means for detecting a peak voltage of an input signal where a leakage current may be present; and
a means for replicating the means for detecting the peak voltage and for negating the leakage current using a replica leakage current that is equivalent to the leakage current.

1. An operating method of a storage device which includes a nonvolatile memory including a plurality of memory cells; and a memory controller adapted to control the nonvolatile memory, the operating method comprising:
receiving write data to be written at the plurality of memory cells;
generating a determination by determining whether the received write data is least significant bit (LSB) data to be written at the plurality of memory cells; and
encoding the write data according to the determination,
wherein the write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells, and
wherein the write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.
2. The operating method of claim 1, wherein LSB data, central significant bit (CSB) data and most significant bit (MSB) data are written at each of the plurality of memory cells,
wherein data that is written as LSBs of data to be written at the plurality of memory cells and is first received is the LSB data,
wherein data that is written as CSBs of data to be written at the plurality of memory cells and is received following the LSB data is the CSB data,
wherein data that is written as MSBs of data to be written at the plurality of memory cells and is received following the CSB data is the MSB data, and
wherein the CSB data is lower data of the MSB data, and the LSB data is lower data of the MSB data and CSB data.
3. The operating method of claim 1, wherein each of the plurality of memory cells has one of at least first to eighth threshold voltage states according to LSB data, central significant bit (CSB) data, and most significant bit (MSB) data, and
wherein when the write data is the LSB data, the encoding the write data according to the determination includes decoding the LSB data such that a number of bits in the write data corresponding to an LSB value that is the same as an LSB value of a highest threshold voltage state is reduced, the highest threshold voltage state being a highest one of the at least first to eighth threshold voltage states.
4. The operating method of claim 3, wherein when the write data is the CSB data,
the operating method further comprises:
detecting bits, from among the encoded LSB data, having a same value as the LSB value of the highest threshold voltage states, and

the encoding the write data according to the determination includes encoding the CSB data is such that, with respect to first data, a number of bits in the first data corresponding to a CSB value that is the same as a CSB value of the highest threshold voltage state, is reduced,
the first data being data, from among the write data, for which values of the encoded LSB data are the same as the LSB value of the highest threshold voltage state.
5. The operating method of claim 4, wherein when the write data is the MSB data,
the operating method further comprises:
detecting bits, from among the encoded LSB data, having a same value as the LSB value of the highest threshold voltage states,
detecting bits, from among the encoded CSB data, having a same value as the CSB value of the highest threshold voltage states, and

the encoding the write data according to the determination includes encoding the MSB data such that, with respect to second data, a number of bits in the second data corresponding to a MSB value that is the same as a MSB value of the highest threshold voltage state, is reduced,
the second data being data, from among the write data, for which values of the encoded LSB data are the same as the LSB value of the highest threshold voltage state and values of the encoded CSB data are the same as the CSB value of the highest threshold voltage state.
6. The operating method of claim 1, wherein the encoding the write data according to the determination includes encoding the write data such that,
a value of a first portion of the write data is changed according to either,
the write data, or
a combination of the write data and encoding data of the lower data, and

a value of a second portion of the write data is changed according to the write data regardless of the encoding data of the lower data.
7. The operating method of claim 1, wherein the encoding the write data according to the determination includes encoding the write data such that the write data is encoded according to encoding data of second data to be written at second memory cells adjacent to the plurality of memory cells.
8. The operating method of claim 7, further comprising:
writing the encoded write data such that at least an LSB, a CSB, and an MSB are written at each of the plurality of memory cells and each of the second memory cells,
wherein each of the plurality of memory cells and each of the second memory cells has one of the at least first to at least eight threshold voltage states, the at least first to at least eighth threshold voltage states each corresponding to values for an LSB, a CSB, and an MSB,
wherein locations of bits, corresponding to a highest threshold voltage state, from among at least first through eighth threshold voltage states, are detected from the encoding data of the second data, and
wherein the write data is encoded such that data corresponding to a lowest threshold voltage, from among the at the least first through eighth threshold voltage states, are not written in memory cells at the detected locations.
9. The operating method of claim 1, wherein the write data is first write data and the method further comprises:
receiving first data; and
dividing the first data into the first write data, second write data, and third write data,
wherein the first write data is selected as the LSB data to be written at the plurality of memory cells as first bits, the second write data is selected as the CSB data to be written at the plurality of memory cells as second bits, and the third write data is selected as the MSB data to be written at the plurality of memory cells as third bits.
10. The operating method of claim 9, wherein the nonvolatile memory further comprises:
first latches, second latches, and third latches connected to the plurality of memory cells, respectively;
second memory cells connected to a same word line as the plurality of memory cells; and
fourth latches, fifth latches, and sixth latches connected to the second memory cells, respectively,
wherein the operating method further includes,
loading encoding data of the first write data on the first latches;
loading encoding data of the second write data on the second latches; and
loading encoding data of the third write data on the third latches.
11. The operating method of claim 10, further comprising:
respectively loading next encoding data on the fourth latches, the fifth latches, and the sixth latches, and then, writing the data loaded on the first to sixth latches at the plurality of memory cells and the second memory cells.
12. An operating method of a storage device which includes a nonvolatile memory including a plurality of memory cells; and a memory controller adapted to control the nonvolatile memory, the operating method comprising:
receiving write data to be written, as a plurality of data units, to the plurality of memory cells,
each of the plurality of data units corresponding to one of at least first through eighth threshold voltages,
each of the at least first through eighth threshold voltages corresponding to a different one of a plurality of multi-bit data values,
each of the multi-bit data values including a least significant bit (LSB), at least one central significant bit (CSB), and a most significant bit (MSB);
dividing the write data based on significance of bits of the write data;
encoding the write data by,
encoding LSB data, from among the write data,
encoding CSB data, from among the write data, based on LSB data corresponding to the CSB data, and
encoding MSB data, from among the write data, based on LSB data and CSB data corresponding to the MSB data.
13. The method of claim 12, wherein the encoding includes encoding the write data such that a number of data units, from among the plurality of data units, having a same multi-bit data value as a highest multi-bit data value is reduced,
the highest multi-bit data value being the multi-bit data value, from among the plurality of multi-bit data values, to which a highest threshold voltage state corresponds,
the highest threshold voltage state being a highest one of the at least first through eighth threshold voltage states.
14. The method of claim 12, wherein the CSB data includes a first plurality of CSBs and a second plurality of CSBs, and the encoding includes encoding the CSB data such that,
values of the first plurality of CSBs are changed based on,
a combination of the first CSBs and bits of encoding data of the LSB data corresponding to the first CSBs, and

values of the second plurality of CSBs are changed based on the second plurality of CSBs regardless of the encoding data of the LSB data.
15. The method of claim 12, wherein the MSB data includes a first plurality of MSBs and a second plurality of MSBs, and the encoding includes encoding the MSB data such that,
values of the first plurality of MSBs are changed based on,
a combination of the first MSBs, bits of encoding data of the CSB data corresponding to the first MSBs, and bits of encoding data of the LSB data corresponding to the first MSBs, and

values of the second plurality of MSBs are changed based on the second plurality of MSBs regardless of the encoding data of the LSB data and regardless of the encoding data of the CSB data.
16. The method of claim, 12, wherein the nonvolatile memory comprises a three-dimensional memory array which includes the plurality of memory cells.
17. The method of claim 16, wherein the three-dimensional memory array is monolithically forms in one or more physical levels of memory cells having active areas disposed above a silicon substrate.
18. The method of claim 16, wherein each of the memory cells includes a charge trap later.
19. The method of claim 16, wherein word lines andor bit lines in the three-dimensional array are shared between levels.
20. The method of claim 12, wherein the nonvolatile memory includes a plurality of strings arranged in rows and columns on a substrate,
wherein each string includes at least one select transistor and memory cells stacked on a direction perpendicular to the substrate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Sensor for measuring the partial pressure of a gas in a gaseous medium, of the type comprising an electrochemical cell (2) and a porous diffusion barrier situated upstream of said cell along the course of said gaseous medium, said diffusion barrier comprising a porous membrane (10) having very fine pores, situated above an orifice (7) made in a component surmounting a casing (1) enclosing said electrochemical cell (2), characterized in that it comprises:
a cap (3) surmounting said casing (1) in a leaktight manner, said cap (3) including or consisting of a first component (4) provided with a central recess (5) in the bottom of which said orifice (7) is made, a housing (9) being provided in the bottom (6) of said recess around said orifice (7) so as to place said porous membrane (10) therein;
a second component (11) applying said membrane (10) against the bottom (6) of said housing (9) with a clearance between said second component (11) and the lateral wall of the housing (9) permitting the passage of the gaseous medium to be analyzed toward said membrane (10); and
a third component (12) held in said central recess (5) of said first component (4) in such a way as to exert on said second component (11) the pressure required for the application of said membrane (10) against the bottom (6) of said recess (9), and comprising at least one orifice (13, 13) permitting the passage of said gaseous medium from outside the sensor up to said membrane (10).
2. Sensor according to claim 1, characterized in that said first (4), second (11) and third (12) components are made of a corrosion-insensitive metallic material exhibiting low expansion between 10 and 40 C., such as SUS 316L stainless steel.
3. Sensor according to claim 1 or 2, characterized in that said cap (3) comprises a polymer envelope laterally jacketing said first metal component, and in that said envelope (8) ensures leaktight contact between the cap (3) and the casing (1) enclosing the electrochemical cell (2).
4. Sensor according to one of claims 1 to 3, characterized in that the central recess (5) of the first component comprises a thread on its lateral wall, and in that the third component (12) comprises on its external wall a thread corresponding to the previous one, so as to ensure the securing together of the first (4) and third (12) components and the holding of the third component (12) in a position where it can ensure the application of the second component (11) against the porous membrane (10).