Author: claimsbot

What is claimed is:

1. An apparatus for catalyzing a reaction on a substrate comprising:
a light source;
a micromirror positioned to redirect light from said light source toward said substrate;
a computer connected to, and controlling, said micromirror; and
a reaction chamber is placed in the path of light redirected by said micromirror, wherein light that is redirected by said micromirror catalyzes a chemical reaction proximate said substrate in said reaction chamber.
2. The apparatus of claim 1 wherein said light source is a UV light.
3. The apparatus of claim 1 wherein said light source produces visible light.
4. The apparatus of claim 1 further comprising a lens between said micromirror and said substrate.
5. The apparatus of claim 4 wherein said lens id further defined as a lens system, and wherein said lens system can change the magnification of light reflected by said micromirror.
6. The apparatus of claim 1 wherein said micromirror is further defined as a micromirror array.
7. The apparatus of claim 1 further comprising a diffusion lens between said light source and said micromirror.
8. The apparatus of claim 1 wherein said light interacts with a novolak resin proximate said substrate to produce a photoresist pattern.
9. The apparatus of claim 1 wherein said light catalyzes the synthesis of a nucleotide base proximate said substrate.
10. The apparatus of claim 1 wherein said light catalyzes the synthesis of an amino acid residue proximate said substrate.
11. The apparatus of claim 1 wherein said light catalyzes a reaction involving a molecule proximate said substrate.
12. The apparatus of claim 1 wherein said light crosslinks a molecule proximate said substrate.
13. The apparatus of claim 1 further comprising:
a reaction chamber disposed about said substrate;
one or more reactant lines connected to said reaction chamber;
one or more reaction chemicals connected to said reactant lines; and
a computer connected to, and controlling, the supply of said one or more reaction chemicals to said reaction chamber via said reactant lines.
14. The apparatus of claim 13 wherein said one or more of said reaction chemicals is involved in a chemical reaction when exposed to light.
15. An apparatus for catalyzing a reaction on a substrate comprising:
a light source;
a micromirror positioned to redirect light from said light source toward said substrate;
a reaction chamber disposed about said substrate;
one or more reactant lines connected to said reaction chamber;
one or more reaction chemicals connected to said reactant lines; and
a computer connected to, and controlling, said micromirror and the supply of said one or more reaction chemicals to said reaction chamber via said reactant lines, wherein a light catalyzable reaction occurs proximate to the site where light produced by said light source and redirected by said micromirror strikes said substrate.
16. The apparatus of claim 15 wherein said light source is a UV light.
17. The apparatus of claim 15 wherein said light source produces visible light.
18. The apparatus of claim 15 wherein said light source is a xenon lamp, or a mercury lamp, or a laser or a combination thereof.
19. The apparatus of claim 15 further a lens system comprising:
a diffusion lens between said light source and said micromirror; and
a lens between said micromirror and said substrate.
20. The apparatus of claim 15 wherein said micromirror is further defined as a micromirror array.
21. The apparatus of claim 15 wherein said light interacts with a novolak resin proximate said substrate to produce a photoresist pattern.
22. The apparatus of claim 15 wherein said light catalyzes the synthesis of a nucleotide base proximate said substrate.
23. The apparatus of claim 15 wherein said light catalyzes the synthesis of an amino acid residue proximate said substrate.
24. The apparatus of claim 15 wherein said light catalyzes a reaction involving a molecule proximate said substrate.
25. The apparatus of claim 15 wherein said light crosslinks a molecule proximate said substrate.
26. The apparatus of claim 15 further comprising a total internal reflection mirror disposed in a position to redirect light from said light source into said micromirror and from said micromirror array toward said substrate.
27. The apparatus of claim 15 wherein said substrate is mounted on a movable platform that can be controlled via a computer to allow for multiple repetitive exposures of said substrate to light reflected by said micromirror.
28. A method of patterning on a substrate comprising the steps of:
generating a light beam;
illuminating a micromirror with said light beam;
redirecting said light beam with said micromirror onto a substrate; and
catalyzing a light sensitive reaction proximate to the surface of said substrate using said redirected light beam in a predetermined pattern.
29. The method of claim 28 further comprising the step of controlling, using a computer, said micromirror.
30. The method of claim 28 wherein said step of redirecting said light beam is accomplished using a micromirror array.
31. The method of claim 28 wherein said illuminating light beam is further defined as a UV light.
32. The method of claim 28, further comprising the step of:
obtaining a substrate; and
depositing a novolak resin on said substrate prior to redirecting said a light beam to pattern said photoresist.
33. The method of claim 28, wherein said step of catalyzing a light sensitive reaction proximate to the surface of said substrate is further defined as patterning a photoresist disposed proximate said substrate.
34. The method of claim 28, further comprising the steps of:
positioning said substrate with a reaction chamber;
flooding said substrate with a light catalyzable reaction chemical; and
exposing said light catalyzable reaction chemical to light using said micromirror to catalyze a chemical reaction at the site where light strikes said substrate.
35. The method of claim 28 wherein said step of catalyzing a light sensitive reaction proximate to the surface of said substrate is further defined as the synthesis of a nucleotide base proximate said substrate.
36. The method of claim 28 wherein said step of catalyzing a light sensitive reaction proximate to the surface of said substrate is further defined as the synthesis of an amino acid residue proximate said substrate.
37. The method of claim 28 wherein said step of catalyzing a light sensitive reaction proximate to the surface of said substrate is further defined as involving a molecule proximate said substrate.
38. The method of claim 28 wherein said step of catalyzing a light sensitive reaction proximate to the surface of said substrate is further defined as crosslinking a molecule proximate said substrate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-3. (canceled)
4. A sensing pad comprising:
a sensing structure that includes:
a layer of force-sensing ink; and
a pair of electrodes coupled to the ink layer; and

a transmitter coupled to the electrodes, for transmitting a signal to a remote reader.
5. The sensing pad of claim 4, wherein the ink layer is between the electrodes.
6. The sensing pad of claim 5, wherein the electrodes are planar electrodes.
7. The sensing pad of claim 4, further comprising:
a substrate; and
an adhesive layer that adhesively couples the sensing structure to the substrate.
8. The sensing pad of claim 4, further comprising circuitry and a power source operatively coupled to the transmitter and the electrodes.
9. The sensing pad of claim 8, wherein the transmitter, the circuitry, and the power source are parts of a radio frequency identification (RFID) device.
10. The sensing pad of claim 4, as part of an item detection system.
11. The item detection system of claim 10, further comprising the reader for receiving signals from the sensing pad.
12. The item detection system of claim 10, wherein the item detection system includes multiple sensing pads.
13. The item detection system of claim 12, in combination with a shelf upon which the sensing pads are placed.
14. A method of detecting items at a specified location, comprising:
placing a sensing pad at the specified location; and
receiving a signal from the sensing pad when an event occurs regarding an item pressing against the sensing pad.
15. The method of claim 14,
wherein the placing includes placing a sensing pad that includes a force-sensing ink layer between a pair of electrodes; and
wherein the force-sensing ink layer changes electrical characteristics when the item is pressed against the sensing pad.
16. The method of claim 15,
wherein the sensing pad includes a transmitter operatively coupled to the electrodes; and
wherein the transmitter is configured to send the signal when the event occurs regarding an item pressing against the sensing pad.
17. The method of claim 16, wherein the sensing pad includes circuitry and a power source operatively coupled to the transmitter.
18. The method of claim 17,
wherein the transmitter, the circuitry, and the power source are parts of a radio frequency identification (RFID) device; and
wherein the signal is a radio frequency signal.
19. The method of claim 14, wherein the specified location includes a chair.
20. The method of claim 14, wherein the receiving includes receiving the signal at an inventory tracker.
21. The method of claim 20, wherein the specified location includes a shelf.
22. The method of claim 20, wherein the specified location includes a protrusion.
23. The method of claim 20, wherein the specified location includes a shopping cart.
24. The method of claim 14, wherein the placing includes adhesively attaching the sensing pad to an object.
25. The method of claim 14, wherein the receiving includes receiving a signal indicating placement of the item on the sensing pad.
26. The method of claim 14,
wherein the placing includes placing plural sensing pads at respective specified locations; and
wherein the receiving includes receiving signals from the plural sensing pads.
27. The method of claim 14, wherein the placing the sensing pad includes placing multiple sensing pads on a shelf.
28. The method of claim 27, wherein the receiving includes receiving a signal indicative of a total weight of items on the shelf.
29. The method of claim 27, wherein the receiving includes receiving a pad-specific signal, indicative at which of the pads the event occurs.
30. The method of claim 14, wherein the receiving includes receiving a signal indicative of a total number of the items on the sensing pad.
31. The method of claim 14, wherein the receiving includes receiving a signal indicative of a total weight of the items on the sensing pad.

1. A semiconductor memory device, comprising:
a memory cell array divided into a plurality of blocks, each of which includes a plurality of memory cells;
a plurality of row decoders which correspond to the blocks, each of the row decoders including an access information holder configured to hold access information indicating whether its corresponding row decoder has been accessed; and
an access information reader configured to read the access information held in the access information holders.
2. The semiconductor memory device according to claim 1, further comprising a first determination circuit configured to determine whether the row decoder to be accessed based on a designated block address has been accessed.
3. The semiconductor memory device according to claim 1, further comprising a second determination circuit configured to determine whether the row decoders other than the row decoder to be accessed based on a designated block address have been accessed.
4. The semiconductor memory device according to claim 1, further comprising a third determination circuit configured to determine whether the row decoder to be accessed based on a designated block address has been accessed and whether the row decoders other than the row decoder to be accessed based on the designated block address have been accessed.
5. The semiconductor memory device according to claim 4, wherein the third determination circuit comprises a plurality of test result determining circuits which correspond to the blocks,
each of the test result determining circuits compares the access information which is read by the access information reader with expected access information which is a theoretical expected value concerning access information specified based on the designated block address, and
each of the test result determining circuits outputs a test result signal indicating whether the access information matches with the expected access information.
6. The semiconductor memory device according to claim 1, wherein the access information held in the respective access information holders are allowed to be collectively reset by a reset signal.
7. The semiconductor memory device according to claim 1, wherein the access information holder is allowed to hold information that only one access has been made as the access information.
8. The semiconductor memory device according to claim 1, wherein the access information holder holds a first state in which no access has been made, a second state in which only one access has been made, and a third state in which two or more accesses have been made, as the access information.
9. The semiconductor memory device according to claim 1, wherein the access information holder comprises a latch circuit which shifts to a set state when being accessed once from a reset state, and shifts to a second reset state when being accessed once more from the set state, but does not shift to the set state even if it is accessed once more in the second reset state.
10. The semiconductor memory device according to claim 1, further comprising a fourth determination circuit configured to read the access information from the access information holders of all the row decoders and determine whether the row decoders corresponding to two or more blocks have been accessed.
11. The semiconductor memory device according to claim 10, wherein the fourth determination circuit comprises:
a first current generating circuit configured to generate a first current which is proportional to the number of the blocks had been accessed;
a second current generating circuit configured to generate a second current between a current flowing when one block has been accessed and a current flowing when two blocks have been accessed; and
a comparison circuit configured to compare the first current with the second current.
12. The semiconductor memory device according to claim 11, wherein the comparison circuit outputs a test result signal indicating a test pass when the first current is smaller than the second current, and outputs a test result signal indicating a teat failure when the first current is larger than the second current.
13. The semiconductor memory device according to claim 12, wherein the access information is read from the access information holders of all the row decoders and whether any block which has not accessed exists is determined.
14. A test method of a semiconductor memory device which comprises: a memory cell array divided into a plurality of blocks each of which including a plurality of memory cells; and a plurality of row decoders which correspond to the blocks, each of the row decoders including an access information holder configured to hold access information indicating whether its corresponding row decoder has been accessed, the test method comprising:
designating a block address and accessing the row decoder which corresponds to the block address;
reading the access information from all the access information holders;
determining whether the row decoder had been accessed is only the designated block address based on the read access information; and
determining whether all block addresses are designated, and when all the block addresses are not designated, designating a new block address and repeating the steps from the step of accessing the row decoder.
15. The test method of the semiconductor memory device according to claim 14,
wherein the step of determining whether the row decoder had been accessed is only the designated block address comprises:
comparing the access information which is read from the access information holder and expected access information which is a theoretical expected value concerning access information specified based on the designated block address, and
outputting a test result signal indicating whether the access information matches with the expected access information.
16. The test method of the semiconductor memory device according to claim 14, further comprising collectively resetting the access information held in the respective access information holders by a reset signal.
17. A test method of a semiconductor memory device which comprises: a memory cell array divided into a plurality of blocks each including a plurality of memory cells; and a plurality of row decoders which correspond to the blocks, each of the row decoders including an access information holder configured to hold access information indicating whether only one access has been made to its corresponding row decoder, the test method comprising:
designating all block addresses in sequence and accessing the row decoders corresponding to all the block addresses in sequence;
reading the access information from all the access information holders; and
determining whether only one access has been made to all the row decoders based on the read access information.
18. The test method of the semiconductor memory device according to claim 17, wherein the access information holder holds a first state in which no access has been made, a second state in which only one access has been made, and a third state in which two or more accesses have been made, as the access information.
19. The test method of the semiconductor memory device according to claim 17, wherein the access information holder comprises a latch circuit which shifts to a set state when being accessed once from a reset state, and shifts to a second reset state when being accessed once more from the set state, but does not shift to the set state even if it is accessed once more in the second reset state.
20. A test method of a semiconductor memory device which comprises: a memory cell array divided into a plurality of blocks each of which includes a plurality of memory cells; and a plurality of row decoders which correspond to the blocks, each of the row decoders including an access information holder configured to hold access information indicating whether its corresponding row decoder has been accessed, the test method comprising:
designating a block address and accessing the row decoder which corresponds to the block address;
reading the access information from all the access information holders;
determining whether row decoders corresponding to two or more blocks have been accessed based on the access information; and
determining whether all block addresses are designated, and when all the block addresses are not designated, designating a new block address and repeating the steps from the step of accessing the row decoder.
21. The test method of the semiconductor memory device according to claim 20, further comprising:
generating a first current which is proportional to the number of the blocks had been accessed;
generating a second current between a current flowing when one block has been accessed and a current flowing two blocks have been accessed; and
comparing the first current and the second current.
22. The test method of the semiconductor memory device according to claim 21, further comprising:
outputting a test result signal indicating a test pass when the first current is smaller than the second current, and
outputting a test result signal indicating a test failure when the first current is larger than the second current.
23. The test method of the semiconductor memory device according to claim 22, further comprising:
reading the access information from the access information holders of all the row decoders after all the blocks addresses are accessed, and
determining whether any block which has not accessed exists.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A container data center comprising:
a portable container;
a plurality of server cabinets accommodated in the container;
at least one shutter set on walls of the container;
a temperature sensor set outside the container to sense a temperature of air outside the container;
a humidity sensor set outside the movable container to sense a humidity of air outside the container; and
a controlling device to receive the sensed temperature and the sensed humidity, and compare the sensed temperature with a preset temperature and compare the sensed humidity with a preset humidity range, wherein when the sensed temperature is less than the preset temperature and the sensed humidity is in the preset humidity range, the controlling device opens the at least one shutter, when the sensed temperature is higher than the preset temperature or the sensed humidity is outside of the preset humidity range, the controlling device closes the at least one shutter.
2. The container data center of claim 1, wherein the temperature sensor is positioned close to the at least one shutter.
3. The container data center of claim 1, wherein the humidity sensor is positioned close to the at least one shutter.
4. The container data center of claim 1, wherein the preset temperature is 25 degrees celsius, and the preset humidity range is 40%-80%.
5. A method for controlling airflow into a container data center, the container data center comprising a portable container, a temperature sensor, a humidity sensor, at least one shutter, and a controlling device, the method comprising:
sensing a temperature of air outside the container through the temperature sensor and transmitting the sensed temperature to the controlling device;
sensing a humidity of air outside the container through the humidity sensor and transmitting the sensed humidity to the controlling device;
comparing the sensed temperature with a preset temperature and comparing the sensed humidity with a preset humidity range, through the controlling device;
opening the at least one shutter through the controlling device when the sensed temperature is less than the preset temperature and the sensed humidity is in the preset humidity range; and
closing the at least one shutter through the controlling device when the sensed temperature is higher than the preset temperature or the sensed humidity is outside of the preset humidity range.
6. The method of claim 5, wherein the preset temperature is 25 degrees celsius, and the preset humidity range is 40%-80%.