Author: claimsbot

1. A backlight module, comprising:
a light guide plate;
a housing clipped to the light guide plate, wherein the housing and the light guide plate form a disposed space; and
at least one light-emitting diode light bar disposed in the disposed space and providing the light guide plate with at least one light, wherein the light-emitting diode light bar comprises a flexible circuit board and a plurality of light-emitting diodes, and the flexible circuit board comprises a first portion and at least two second portions, wherein the light-emitting diodes are disposed on the first portion of the flexible circuit board, and the second portions are stacked with respect to each other.
2. The backlight module according to claim 1, wherein the first portion of the flexible circuit board is between the light guide plate and the second portions of the flexible circuit board.
3. The backlight module according to claim 2, wherein the housing further comprises a first side plate, a second side plate and a third side plate, and the light guide plate is positioned between the first side plate and the third side plate, wherein the first portion and the second portions of the flexible circuit board are disposed on the first side plate.
4. The backlight module according to claim 2, wherein the housing further comprises a first side plate, a second side plate and a third side plate, and the light guide plate is positioned between the first side plate and the third side plate, wherein the first portion of the flexible circuit board is disposed on the first side plate, and the second portions are disposed on the second side plate.
5. The backlight module according to claim 1, wherein the light-emitting diode light bar further comprises a thermal conductive material layer connected between the light-emitting diodes and the flexible circuit board.
6. The backlight module according to claim 1, wherein the second portions of the flexible circuit board are adhered to each other with at least one adhesive layer.
7. The backlight module according to claim 1, wherein the housing is composed of a reflective material.
8. A backlight module, comprising:
a light guide plate;
a housing clipped to the light guide plate, wherein the housing and the light guide plate form a disposed space; and
at least one light-emitting diode light bar disposed in the disposed space and providing the light guide plate with at least one light, wherein the light-emitting diode light bar comprises a flexible circuit board and a plurality of light-emitting diodes, the flexible circuit board comprises a first region and a second region, and the light-emitting diodes are disposed on the first region, wherein a thickness of a structure of the flexible circuit board in the second region is greater than a thickness of a structure of the flexible circuit board in the first region.
9. The backlight module according to claim 8, wherein the first region is between the light guide plate and the second region.
10. The backlight module according to claim 9, wherein the housing further comprises a first side plate, a second side plate and a third side plate, the light guide plate is positioned between the first side plate and the third side plate, and the second region and the first region are disposed on the first side plate.
11. The backlight module according to claim 8, wherein the light-emitting diode light bar further comprises a thermal conductive material layer connected between the light-emitting diodes and the flexible circuit board.
12. The backlight module according to claim 8, wherein a structure of the flexible circuit board in the second region is composed of a portion of the flexible circuit board in a stack.
13. The backlight module according to claim 12, wherein the stack of the portion of the flexible circuit board in the second region includes at least two layers, and the layers are adhered to each other with at least one adhesive layer.
14. The backlight module according to claim 8, wherein the housing is composed of a reflective material.
15. A liquid crystal display, comprising:
a liquid crystal display panel; and
a backlight module disposed on a rear side of the liquid crystal display panel, wherein the backlight module comprises:
a light guide plate;
a housing clipped to the light guide plate, wherein the housing and the light guide plate form a disposed space; and
at least one light-emitting diode light bar disposed in the disposed space and providing the light guide plate with at least one light, wherein the light-emitting diode light bar comprises a flexible circuit board and a plurality of light-emitting diodes, and the flexible circuit board comprises a first portion and at least two second portions, wherein the light-emitting diodes are disposed on the first portion of the flexible circuit board, and the second portions are stacked with respect to each other.
16. The liquid crystal display according to claim 15, wherein the first portion of the flexible circuit board is between the light guide plate and the second portions of the flexible circuit board.
17. The liquid crystal display according to claim 16, wherein the housing further comprises a first side plate, a second side plate and a third side plate, and the light guide plate is positioned between the first side plate and the third side plate, wherein the first portion and the second portions of the flexible circuit board are disposed on the first side plate.
18. The liquid crystal display according to claim 15, wherein the light-emitting diode light bar further comprises a thermal conductive material layer connected between the light-emitting diodes and the flexible circuit board.
19. The liquid crystal display according to claim 15, wherein the second portions of the flexible circuit board are adhered to each other with at least one adhesive layer.
20. The liquid crystal display according to claim 15, wherein the housing is composed of a reflective material.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A logic circuit, comprising:
a first field effect transistor (FET) circuit of first type; and
a second FET circuit of second type that is coupled to the first FET circuit, wherein the first FET circuit and the second FET circuit share a floating gate terminal that includes at least in part doped implants of first type.
2. The circuit of claim 1, wherein
the entire shared floating gate terminal is doped with implants of first type.
3. The circuit of claim 1, wherein
a source terminal of the first FET circuit is coupled to a high supply voltage;
a drain terminal of the second FET circuit is coupled to a drain terminal of the first FET circuit such that an output voltage is provided from the drain terminal of the second FET circuit;
a source terminal of the second FET circuit is coupled to a low supply voltage; and
the shared gate terminal is coupled to an input voltage for programming the logic circuit such that the logic circuit is arranged to operate as a non-volatile memory cell.
4. The circuit of claim 3, further comprising:
a charge adjustment circuit is arranged to be coupled with the input voltage for programming and adjusting a charge storage level of the shared floating gate of the logic circuit based on an adjustment signal such that the logic circuit is employed as an enhanced retention non-volatile memory (NVM) cell.
5. The circuit of claim 3, further comprising:
a programming circuit is arranged to provide the input voltage for the charge adjustment circuit based on a programming signal.
6. The circuit of claim 3, further comprising:
a third FET circuit of second type and a fourth FET circuit of first type such that the logic circuit is configured to operate as a NOR circuit, wherein
a drain terminal of the third FET circuit is coupled to the drain terminal of the first FET circuit and the drain terminal of the second FET circuit;
a source terminal of the third FET circuit is coupled to the source terminal of the second FET circuit and a low supply voltage;
a drain terminal of the fourth FET circuit is coupled to the source terminal of the first FET circuit;
a source terminal of the fourth FET circuit is coupled to a high supply voltage; and
the third FET circuit and the fourth FET circuit share a second floating gate terminal that is arranged to receive a second input voltage.
7. The circuit of claim 3, further comprising:
a third FET circuit of second type and a fourth FET circuit of first type such that the logic circuit is configured to operate as a NAND circuit, wherein
a drain terminal of the third FET circuit is coupled to the drain terminal of the first FET circuit and a drain terminal of the fourth FET circuit;
a source terminal of the third FET circuit is coupled to the drain terminal of the second FET circuit;
a source terminal of the fourth FET circuit is coupled to the source terminal of the first FET circuit and a high supply voltage; and
the third FET circuit and the fourth FET circuit share a second floating gate terminal that is arranged to receive a second input voltage.
8. The circuit of claim 1, wherein
the first type is p-type and the second type is n-type.
9. The circuit of claim 1, wherein
the first FET circuit comprises at least one of: a MOSFET, a FinFET, and a MESFET.
10. The circuit of claim 1, wherein
the shared gate terminal is adapted to be charged by at least one of: impact-ionized hot-electron injection, Fowler-Nordheim (FN) tunneling, channel hot-electron injection, and band-to-band tunneling induced electron injection.
11. The circuit of claim 1, wherein
the shared gate terminal is adapted to be discharged by FN tunneling, impact-ionization induced hot-hole injection, and band-to-band tunneling induced hot-hole injection.
12. The circuit of claim 1, wherein
the entire shared floating gate terminal is doped with implants of p-type.
13. The circuit of claim 1, wherein
the shared floating gate terminal is partially doped with implants of p-type and n-type;
14. A dual transistor, NVM cell circuit, comprising:
a substrate that includes impurities of p-type;
a p-well within the substrate that includes impurities of p-type;
a first surface region and a second surface region in the p-well that include impurities of n-type and define a first channel within the p-well;
a first portion of a shared gate disposed over the first channel, the first portion of the shared gate having doped implants of p-type impurities;
an n-well in the substrate that includes impurities of n-type;
a third surface region and a fourth surface region within the n-well that include impurities of p-type and define a second channel within the n-well;
a fifth surface region within the n-well that includes impurities of n-type; and
a second portion of the shared gate disposed over the second channel, the second portion of the shared gate having doped implants of p-type impurities.
15. The circuit of claim 14, further comprising:
a first contact region over the first surface region that is arranged to receive a low supply voltage;
a first field oxide layer between the second surface region and the third surface region that defines a second contact region, wherein the second contact region is arranged to provide an output voltage;
a second field oxide layer between the fourth surface region and the fifth surface region that defines a third contact region, wherein the third contact region is arranged to receive a high supply voltage; and
a third field oxide layer between the n-well and the substrate along an opposite edge of the n-well with respect to the first field oxide layer.
16. The circuit of claim 14, wherein
the shared gate is arranged to receive an input voltage for programming the NVM cell circuit.
17. The circuit of claim 14, wherein
the first portion of the shared gate disposed over the first channel is doped partially with implants of p-type and n-type impurities.
18. The circuit of claim 14, wherein
the p-well includes substantially same concentration of impurities of p-type as the substrate.
19. The circuit of claim 14, wherein
the circuit is of Silicon-On-Insulator (SOI) type and the substrate comprises a relatively thin layer of Si deposited over a thin film of oxide embedded onto a relatively thick layer of Si.
20. The circuit of claim 14, wherein
the circuit is of Silicon-On-Sapphire (SOS) type and the substrate comprises a relatively thin layer of Si over sapphire (Al2O3).
21. The circuit of claim 14, wherein
the circuit is of GaAs type and the substrate comprises a thin layer of Ga deposited over a layer of As.
22. A method for creating a dual transistor, NVM cell circuit comprising:
forming a substrate that includes doped implants of a first type;
forming a first well within the substrate that includes doped implants of a first type;
forming a first surface region and a second surface region in the first well that include impurities of a second type and define a first channel within the substrate;
forming a second well in the substrate that includes impurities of the second type;
forming a third surface region and a fourth surface region within the second well that include impurities of the first type and define a second channel within the second well;
forming a fifth surface region within the second well that includes impurities of the first type; and
forming a shared gate disposed over the first channel and the second channel, the shared gate having doped implants of the first type impurities.
23. The method of claim 22, further comprising:
forming a first contact region over the first surface region that is arranged to receive a low supply voltage;
forming a first field oxide layer between the second surface region and the third surface region that defines a second contact region, wherein the second contact region is arranged to provide an output voltage;
forming a second field oxide layer between the fourth surface region and the fifth surface region that defines a third contact region, wherein the third contact region is arranged to receive a high supply voltage; and
forming a third field oxide layer between the well and the substrate along an opposite edge of the well with respect to the first field oxide layer.
24. The method of claim 23, wherein a portion of the shared gate disposed over the first channel is partially doped with implants of the first type and the second type.
25. The method of claim 23, wherein the doped implants of the first type includes p-type and the doped implants of the second type includes n-type.
26. A method for creating a dual transistor, NVM cell circuit comprising:
forming a substrate that includes doped implants of a first type;
forming a first surface region and a second surface region in the substrate that include impurities of a second type and define a first channel within the substrate;
forming a well in the substrate that includes impurities of the second type;
forming a third surface region and a fourth surface region within the well that include impurities of the first type and define a second channel within the well;
forming a fifth surface region within the well; and
forming a shared gate disposed over the first channel and the second channel, the shared gate having doped implants of the first type impurities.
27. The method of claim 26, further comprising:
forming a first contact region over the first surface region that is arranged to receive a low supply voltage;
forming a first field oxide layer between the second surface region and the third surface region that defines a second contact region, wherein the second contact region is arranged to provide an output voltage;
forming a second field oxide layer between the fourth surface region and the fifth surface region that defines a third contact region, wherein the third contact region is arranged to receive a high supply voltage; and
forming a third field oxide layer between the well and the substrate along an opposite edge of the well with respect to the first field oxide layer.
28. The method of claim 27, wherein a portion of the shared gate disposed over the first channel is partially doped with implants of the first type and the second type.
29. The method of claim 27, wherein the doped implants of the first type includes p-type and the doped implants of the second type includes n-type.

1. A method for packaging a user’s personal computing environment on a client platform and mobilizing it for transfer over a network, said method comprising the steps of:
providing a remote server enabled for communication with the client platform;
storing the user’s personal computer environment on said client platform and on said remote server;
enabling said user to log onto said client platform;
said client platform automatically connecting to said remote server; and
mirroring said user’s computing environment on said client platform and said remote server.
2. The method according to claim 1, wherein said computing environment comprises:
(1) said user’s personal data;
(2) said user’s application settings; and
(3) software.
3. The method according to claim 2, wherein said software comprises open source software.
4. The method according to claim 2, wherein said software comprises a combination of open source software and proprietary software.
5. The method according to claim 1, said mirroring step further comprising:
incorporating a graphics system, a messaging system, and a distributed file sharing system to enable an interface between the user and selected application software and data.
6. The method according to claim 5, wherein said messaging system includes email, instant messaging, or file sharing.
7. The method according to claim 5, wherein said distributed file sharing system further comprises a plurality of hooks.
8. The method according to claim 7, said hooks being selected from the group consisting of:
conflict resolution;
administrative tools;
data layout; and
hoarding.
9. The method according to claim 1, said mirroring step further comprising:
simultaneously storing said user’s personal data and application data on the local client platform and the remote server as such data may change during a user session.
10. The method according to claim 1, said mirroring step further comprising:
maintaining computer applications current using automatic updating that monitors the software and confirms, updates, and patches applications as needed by the user.
11. The method according to claim 1, said mirroring step further comprising:
managing authentication, local and remote caching of personalized data and software applications, and rights management of proprietary applications through a secure authentication and encryption system.
12. The method according to claim 1, wherein said step to enable said user to log onto said client platform further comprises:
displaying a login screen;
requiring said user to verify his or her identity;
validating said user as a subscribed customer; and
upon validation, displaying a personal desktop for said user.
13. The method according to claim 12, further comprising:
after requiring said user to verify his or her identity, requiring said user to input a personal identification number.
14. The method according to claim 12, wherein said step of requiring said user to verify his or her identity is performed by a biometric device.
15. The method according to claim 1, further comprising:
enabling remote control access of said client terminal over a secure network.
16. The method according to claim 16, wherein said remote access includes access to the user’s applications and data.
17. The method according to claim 1, wherein said network comprises a secure network.
18. A system for packaging a user’s personal computing environment on a client platform and mobilizing it for transfer over a network, said system comprising:
a remote server enabled for communication with the client platform;
a secure authentication and encryption system that enables said user to log onto said client platform and to automatically connect said client platform to said remote server; and
a software manager that monitors the user’s personal computing environment and automatically mirrors said user’s computing environment on said client platform and said remote server.
19. The system according to claim 18, wherein said software manager resides on said remote server.
20. The system according to claim 18, wherein said software manager simultaneously stores said user’s personal data and application data on the local client platform and the remote server and updates such data as it may change during a user session.
21. The system according to claim 18, wherein said software manager maintains said user’s computer applications current using automatic updating that monitors the software and confirms, updates, and patches applications as needed by the user.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A one swipe anti-bacteria disposable toilet seat wipe comprising:
an absorbent first layer infused with an anti-bacteria solution;
a second layer, being substantially impervious to the solution of said first layer and having a top side and a bottom side, where the top side is attached to said first layer;
a substantially dry and absorbent third layer that is attached to the bottom side of said second layer.
2. The one swipe anti-bacteria disposable toilet seat wipe of claim 1 wherein said solution infused in the first layer is capable of cleansing the toilet seat on contact.
3. The one swipe anti-bacteria disposable toilet seat wipe of claim 2 wherein the wipe is substantially biodegradable as to be easily disposed of by flushing down the toilet.
4. The one swipe anti-bacteria disposable toilet seat wipe of claim 3 further comprising a sealable plastic pouch to enclose the wipe;
said sealable pouch having a pull tab to break the seal on the pouch.
5. The one swipe anti-bacteria disposable toilet seat wipe of claim 4 wherein said solution further comprises an aqueous alcoholic composition to speed drying.
6. The one swipe anti-bacteria disposable toilet seat wipe of claim 4 wherein said solution is selected from the group consisting of: a germicide, a sterilizer, an aqueous alcoholic composition, an emollient, a fragrance, and combinations thereof.
7. The one swipe anti-bacteria disposable toilet seat wipe of claim 4 wherein said solution is selected from the group consisting of: a phenol compound, aloe vera, an aqueous alcoholic composition, hydro-peroxide, leptospermum scoparium, kunzea ericoides, and combinations thereof.
8. The one swipe anti-bacteria disposable toilet seat wipe of claim 2 wherein said solution is selected from the group consisting of: purified or distilled water, liquid soap, zinc pyrithione, black walnut green hull extract, olive leaf, aloe vera, leptospermum scoparium, kunzea ericoides, and combinations thereof.
9. A wiping device for cleansing toilet seats on contact comprising:
a first layer having a top side and a bottom side;
said first layer including an infusion of a liquid anti-bacteria means formulated to kill germs and bacteria on contact;
said first layer being composed of a biodegradable sanitary paper;
a second layer having a top side and a bottom side;
said top side of the second layer being attached to the bottom side of said first layer;
said second layer being composed of an ultra thin biodegradable plastic to prevent moisture seepage between the layers;
a third layer having a top side and a bottom side;
said third layer being comprised of a substantially dry absorbent biodegradable material;
said top side of the third layer being attached to the bottom side of the second layer.
10. The wiping device of claim 9 further comprising a sealable plastic pouch to enclose the wipe;
said sealable pouch having a pull tab to break the seal on the pouch.
11. The wiping device of claim 10 wherein said sealable plastic pouch is biodegradable.