Author: claimsbot

1. A light guide plate unit comprising:
a light guide plate having a light incidence section provided along at least one side face of the light guide plate; and
a plurality of light sources that cause light to enter the light guide plate through the light incidence section,
the light incidence section including:
a plurality of first light incidence planes arranged along the side face;
a plurality of light guide sections formed in such a manner as to protrude outward from spaces between the plurality of first light incidence planes on the side face, respectively; and
a plurality of second light incidence planes positioned as protruding surfaces of the plurality of light guide sections, respectively,

the plurality of light sources including:
a plurality of first light sources provided in such a manner as to face the plurality of first light incidence planes, respectively; and
a plurality of second light sources provided in such a manner as to face the plurality of second light incidence planes, respectively.
2. The light guide plate unit as set forth in claim 1, wherein each of the light guide sections has a columnar shape or a conical shape or includes (i) a columnar region extending out of the light guide plate from the side face and (ii) a region protruding further outward from the columnar region and having a shape that gets wider toward an outside.
3. The light guide plate unit as set forth in claim 1, wherein the light incidence section is provided along plural side faces of the light guide plate.
4. A surface light source device comprising a light guide plate unit as set forth in claim 1.
5. A display device comprising a surface light source device as set forth in claim 4.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for providing direct bonding of wires to silicon for microelectronics and microelectromechanical systems (MEMS), said method comprising:
preparing a rough pothole during one of the many deep etch steps already performed in microelectronics and MEMS fabrication;
roughening of the smooth silicon surface in and around said rough pothole; and
plastically deforming a ball-bond into said rough pothole, such that the interconnection will eliminate a costly metallization layer, and thereby lower fabrication expenses and enable further high temperature processing.
2. The method according to claim 1, wherein the metallization layer eliminated is a gold layer.
3. The method according to claim 1, wherein the metallization layer eliminated is an aluminum layer.
4. The method according to claim 1, wherein the method is part of semiconductor device fabrication.
5. The method according to claim 4, wherein said fabrication uses passivation layers.
6. The method according to claim 5, wherein the passivation layers are used as hard masks.
7. The method according to claim 5, wherein the passivation layers are used as electric isolation.
8. The method according to claim 1, wherein said pothole is a silicon Deep Reactive Ion Etching (DRIE) pothole.
9. A system for providing direct bonding of wires to silicon for microelectronics and microelectromechanical systems (MEMS), said system comprising:
means for preparing a rough pothole during one of the many deep etch steps already performed in microelectronics and MEMS fabrication;
means for roughening of the smooth silicon surface in and around said rough pothole; and
means for plastically deforming a ball-bond into said rough pothole, such that the interconnection will eliminate a costly metallization layer, and thereby lower fabrication expenses and enable further high temperature processing.
10. The system according to claim 9, wherein the metallization layer eliminated is a gold layer.
11. The method according to claim 1, wherein the metallization layer eliminated is an aluminum layer.
12. The system according to claim 9, wherein the system is part of semiconductor device fabrication.
13. The system according to claim 12, wherein said fabrication uses passivation layers.
14. The system according to claim 13, wherein the passivation layers are used as hard masks.
15. The system according to claim 13, wherein the passivation layers are used as electric isolation.
16. The system according to claim 9, wherein said pothole is a silicon Deep Reactive Ion Etching (DRIE) pothole.

1. A method comprising:
a) providing a steel substrate;
b) contacting the steel substrate with a pre-plating composition comprising one or more organic sulfonic acids, salts or anhydrides thereof and one or more grain refiners, wherein the pre-plating composition does not include metal or metal ions;
c) electrolytically polarizing the steel substrate in contact with the pre-plating composition by anodic polarization followed by cathodic polarization to activate a surface of the steel substrate; and
d) electrolytically plating a tin or a tin alloy layer on the activated surface of the steel substrate with a tin or a tin alloy electroplating bath.
2. The method of claim 1, wherein the tin or tin alloy layer comprises a FeSn2 intermetallic layer of 0.1-1.4 gm2.
3. The method of claim 1, wherein the one or more grain refiners are chosen from carboxy aromatic compounds, alkoxylates, alkylene oxide compounds and polyalkylene glycols.
4. The method of claim 3, wherein the one or more grain refiners are in amounts of 0.01 gL to 20 gL.
5. The method of claim 1, wherein the pre-plating composition further comprises one or more metal solubilizing agents.
6. The method of claim 1, wherein the pre-plating composition further comprises one or more inorganic acids.
7. The method of claim 1, wherein the one or more organic sulfonic acids, salts or anhydrides thereof are in amounts of 0.1 gL to 50 gL.
8. The method of claim 1, wherein the pre-plating composition further comprises one or more tin plating promoting agents.
9. The method of claim 8, wherein the one or more tin plating promoting agents are chosen from reducing agents and brightening agents.
10. The method of claim 1, wherein the pre-plating composition further comprises one or more buffering agents.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming a transistor comprising:
forming a barrier layer, the barrier layer including AlGaN;
forming a layer of Si3N4 that touches the barrier layer;
forming a layer of SiO2 that touches the layer of Si3N4; and
forming a metal gate that touches and lies over the layer of SiO2.
2. The method of claim 1 wherein:
the barrier layer is epitaxially grown in a reactor; and
the layer of Si3N4 is epitaxially grown in the reactor after the barrier layer is grown without removing the barrier layer from the reactor.
3. The method of claim 2 wherein the layer of SiO2 is formed to touch the layer of Si3N4 by oxidizing a portion of the layer of Si3N4.
4. The method of claim 3 and further comprising forming spaced-apart metal source and drain regions that touch the barrier layer.
5. The method of claim 4 wherein the barrier layer further includes indium.
6. The method of claim 4 and further comprising forming a channel layer before the barrier layer is formed, the channel layer including GaN, a top surface of the channel layer touching a bottom surface of the barrier layer, the channel layer including a two dimensional electron gas that touches the top surface of the channel layer.
7. The method of claim 6 and further comprising selectively etching the barrier layer to form an exposed region before the layer of Si3N4 is formed.
8. The method of claim 7 and further comprising forming a barrier film to touch the exposed region before the layer of Si3N4 is formed, the barrier film including AlGaN.
9. The method of claim 8 wherein the layer of Si3N4 is formed to touch and lie over the barrier film.
10. The method of claim 6 and further comprising selectively etching the barrier layer and the channel layer to form an exposed region before the layer of Si3N4 is formed.
11. The method of claim 10 and further comprising forming a barrier film to touch the exposed region before the layer of Si3N4 is formed, the barrier film including AlGaN.
12. The method of claim 11 wherein the layer of Si3N4 is formed to touch the barrier film.
13. The method of claim 12 wherein the barrier layer further includes indium, and the barrier film further includes indium.
14. A transistor comprising:
a barrier layer, the barrier layer including AlGaN;
a layer of Si3N4 that touches the barrier layer;
a layer of SiO2 that touches and lies over the layer of Si3N4; and
a metal gate that touches the layer of SiO2, and lies above the layer of SiO2, and the layer of Si3N4.
15. The transistor of claim 14 and further comprising spaced-apart metal source and drain regions that touch the barrier layer.
16. The transistor of claim 15 wherein the barrier layer further includes indium.
17. The transistor of claim 15 and further comprising a channel layer that touches and lies below the barrier layer, the channel layer including GaN, the channel layer including a two dimensional electron gas that touches the top surface of the channel layer.
18. The transistor of claim 17 and further comprising a barrier film that touches and lies below the layer of Si3N4, the barrier film having a thickness that is less than a largest thickness of the barrier layer, the barrier film including AlGaN.
19. The transistor of claim 18 wherein the barrier layer lies laterally adjacent to the layer of Si3N4.
20. The transistor of claim 19 wherein the barrier layer further includes indium.